Designed primarily for wideband large–signal output and driver stages from
100 – 500 MHz.
• Guaranteed Performance @ 500 MHz, 28 Vdc
Output Power — 150 Watts
Power Gain — 10 dB (Min)
Efficiency — 50% (Min)
100% Tested for Load Mismatch at all Phase Angles with VSWR 30:1
• Overall Lower Capacitance @ 28 V
C
— 135 pF
iss
C
— 140 pF
oss
C
— 17 pF
rss
• Simplified AVC, ALC and Modulation
Typical data for power amplifiers in industrial and
commercial applications:
• Typical Performance @ 400 MHz, 28 Vdc
Output Power — 150 Watts
Power Gain — 12.5 dB
Efficiency — 60%
• Typical Performance @ 225 MHz, 28 Vdc
Output Power — 200 Watts
Power Gain — 15 dB
Efficiency — 65%
G
G
D
(FLANGE)
D
MRF275G
150 W, 28 V, 500 MHz
N–CHANNEL MOS
BROADBAND
100 – 500 MHz
RF POWER FET
S
CASE 375–04, STYLE 2
MAXIMUM RATINGS
RatingSymbolValueUnit
Drain–Source VoltageV
Drain–Gate Voltage
(RGS = 1.0 MΩ)
Gate–Source VoltageV
Drain Current — ContinuousI
Total Device Dissipation @ TC = 25°C
Derate above 25°C
Storage Temperature RangeT
Operating Junction TemperatureT
V
DSS
DGR
GS
D
P
D
stg
J
65Vdc
65Vdc
±40Adc
26Adc
400
2.27
–65 to +150°C
200°C
THERMAL CHARACTERISTICS
CharacteristicSymbolMaxUnit
Thermal Resistance, Junction to CaseR
NOTE – CAUTION – MOS devices are susceptible to damage from electrostatic charge. Reasonable precautions in handling and
packaging MOS devices should be observed.
REV 1
θJC
0.44°C/W
1
Watts
W/°C
Page 2
ELECTRICAL CHARACTERISTICS (T
Characteristic
= 25°C unless otherwise noted)
C
OFF CHARACTERISTICS (1)
Drain–Source Breakdown Voltage
(VGS = 0, ID = 50 mA)
Zero Gate Voltage Drain Current
(VDS = 28 V, VGS = 0)
Gate–Source Leakage Current
(VGS = 20 V, VDS = 0)
ON CHARACTERISTICS (1)
Gate Threshold Voltage (VDS = 10 V, ID = 100 mA)V
Drain–Source On–Voltage (VGS = 10 V, ID = 5 A)V
Forward Transconductance (VDS = 10 V, ID = 2.5 A)g
DYNAMIC CHARACTERISTICS (1)
Input Capacitance (VDS = 28 V, VGS = 0, f = 1 MHz)C
Output Capacitance (VDS = 28 V, VGS = 0, f = 1 MHz)C
Reverse Transfer Capacitance (VDS = 28 V, VGS = 0, f = 1 MHz)C
R11.0 kΩ, 1/4 W Resistor
R2, R310 kΩ, 1/4 W Resistor
Z1, Z20.400″ x 0.250″, Microstrip Line
Z3, Z40.870″ x 0.250″, Microstrip Line
Z5, Z60.500″ x 0.250″, Microstrip Line
Unless otherwise noted, all chip capacitors
are ATC Type 100 or Equivalent.
D.U.T.
C6
R1100 Ω, 1/2 W
R21.0 k Ω, 1/2 W
T14:1 Impedance Ratio, RF Transformer
T21:9 Impedance Ratio, RF Transformer.
NOTE: For stability, the input transformer T1 should be loaded
NOTE: with ferrite toroids or beads to increase the common
NOTE: mode inductance. For operation below 100 MHz. The
NOTE: same is required for the output transformer.
T2
Can Be Made of 25 Ω, Semi Rigid Coax,
47–52 Mils O.D.
Can Be Made of 15–18 Ω, Semi Rigid
Coax, 62–90 Mils O.D.
The physical structure of a MOSFET results in capacitors
between the terminals. The metal oxide gate structure determines the capacitors from gate–to–drain (Cgd), and gate–to–
source (Cgs). The PN junction formed during the fabrication
of the MOSFET results in a junction capacitance from drain–
to–source (Cds).
These capacitances are characterized as input (C
put (C
) and reverse transfer (C
oss
) capacitances on data
rss
iss
), out-
sheets. The relationships between the inter–terminal capacitances and those given on data sheets are shown below. The
C
can be specified in two ways:
iss
1. Drain shorted to source and positive voltage at the gate.
2. Positive voltage of the drain in respect to source and zero
volts at the gate. In the latter case the numbers are lower.
However, neither method represents the actual operating conditions in RF applications.
DRAIN
C
ds
SOURCE
C
iss
C
oss
C
rss
= Cgd + C
= Cgd + C
= C
gd
gs
ds
The C
C
gd
GA TE
C
gs
given in the electrical characteristics table was
iss
measured using method 2 above. It should be noted that
C
, C
, C
iss
oss
are measured at zero drain current and are
rss
provided for general information about the device. They are
not RF design parameters and no attempt should be made to
use them as such.
DRAIN CHARACTERISTICS
One figure of merit for a FET is its static resistance in the
full–on condition. This on–resistance, V
DS(on)
, occurs in the
linear region of the output characteristic and is specified under specific test conditions for gate–source voltage and drain
current. For MOSFETs, V
has a positive temperature
DS(on)
coefficient and constitutes an important design consideration
at high temperatures, because it contributes to the power
dissipation within the device.
GATE CHARACTERISTICS
The gate of the MOSFET is a polysilicon material, and is
electrically isolated from the source by a layer of oxide. The
input resistance is very high — on the order of 109 ohms —
resulting in a leakage current of a few nanoamperes.
Gate control is achieved by applying a positive voltage
slightly in excess of the gate–to–source threshold voltage,
V
GS(th)
.
Gate Voltage Rating — Never exceed the gate voltage
rating (or any of the maximum ratings on the front page). Exceeding the rated VGS can result in permanent damage to
the oxide layer in the gate region.
Gate Termination — The gates of this device are essentially capacitors. Circuits that leave the gate open–circuited
or floating should be avoided. These conditions can result in
turn–on of the devices due to voltage build–up on the input
capacitor due to leakage currents or pickup.
Gate Protection — These devices do not have an internal
monolithic zener diode from gate–to–source. If gate protection is required, an external zener diode is recommended.
Using a resistor to keep the gate–to–source impedance
low also helps damp transients and serves another important
function. Voltage transients on the drain can be coupled to
the gate through the parasitic gate–drain capacitance. If the
gate–to–source impedance and the rate of voltage change
on the drain are both high, then the signal coupled to the gate
REV 1
14
Page 15
may be large enough to exceed the gate–threshold voltage
and turn the device on.
HANDLING CONSIDERATIONS
When shipping, the devices should be transported only in
antistatic bags or conductive foam. Upon removal from the
packaging, careful handling procedures should be adhered
to. Those handling the devices should wear grounding straps
and devices not in the antistatic packaging should be kept in
metal tote bins. MOSFETs should be handled by the case
and not by the leads, and when testing the device, all leads
should make good electrical contact before voltage is applied. As a final note, when placing the FET into the system it
is designed for, soldering should be done with grounded
equipment.
DESIGN CONSIDERATIONS
The MRF275G is a RF power N–channel enhancement
mode field–effect transistor (FETs) designed for HF, VHF and
UHF power amplifier applications. M/A-COM RF MOSFETs
feature a vertical structure with a planar design.
M/A-COM Application Note AN211A, FETs in Theory and
Practice, is suggested reading for those not familiar with the
construction and characteristics of FETs.
The major advantages of RF power FETs include high
gain, low noise, simple bias systems, relative immunity from
thermal runaway, and the ability to withstand severely mismatched loads without suffering damage. Power output can
be varied over a wide range with a low power dc control signal.
DC BIAS
The MRF275G is an enhancement mode FET and, therefore, does not conduct when drain voltage is applied. Drain
current flows when a positive voltage is applied to the gate.
RF power FETs require forward bias for optimum performance. The value of quiescent drain current (IDQ) is not critical for many applications. The MRF275G was characterized
at IDQ = 100 mA, each side, which is the suggested minimum
value of IDQ. For special applications such as linear amplification, IDQ may have to be selected to optimize the critical
parameters.
The gate is a dc open circuit and draws no current. Therefore, the gate bias circuit may be just a simple resistive divider network. Some applications may require a more elaborate
bias system.
GAIN CONTROL
Power output of the MRF275G may be controlled from its
rated value down to zero (negative gain) by varying the dc
gate voltage. This feature facilitates the design of manual
gain control, AGC/ALC and modulation systems.
REV 1
15
Page 16
P ACKAGE DIMENSIONS
U
G
12
R
5
K
34
Q
RADIUS 2 PL
0.25 (0.010)B
–B–
M
M
A
T
M
D
E
N
H
–A–
J
SEATING
–T–
PLANE
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
DIM MINMAXMINMAX
A 1.330 1.350 33.79 34.29
B 0.370 0.4109.40 10.41
C 0.190 0.2304.835.84
D 0.215 0.2355.475.96
E 0.050 0.0701.271.77
G 0.430 0.440 10.92 11.18
H 0.102 0.1122.592.84
J0.004 0.0060.110.15
K 0.185 0.2154.835.33
N 0.845 0.875 21.46 22.23
Q 0.060 0.0701.521.78
R 0.390 0.4109.91 10.41
U1.100 BSC27.94 BSC
STYLE 2:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. GATE
5. SOURCE
MILLIMETERSINCHES
CASE 375–04
ISSUE D
Specifications subject to change without notice.
n
North America: Tel. (800) 366-2266, Fax (800) 618-8883
n Asia/Pacific: Tel.+81-44-844-8296, Fax +81-44-844-8298
n