MPIC2131
3
Motorola Power Products Division Advanced Data
RECOMMENDED OPERATING CONDITIONS
The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended conditions. The VS offset rating is tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage
V
B1,2,3
V
S1,2,3
+10 V
S1,2,3
+20 V
High Side Floating Supply Offset Voltage V
S1,2,3
Note 1 VSO+600 V
High Side Floating Output Voltage V
HO1,2,3
V
S1,2,3
V
B1,2,3
V
Fixed Supply Voltage V
CC
10 20 V
Low Side Output Voltage V
LO1,2,3
0 V
CC
V
Low Side Driver Return V
SS
–5 5 V
Logic Input Voltage (HIN–, LIN–, FLT–CLR, SD & ITRIP) V
IN
V
SS
5 V
Fault Output Voltage FAULT– V
SS
V
CC
V
Ambient Temperature T
A
–40 125 °C
Note 1: Logic operational for VS of –5 V to +600 V. Logic state held for VS of –5 V to –VBS.
ELECTRICAL CHARACTERISTICS (T
A
= 25°C unless otherwise specified)
Characteristic
Symbol Min Typ Max Unit
STATIC ELECTRICAL CHARACTERISTICS
V
BIAS
(VCC, V
BS1,2,3
) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to COM and V
SO1,2,3
and are applicable to
the respective output leads: HO1,2,3 or LO1,2,3.
Logic “0” Input Voltage (OUT = LO) V
IH
2.2 – – V
Logic “1” Input Voltage (OUT = HI) V
IL
– – 0.8 V
Logic “0” Fault Clear Input Voltage V
FCLR,IH
2.2 – – V
Logic “1” Fault Clear Input Voltage V
FCLR,IL
– – 0.8 V
SD Input Positive Going Threshold V
SD,TH+
– 1.8 – V
SD Input Negative Going Threshold V
SD,TH–
– 1.5 – V
ITRIP Input Positive Going Threshold V
IT,TH+
– 485 – mV
ITRIP Input Negative Going Threshold V
IT,TH–
– 400 – mV
High Level Output Voltage, V
BIAS–VO
@ VIN = 0 V, IO = 0 A V
OH
– – 100 mV
Low Level Output Voltage, VO @ VIN = 5 V, IO = 0 A V
OL
– – 100 mV
Offset Supply Leakage Current @ V
B1,2,3
= V
S1,2,3
= 600 V I
LK
– – 50 µA
Quiescent VBS Supply Current @ VIN = 0 V or 5 V I
QBS
– 30 – µA
Quiescent VCC Supply Current @ VIN = 0 V or 5 V I
QCC
– 3.0 – mA
Logic “1” Input Bias Current (OUT = HI) @ VIN = 0 V I
IN+
– 190 – µA
Logic “0” Input Bias Current (OUT = LO) @ VIN = 5 V I
IN–
– 100 – µA
“High” ITRIP Bias Current @ ITRIP = 5 V I
TRIP+
– 60 – µA
“Low” ITRIP Bias Current @ ITRIP = 0 V I
TRIP–
– – 50 nA
Logic “1” Fault Clear Bias Current @ FLT–CLR = 0 V I
FCLR+
– 190 – µA
Logic “0” Fault Clear Bias Current @ FLT–CLR = 5 V I
FCLR–
– 100 – µA
Logic “1” Shut Down Bias Current @ SD = 5 V I
SD+
– 60 – µA
Logic “0” Shut Down Bias Current @ SD = 5 V I
SD–
– – 150 nA
VBS Supply Undervoltage Positive Going Threshold V
BSUV+
– 8.6 – V
VBS Supply Undervoltage Negative Going Threshold V
BSUV–
– 8.2 – V
VCC Supply Undervoltage Positive Going Threshold V
CCUV+
– 9.0 – V
VCC Supply Undervoltage Negative Going Threshold V
CCUV–
– 8.7 – V
FAULT – Low On Resistance R
on,FLT
– 55 – Ω
Output High Short Circuit Pulsed Current @ V
out
= 0 V, Vin = 0 V, PW ≤ 10 µs I
O+
200 250 – mA
Output Low Short Circuit Pulsed Current @ V
out
= 15 V, Vin = 5 V, PW ≤ 10 µs I
O–
420 500 – mA