Page 1
SEMICONDUCTOR TECHNICAL DATA
1
REV 1
Motorola, Inc. 1996
10/96
The MPC946 is a low voltage CMOS, 10 output clock buffer. The 10
outputs can be configured into a standard fanout buffer or into 1X and
1/2X combinations. The ten outputs were designed and optimized to drive
50Ω series or parallel terminated transmission lines. With output to output
skews of 350ps the MPC946 is an ideal clock distribution chip for
synchronous systems which need a tight level of skew from a large
number of outputs. For a similar product with more outputs consult the
MPC949 data sheet.
• Clock Distribution for Pentium Systems with PCI
• 2 Selectable LVCMOS/LVTTL Clock Inputs
• 350ps Output to Output Skew
• Drives up to 20 Independent Clock Lines
• Maximum Input/Output Frequency of 150MHz
• Tristatable Outputs
• 32–Lead TQFP Packaging
• 3.3V VCC Supply
With an output impedance of approximately 7Ω, in both the HIGH and
the LOW logic states, the output buffers of the MPC946 are ideal for
driving series terminated transmission lines. More specifically each of the
10 MPC946 outputs can drive two series terminated transmission lines.
With this capability, the MPC946 has an effective fanout of 1:20 in
applications using point–to–point distribution schemes.
The MPC946 has the capability of generating 1X and 1/2X signals from
a 1X source. The design is fully static, the signals are generated and
retimed inside the chip to ensure minimal skew between the 1X and 1/2X
signals. The device features selectability to allow the user to select the
ratio of 1X outputs to 1/2X outputs.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected.
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced
HIGH.
The MPC946 is fully 3.3V compatible. The 32–lead TQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
Pentium is a trademark of Intel Corporation.
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
LOW VOLTAGE
1:10 CMOS CLOCK DRIVER
Page 2
MPC946
MOTOROLA TIMING SOLUTIONS
BR1333 — Rev 6
2
VCCa
Qa2
GNDa
Qa1
VCCa
Qa0
GNDa
Qc3
GNDc
Qc2
VCCc
Qc1
GNDc
Qc0
VCCc
GNDb
Qb0
VCCb
Qb1
GNDb
Qb2
VCCb
VCCc
TCLK_Sel
VCCI
TCLK0
TCLK1
Dsela
Dselb
Dselc
GNDI
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MPC946
Pinout: 32–Lead TQFP (Top View)
FUNCTION TABLES
TCLK_Sel Input
0
1
TCLK0
TCLK1
Dselx Outputs
0
1
1x
1/2x
MR/OE Outputs
0
1
Enabled
Hi–Z
LOGIC DIAGRAM
TCLK1
Qa0:2
TCLK0
TCLK_Sel
3
R
÷
2
MR/OE
÷
1
Dsela
Qb0:2
3
Dselb
Qc0:3
4
Dselc
MR/OE
0
1
0
1
0
1
0
1
(Int Pull Up)
(Int Pull Up)
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
(Int Pull Down)
Page 3
MPC946
TIMING SOLUTIONS
BR1333 — Rev 6
3 MOTOROLA
ABSOLUTE MAXIMUM RATINGS*
Symbol Parameter Min Max Unit
V
CC
Supply Voltage –0.3 4.6 V
V
I
Input Voltage –0.3 VDD + 0.3 V
I
IN
Input Current (CMOS Inputs) ±20 mA
T
Stor
Storage Temperature Range –40 125 °C
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
DC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V)
Symbol Characteristic Min Typ Max Unit Condition
V
IH
Input HIGH Voltage 2.0 3.6 V
V
IL
Input LOW Voltage 0.8 V
V
OH
Output HIGH Voltage 2.5 V IOH = –20mA
1
V
OL
Output LOW Voltage 0.4 V IOL = 20mA
1
I
IN
Input Current ±120 µA Note 2.
I
CC
Maximum Quiescent Supply Current 70 85 mA
C
IN
Input Capacitance 4 pF
C
pd
Power Dissipation Capacitance 25 pF Per Output
1. The MPC946 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge (see Applications
Info section).
2. IIN current is a result of internal pull–up/pull–down resistors.
AC CHARACTERISTICS (TA = 0° to 70°C, VCC = 3.3V ±0.3V)
Symbol Characteristic Min Typ Max Unit Condition
F
max
Maximum Input Frequency 150 MHz Note 1.
t
PLH
,
t
PHL
Propagation Delay TCLK to Q 5.0
4.5
8.0
7.5
12.0
11.5
ns Note 1., 3.
t
sk(o)
Output–to–Output Skew
Same Frequency Outputs
Different Frequency Outputs
Same Frequency Outputs
Different Frequency Outputs
350
350
350
450
ps Note 1., 3.
F
max
< 100MHz
F
max
< 100MHz
F
max
> 100MHz
F
max
> 100MHz
t
sk(pr)
Part–to–Part Skew 2.0 4.5 ns Note 2.
t
PZL
, t
PZH
Output Enable Time 3 11 ns Note 3.
t
PLZ
, t
PHZ
Output Disable Time 3 11 ns Note 3.
tr, t
f
Output Rise/Fall Time 0.1 0.5 1.0 ns 0.8V to 2.0V , Note 3.
1. Driving 50Ω transmission lines.
2. Part–to–part skew at a given temperature and voltage.
3. Termination is 50Ω to VCC/2.
Page 4
MPC946
MOTOROLA TIMING SOLUTIONS
BR1333 — Rev 6
4
APPLICATIONS INFORMATION
Driving Transmission Lines
The MPC946 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 10Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC946 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 1 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC946 clock
driver is effectively doubled due to its capability to drive
multiple lines.
Figure 1. Single versus Dual Transmission Lines
7
Ω
IN
MPC946
OUTPUT
BUFFER
RS = 43
Ω
ZO = 50
Ω
OutA
7
Ω
IN
MPC946
OUTPUT
BUFFER
RS = 43
Ω
ZO = 50
Ω
OutB0
RS = 43
Ω
ZO = 50
Ω
OutB1
The waveform plots of Figure 2 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC946 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC946. The output waveform
in Figure 2 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
Figure 2. Single versus Dual Waveforms
TIME (nS)
VOLTAGE (V)
3.0
2.5
2.0
1.5
1.0
0.5
0
2 4 6 8 10 12 14
OutB
tD = 3.9386
OutA
tD = 3.8956
In
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 3 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 3. Optimized Dual Line Termination
7
Ω
MPC946
OUTPUT
BUFFER
RS = 36
Ω
ZO = 50
Ω
RS = 36
Ω
ZO = 50
Ω
7Ω + 36Ω k 36Ω = 50Ω k 50Ω
25Ω = 25Ω
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
Page 5
MPC946
TIMING SOLUTIONS
BR1333 — Rev 6
5 MOTOROLA
OUTLINE DIMENSIONS
FA SUFFIX
TQFP PACKAGE
CASE 873A-02
ISSUE A
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
DF
METAL
SECTION AE–AE
G
SEATING
PLANE
R
Q
_
W
K
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
DIMAMIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B 7.000 BSC 0.276 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC 0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028
M 12 REF 12 REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
Q 1 5 1 5
R 0.150 0.250 0.006 0.010
V 9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
__
____
DETAIL AD
A1
B1
V1
4X
S
4X
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S 9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF
9
–T–
–Z–
–U–
T–U0.20 (0.008) ZAC
T–U0.20 (0.008) ZAB
0.10 (0.004) AC
–AC–
–AB–
M
_
8X
–T–, –U–, –Z–
T–U
M
0.20 (0.008) ZAC
Page 6
MPC946
MOTOROLA TIMING SOLUTIONS
BR1333 — Rev 6
6
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MPC946/D
*MPC946/D*
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