Page 1
SEMICONDUCTOR TECHNICAL DATA
"
!
The MPC940L is a 1:18 low voltage clock distribution chip with 2.5V
LVCMOS output capabilities. The device features the capability to select
either a differential L VPECL or an L VTTL/ L VCMOS compatible input. The
18 outputs are 2.5V LVCMOS compatible and feature the drive strength
to drive 50Ω series or parallel terminated transmission lines. With
output–to–output skews of 150ps, the MPC940L is ideal as a clock
distribution chip for the most demanding of synchronous systems. The
2.5V outputs also make the device ideal for supplying clocks for a high
performance Pentium II microprocessor based design.
• LVPECL or LVCMOS/LVTTL Clock Input
• 2.5V LVCMOS Outputs for Pentium II Microprocessor Support
• 150ps Maximum Targeted Output–to–Output Skew
• Maximum Output Frequency of 250MHz
• 32–Lead TQFP Packaging
• Dual V
With a low output impedance (≈30Ω), in both the HIGH and LOW logic
states, the output buffers of the MPC940L are ideal for driving series
terminated transmission lines. With this drive capability, the MPC940L
provides enough copies of low skew clocks for most high performance
synchronous systems.
The differential LVPECL inputs of the MPC940L allow the device to interface directly with a LVPECL fanout buffer like the
MC100EP111 to build very wide clock fanout trees or to couple to a high frequency clock source. The LVCMOS/LVTTL input
provides a more standard interface for applications requiring only a single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a test clock interface as well as the primary system clock. A logic HIGH
on the LVCMOS_CLK_Sel pin will select the TTL level clock input.
The MPC940L is a dual supply device. The core VCC power pins (VCCI) require 3.3V with the output VCC pins (VCCO)
requiring 2.5V. The 32–lead TQFP package was chosen to optimize performance, board space and cost of the device. The
32–lead TQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
Supply Voltage, 3.3V Core and 2.5V Output
CC
LOW VOLTAGE
1:18 CLOCK
DISTRIBUTION CHIP
FA SUFFIX
32–LEAD TQFP PACKAGE
CASE 873A–02
Pentium II is a trademark of Intel Corporation.
This document contains information on a new product. Specifications and information herein are subject to
change without notice.
10/97
Motorola, Inc. 1997
1
REV 0
Page 2
MPC940L
LOGIC DIAGRAM
GNDO
Q5
Q4
Q3
VCCO
PECL_CLK
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_Sel
0
1
Pinout: 32–Lead TQFP (Top View)
Q6
Q7
Q8
VCCIQ9Q10
24 23 22 21 20 19 18 17
25
26
27
28
29
MPC940L
Q0
16
Q1–Q16
Q17
Q11
GND
16
15
14
13
12
VCCO
Q12
Q13
Q14
GNDO
FUNCTION TABLE
LVCMOS_CLK_Sel Input
0
1
PECL_CLK
LVCMOS_CLK
Q2
Q1
Q0
30
31
32
12345678
GNDO
GNDI
PECL_CLK
LVCMOS_CLK
LVCMOS_CLK_Sel
VCCI
PECL_CLK
11
10
9
VCCO
Q15
Q16
Q17
POWER SUPPLY VOLTAGES
Supply Pin
VCCI
VCCO
V oltage Level
3.3V ± 5%
2.5V ± 5%
MOTOROLA TIMING SOLUTIONS
2
BR1333 — Rev 6
Page 3
MPC940L
ABSOLUTE MAXIMUM RATINGS*
Symbol Parameter Min Max Unit
V
CC
V
I
I
IN
T
Stor
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.
Supply Voltage –0.3 3.6 V
Input Voltage –0.3 VDD + 0.3 V
Input Current ±20 mA
Storage Temperature Range –40 125 °C
DC CHARACTERISTICS (TA = 0° to 70°C, V
Symbol Characteristic Min Typ Max Unit Condition
V
IH
V
IL
V
PP
V
CMR
V
OH
V
OL
I
IN
C
IN
C
pd
I
CC
1. The MPC940L outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge.
Input HIGH Voltage PECL_CLK
Input LOW Voltage PECL_CLK
Peak–to–Peak Input Voltage PECL_CLK 300 1000 mV
Common Mode Range PECL_CLK VCC–1.6 VCC–0.6 V
Output HIGH Voltage 2.5 V IOH = –16mA, Note 1.
Output LOW Voltage 0.5 V IOH = 16mA, Note 1.
Input Current ±100 µA
Input Capacitance 4 pF
Power Dissipation Capacitance 8 pF Per Output
Maximum Quiescent Supply Current I
AC CHARACTERISTICS (TA = 0° to 70°C, V
Symbol Characteristic Min Typ Max Unit Condition
F
max
t
pd
t
sk(o)
t
sk(pr)
t
pwo
tr, t
f
1. Driving 50Ω transmission lines
2. Part–to–part skew at a given temperature and voltage
3. Final specification limits will be determined from matrix lot material. 800ps is the “best estimate” based on initial material and experience with
previous products.
Maximum Input Frequency 250 MHz Note 1.
Propagation Delay PECL_CLK to Q
Output–to–Output Skew 150 ps Note 1.
Part–to–Part Skew PECL_CLK to Q
Output Pulse Width 45 55 p% Note 1.,
Output Rise/Fall Time 0.20 1.0 ns 0.8V to 2.0V
= 3.3V ±5%; V
CCI
Other
Other
CCL
I
CCH
= 3.3V ±5%; V
CCI
TTL_CLK to Q
TTL_CLK to Q
= 2.5V ±5%)
CCO
2.135
2.0
1.49 1.825
70
140
= 2.5V ±5%)
CCO
2.0
2.3
800
800
2.42
3.60
0.8
V
V
mA
ns Note 1.
ps Notes 2., 3.
Measured at VCC/2
TIMING SOLUTIONS
BR1333 — Rev 6
3 MOTOROLA
Page 4
MPC940L
OUTLINE DIMENSIONS
FA SUFFIX
TQFP PACKAGE
CASE 873A–02
ISSUE A
SEATING
PLANE
9
C
–T–
B1
–AB–
–AC–
E
A
A1
32
1
4X
25
T–U0.20 (0.008) ZAB
–T–, –U–, –Z–
–U–
VB
AE
P
DETAIL Y
8
9
–Z–
S1
S
G
0.10 (0.004) AC
_
M
8X
H
W
R
K
X
DETAIL AD
17
4X
_
Q
V1
DETAIL AD
0.250 (0.010)
GAUGE PLANE
T–U0.20 (0.008) ZAC
BASE
METAL
N
DF
J
SECTION AE–AE
T–U
M
0.20 (0.008) ZAC
AE
DETAIL Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
MILLIMETERS
DIMAMIN MAX MIN MAX
7.000 BSC 0.276 BSC
A1 3.500 BSC 0.138 BSC
B 7.000 BSC 0.276 BSC
B1 3.500 BSC 0.138 BSC
C 1.400 1.600 0.055 0.063
D 0.300 0.450 0.012 0.018
E 1.350 1.450 0.053 0.057
F 0.300 0.400 0.012 0.016
G 0.800 BSC 0.031 BSC
H 0.050 0.150 0.002 0.006
J 0.090 0.200 0.004 0.008
K 0.500 0.700 0.020 0.028
__
M 12 REF 12 REF
N 0.090 0.160 0.004 0.006
P 0.400 BSC 0.016 BSC
____
Q 1 5 1 5
R 0.150 0.250 0.006 0.010
S 9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
V 9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC
W 0.200 REF 0.008 REF
X 1.000 REF 0.039 REF
INCHES
MOTOROLA TIMING SOLUTIONS
4
BR1333 — Rev 6
Page 5
MPC940L
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
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Opportunity/Affirmative Action Employer.
How to reach us:
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5 MOTOROLA
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MPC940L/D
BR1333 — Rev 6
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