Page 1
NXP Semiconductors
416 TEPBGA
27mm x 27 mm
512 TEPBGA
25 mm x 25 mm
Data Sheet: Technical Data
MPC5777M Microcontroller
Data Sheet
Document Number: MPC5777M
Rev. 6, 06/2016
MPC5777M
• Three main CPUs, single issue, 32-bit CPU core complexes
(e200z7), one of which is a dedicated lockstep core.
– Power Architecture
compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 16 KB I-Cache and 4 KB D-Cache
• I/O Processor, dual issue, 32-bit CPU core complex
(e200z4), with
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length
encoding (VLE), encoding a mix of 16-bit and 32-bit
instructions, for code size footprint reduction
– Single-precision floating point operations
– Lightweight Signal Processing Auxiliary Processing
Unit (LSP APU) instruction support for digital signal
processing (DSP)
– 16 KB Local instruction RAM and 64 KB local data
RAM
– 8 KB I-Cache
• 8640 KB on-chip flash
– Supports read during program and erase operations, and
multiple blocks allowing EEPROM emulation
• 404 KB on-chip general-purpose SRAM including 64 KB
standby RAM (+ 192 KB data RAM included in the
CPUs). Of this 404 KB, 64 KB can be powered by a
separate supply so the contents of this portion can be
preserved when the main MCU is powered down.
• Multichannel direct memory access controllers (eDMA): 2
x 64 channels per eDMA (128 channels total)
• Triple Interrupt controller (INTC)
®
embedded specification
– Dual phase-locked loops with stable clock domain for
peripherals and FM modulation domain for
computational shell
• Dual crossbar switch architecture for concurrent access to
peripherals, flash, or RAM from multiple bus masters with
end-to-end ECC
• Hardware Security Module (HSM) to provide robust
integrity checking of flash memory
• System Integration Unit Lite (SIUL)
• Boot Assist Module (BAM) supports factory programming
using serial bootload through ‘UART Serial Boot Mode
Protocol’. Physical interface (PHY) can be:
– UART/LIN
–CAN
• GTM104 — generic timer module
• Enhanced analog-to-digital converter system with
– Twelve separate 12-bit SAR analog converters
– Ten separate 16-bit Sigma-Delta analog converters
• Eight deserial serial peripheral interface (DSPI) modules
• Two Peripheral Sensor Interface (PSI5) controllers
• Three LIN and three UART communication interface
(LINFlexD) modules (6 total)
– LINFlexD_0 is a Master/Slave
– LINFlexD_1, LINFlexD_2, LINFlexD_14,
LINFlexD_15, and LINFlexD_16 are Masters
• Four modular controller area network (MCAN) modules
and one time-triggered controller area network
(M-TTCAN)
• External Bus Interface (EBI)
– Dual routing of accesses to EBI
– Access path determined by access address
– Access path downstream of PFLASH controller
– Allows EBI accesses to share buffer and prefetch
capabilities of internal flash
– Allows internal flash accesses to be remapped to
memories connected to EBI
NXP reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
Page 2
Ta ble of Contents
1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.3 Device feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . .10
2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Pin/ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.2.1 Power supply and reference voltage pins/balls .15
2.2.2 System pins/balls. . . . . . . . . . . . . . . . . . . . . . . .16
2.2.3 LVDS pins/balls . . . . . . . . . . . . . . . . . . . . . . . . .17
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .21
3.3 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . .23
3.4 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.5 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . .27
3.6 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3.6.1 I/O input DC characteristics. . . . . . . . . . . . . . . .31
3.6.2 I/O output DC characteristics. . . . . . . . . . . . . . .35
3.7 I/O pad current specification . . . . . . . . . . . . . . . . . . . . .42
3.8 Reset pad (PORST, ESR0) electrical characteristics . .45
3.9 Oscillator and FMPLL . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.10 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.10.1 ADC input description . . . . . . . . . . . . . . . . . . . .53
3.10.2 SAR ADC electrical specification. . . . . . . . . . . .54
3.10.3 S/D ADC electrical specification . . . . . . . . . . . .58
3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . .67
3.12 LVDS Fast Asynchronous Serial Transmission
(LFAST) pad electrical characteristics . . . . . . . . . . . . .67
3.12.1 LFAST interface timing diagrams . . . . . . . . . . .68
3.12.2 LFAST and MSC/DSPI LVDS interface
electrical characteristics . . . . . . . . . . . . . . . . . .69
3.12.3 LFAST PLL electrical characteristics. . . . . . . . .72
3.13 Aurora LVDS electrical characteristics . . . . . . . . . . . . .73
3.14 Power management: PMC, POR/LVD, sequencing . . .75
3.14.1 Power management electrical characteristics . .75
3.14.2 Power management integration . . . . . . . . . . . . 75
3.14.3 3.3 V flash supply. . . . . . . . . . . . . . . . . . . . . . . 76
3.14.4 Device voltage monitoring . . . . . . . . . . . . . . . . 77
3.14.5 Power up/down sequencing. . . . . . . . . . . . . . . 79
3.15 Flash memory electrical characteristics. . . . . . . . . . . . 80
3.15.1 Flash memory program and erase
specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 80
3.15.2 Flash memory FERS program and
erase specifications . . . . . . . . . . . . . . . . . . . . . 82
3.15.3 Flash memory Array Integrity and Margin
Read specifications . . . . . . . . . . . . . . . . . . . . . 83
3.15.4 Flash memory module life specifications . . . . . 84
3.15.5 Data retention vs program/erase cycles. . . . . . 84
3.15.6 Flash memory AC timing specifications . . . . . . 85
3.15.7 Flash read wait state and address pipeline
control settings. . . . . . . . . . . . . . . . . . . . . . . . . 85
3.16 AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
3.16.1 Debug and calibration interface timing. . . . . . . 86
3.16.2 DSPI timing with CMOS and LVDS pads. . . . . 94
3.16.3 FEC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.16.4 FlexRay timing . . . . . . . . . . . . . . . . . . . . . . . . 115
3.16.5 PSI5 timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.16.6 UART timing. . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.16.7 External Bus Interface (EBI) Timing. . . . . . . . 119
3.16.8 I2C timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.16.9 GPIO delay timing . . . . . . . . . . . . . . . . . . . . . 124
3.16.10Package characteristics. . . . . . . . . . . . . . . . . 124
3.17 416 TEPBGA (production) case drawing . . . . . . . . . 125
3.18 416 TEPBGA (emulation) case drawing. . . . . . . . . . 127
3.19 512 TEPBGA case drawing . . . . . . . . . . . . . . . . . . . 130
3.20 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . 132
3.20.1 General notes for specifications at
maximum junction temperature . . . . . . . . . . . 132
4 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . 137
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors2
Page 3
— Access path via dedicated AXBS slave port
– Avoids contention with other memory accesses
• Two Dual-channel FlexRay controllers
• Nexus development interface (NDI) per IEEE-ISTO 5001-2003 standard, with some support for 2010 standard
• Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1)
• Self-test capability
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 3
Page 4
Introduction
1 Introduction
1.1 Document overview
This document provides electrical specifications, pin assignments, and package diagrams for the MPC5777M series of
microcontroller units (MCUs). For functional characteristics, see the MPC5777M Microcontroller Reference Manual.
1.2 Description
This family of MCUs is targeted at automotive powertrain controller and chassis control applications from single cylinder
motorcycles at the very bottom end; through 4 to 8 cylinder gasoline and diesel engines; transmission control; steering and
breaking applications; to high end hybrid and advanced combustion systems at the top end.
Many of the applications are considered to be functionally safe and the family is designed to achieve ISO26262 ASIL-D
compliance.
1.3 Device feature
Table 1. MPC5777M feature
Feature MPC5777M
Process 55 nm
Main processor Core e200z7
Number of main cores 2
Number of checker cores 1
Local RAM (per main core) 16 KB Instruction
64 KB Data
Single precision floating point Yes
LSP No
VLE Yes
Cache 16 KB Instruction
4 KB Data
I/O processor Core e200z4
Local RAM 16 KB instruction
64 KB Data
Single precision floating point Yes
LSP Yes
VLE Yes
Cache 8 KB instruction
Main processor frequency 300 MHz
I/O processor frequency 200 MHz
MMU entries 0
1
MPU Yes
Semaphores Yes
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors4
Page 5
Table 1. MPC5777M feature (continued)
Feature MPC5777M
CRC channels 2
Introduction
Software watchdog timer
4 (3/1)
(Task SWT/Safety SWT)
Core Nexus class 3+
Sequence processing unit (SPU) Yes
Debug and calibration interface (DCI) / run control
Yes
module
System SRAM 404 KB
Flash memory 8640 KB
Flash memory fetch accelerator 4 256 bit
Data flash memory (EEPROM) 8 64 KB
+ 2 16 KB
Flash memory overlay RAM 16 KB
External bus 32 bit
Calibration interface 64-bit IPS Slave
DMA channels 2 64
DMA Nexus Class 3+
LINFlex (UART/MSC) 6 (3/3)
MCAN/TTCAN 4/1
DSPI
8 (4/3/1)
(SPI/MSC/sync SCI)
Microsecond bus downlink Yes
SENT bus 15
2
C 2
I
PSI5 bus 5
PSI5-S UART-to-PSI5 interface Yes
FlexRay 2 dual channel
Ethernet MII / RMII
Zipwire
(SIPI / LFAST2) Interprocessor Communication
High speed
Interface
System timers 8 PIT channels
3 AUTOSAR
®
(STM)
64-bit PIT
BOSCH
GTM Timer
3
Yes
GTM RAM 58 KB
Interrupt controller 727 sources
ADC (SAR) 12
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 5
Page 6
Introduction
ADC (SD) 10
Temperature sensor Yes
Self test controller Yes
PLL Dual PLL with FM
Integrated linear voltage regulator None
External power supplies 5 V
Low-power modes Stop mode
Packages • 416 TEPBGA
1
Includes four user-programmable CPU cores and one safety core. The main computational shell consists of
dual e200z7 CPUs operating at 300 MHz with a third identical core running as a safety checker core in delayed
lockstep mode with one of the dual e200z7 cores. The I/O subsystem includes a CPU targeted at managing
the peripherals. This is an e200z4 CPU running at 200 MHz. The fifth CPU is an e200z0 running at 100 MHz
and is embedded in the Hardware Security Module. All CPUs are compatible with the Power Architecture.
2
LVDS Fast Asynchronous Serial Transmission
3
BOSCH® is a registered trademark of Robert Bosch GmbH.
4
416 TEPBGA package supports development and production applications with the same package footprint.
5
512 TEPBGA package supports development and production applications with the same package footprint.
Table 1. MPC5777M feature (continued)
Feature MPC5777M
7
3.3 V
1.2 V
Slow mode
4
• 512 TEPBGA
5
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors6
Page 7
1.4 Block diagram
The figures below show the top-level blo c k diagrams.
MPC5777M Microcontroller Data Sheet, Rev. 6
Introduction
NXP Semiconductor s7
Page 8
NXP Semiconductors 8
MPC5777M Microcontroller Data Sheet, Rev. 6
Figure 1. Block diagram
Introduction
Page 9
Package pinouts and signal descriptions
Peripheral Bus (AIPS_0)
Peripheral
Clust er A
WKPU
LVIIO
LVIFLASH
LVI 1.2V
HVI 1.2V
PMC
PCU
RGM
CGM
RCOSC_DIG_0
OSC_DIG
CMU_PLL
ME
SUIL2
2 x SIPI
2 x LFAST
CFLASH_0
PAS S
SSCM
BAF
PLL
PRAM
PFLASH
INTC_0
4 x SWT
3 x STM
2 x SMPU
3 x SAR ADC
PSI5_0
FLEXRAY_0
SENT_0
IIC_0
5 x DSPI
4 x LINFlexD
4 x MCAN
TTCAN_0
HSM INTERFACE
DTS
JDC
SRAM CAN
5 x SD ADC
2 x DMA
FEC
GTM
2 x LINFlexD
5 x SD ADC
9 x SAR ADC
PSI5_1
SENT_1
3 x DSPI
12 x CMU
CRC_1
FCCU
Peripheral Bus (AIPS_1)
Peripheral
Clust er B
JTAGM
STCU2
MEMU
IMA CRC_0
10 x DMAMUX
2 x PIT_RTCAT X
SEMA4
FLEXRAY_1
IIC_1
TDM
PCM
2 x AXBS
EBI
2 x XBIC
TSENS
PSI5_S_0
2 Package pinouts and signal descriptions
See the MPC5777M Microcontroller Reference Manual for signal information.
NXP Semiconductors 9
Figure 2. Periphery allocation
MPC5777M Microcontroller Data Sheet, Rev. 6
Page 10
NXP Semiconductors 10
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2.1 Package pinouts
The BGA ballmap package pinouts for the 416 and 512 production and emulation devices are show n in the following figures.
MPC5777M Microcontroller Data Sheet, Rev. 6
Figure 3. 416-ball BGA production device pinout (top view)
Package pinouts and signal descriptions
Page 11
Package pinouts and signal descriptions
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+
:
WEϵ WEϲ W ϯ s^^ͺ,s W/ϭϰ W&ϭϬ W&ϭϭ W&ϭϮ
:
<
WEϭϭ WEϭϬ WEϴ
sͺ,sͺ
/KͺD/E
s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s W&ϵ W,ϱ W,ϲ W:ϵ
<
>
WEϭϱ WEϭϰ WEϭϯ WEϭϮ s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ,s W&ϴ W:ϯ W: ϰ
>
D
WϬ WϬ Wϭ WϮ s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s
sͺ,sͺ/
Kͺ/
Wtϭϰ Wtϭϱ W:Ϯ
D
E
W'Ϭ Wϰ WϮ Wϭ s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s WtϭϬ Wtϭϭ WtϭϮ Wtϭϯ
E
W
W/ϵ W/ϴ WYϭ WYϮ dyϯW s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s
sͺ,sͺ
/Kͺ
sͺ>s Wtϳ Wtϴ Wtϵ
W
Z
sͺ>sͺ
WYϬ WϭϮ
sͺ>sͺ
dyϯE s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s E s^^ͺ,s Wtϰ Wtϱ Wtϲ
Z
d
W<ϭ Wϯ Wϭϯ s^^ͺ,s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>ss^^ͺ>s
sͺ,sͺ/
Kͺ/
Wtϭ WtϮ Wtϯ
d
h
W<Ϭ WZϭϰ W<Ϯ W<ϯ dyϮ E dyϮW dyϭE dyϭW dyϬE dyϬ W ><E ><W WtϬ Wsϭϯ Wsϭϰ Wsϭϱ
h
s
WZϭϱ WZϭϮ Wϭϯ WϭϮ sͺ>s WsϭϬ Wsϭϭ WsϭϮ
s
t
WZϭϯ WZϭϬ W/ϭ
sͺ,sͺ
Zͺ
s^^ͺ,s Wsϳ Wsϴ Wsϵ
t
z
WZϭϭ WZϴ W/Ϭ
s^^ͺ,sͺ
Zͺ
sͺ,sͺ/
Kͺ/
Wsϯ Wsϰ Wsϱ
z
WZϵ W/ϱ Wϭϯ WZϲ WsϮ Wsϭ Wzϰ WsϬ
W/ϯ W/ϰ WZϳ Wϭϰ s ͺ>s WdϮ Wdϳ WdϭϮ
$&
W/Ϯ Wϭϭ W'ϴ Wϭϱ WϬ
s^^ͺ,sͺ
ZͺϮ
W'ϲ Wϲ W>ϵ W>ϭϬ W/ϭϯ W&ϭ W>ϭϰ Wϭ ϱ WϭϬ
sͺ,sͺ
/KͺD/E
W&ϳ
sͺ,sͺ
/Kͺ&>y
s^^ͺ,s sͺ>s E
sͺ,sͺ
/Kͺ&>y
s^^ͺ,s Wdϯ Wdϴ Wdϭϯ
$&
$'
Wϰ WZϬ W'ϳ W<ϭϬ Wϭ
sͺ,sͺ
ZͺϮ
W'ϱ Wϳ s^dz W>ϭϮ W/ϭϮ W&Ϭ W>ϭϱ W:ϲ Wϭϭ
sͺ,sͺ
/KͺD/E
W&ϲ W^Ϭ W^ϯ W^ϲ W^ϵ W^ϭϮ W^ϭϰ Wdϰ Wdϵ Wdϭϰ
$'
$(
WZϭ W/ϳ W'ϭϮ WϮ
sͺ,sͺ
sͺ
WZϮ WZϰ
s^^ͺ,sͺ
Zͺ^
sͺ,sͺ
sͺ^
W>ϭϯ W/ϭϭ Wϵ W:Ϭ Wϵ Wϴ
sͺ,sͺ
/KͺD/E
W:ϳ W^ϭ W^ϰ W^ϳ W^ϭϬ W^ϭϯ W^ϭϱ Wdϱ WdϭϬ Wdϭϱ
$(
$)
E W/ϲ W'ϭϭ Wϯ
s^^ͺ,sͺ
sͺ
WZϯ WZϱ
sͺ,sͺ
Zͺ^
s^^ͺ,sͺ
sͺ^
W>ϭϭ W/ϭϬ WϭϬ W: ϭ Wϴ Wϯ
sͺ,sͺ
/KͺD/E
W:ϱ W^Ϯ W^ϱ W^ϴ W^ϭϭ WdϬ Wdϭ Wdϲ Wdϭϭ E
$)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductor s11
Figure 4. 416-ball BGA emulation device pinout (top view)
Page 12
NXP Semiconductors 12
ϭϮϯϰϱϲϳϴϵϭϬϭϭϭϮϭϯϭϰϭϱϭϲϭϳϭϴϭϵϮϬϮϭϮϮϮϯϮϰϮϱϮϲϮϳϮϴϮϵϯϬ
sͺ,sͺ
/KͺD/E
E E WyϬ WDϭϱ WEϬ E E E Wyϰ Wyϯ Wyϭ WYϭϯ WYϭϭ WYϵ E WYϳ WYϱ WYϯ E Wyϭϭ Wyϵ Wyϳ E E E E
sͺ,sͺ
/KͺD/E
E s^^ͺ,s
sͺ,sͺ
/KͺD/E
E WDϭϰ WDϭϯ WDϭϮ WDϭϭ E E WyϮ WYϭϱ WYϭϰ WYϭϮ WYϭϬ WYϴ E WYϲ WYϰ E E WyϭϬ Wyϴ Wyϲ Wyϱ E E
sͺ,sͺ
/KͺD/E
s^^ͺ,s s^^ͺ,s
E E E E
E E E E
E E E E
&
WEϮ WEϭ s^^ͺ,s
sͺ,sͺ
/KͺD/E
W,ϭϯ W&Ϯ W&ϱ WDϭϬ W,ϭϱ Wϭϭ Wϭϯ WϭϮ WϬ WϮ W,ϵ W,ϯ Wϭϭ WDϵ WϬ Wϭ
sͺ,sͺ/
KͺD/E
s^^ͺ,s E E
&
'
WEϰ WEϯ Wϭϰ s^^ͺ,s
sͺ,sͺ
/KͺD/E
W,ϭϮ W&ϯ W,ϭϰ W&ϰ WϭϬ WϭϮ Wϭϱ Wϭ Wϯ W,ϰ WϭϬ Wϭϭ WϭϬ Wϭϯ
sͺ,sͺ
/KͺD/E
s^^ͺ,s WϮ E E
'
,
E E Wϵ Wϭϱ WϭϮ Wϵ s^^ͺ,s s^^ͺ,s
,
:
E WEϱ Wϳ Wϴ s^^ͺ,s
sͺ,sͺ
/Kͺ&>y
WDϮ WDϬ W<ϭϰ Wϭϰ WDϲ W,ϳ W,ϴ W,ϭϬ W,ϭ W,Ϭ
sͺ,sͺ
&>
s^^ͺ,s Wϱ Wϴ
sͺ,sͺ
/Kͺ/
sͺ,sͺ
/Kͺ/
:
<
WEϲ WEϳ Wϱ Wϲ W>ϭ s^^ͺ,s WDϯ WDϭ W<ϭϱ WDϰ WDϱ WDϳ WDϴ W,Ϯ W'ϭϱ
sͺ,sͺ
&>
s^^ͺ,s Wϲ Wϳ Wϰ Wtϭϰ Wtϭϱ
<
>
WEϴ WEϵ Wϯ Wϰ W>Ϯ W>Ϭ ^ZϬ W'ϭϯ W'ϭϰ Wϱ WtϭϮ Wtϭϯ
>
D
WEϭϭ WE ϭϬ WϮ Wϭ W>ϯ W>ϰ E s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s sͺ>s Wϰ WKZ^d W,ϭϭ W&ϭϱ WtϭϬ Wtϭϭ
D
E
WEϭϯ WE ϭϮ WϬ WϬ W>ϲ W>ϱ E s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s sͺ>s Wϵ Wϴ d^dDK W&ϭϰ Wtϴ Wtϵ
E
W
WEϭϱ WEϭϰ Wϭ WϮ WϭϮ W>ϳ s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s Wϲ W/ϭϱ Wϳ Wϭϰ Wtϲ Wtϳ
W
Z
E E Wϭϯ Wϰ W ϯ W'Ϭ E s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s E Wϳ W/ϭϰ W&ϭϯ Wϲ Wtϰ Wtϱ
Z
d
W>ϴ WYϭ W/ϴ W/ϵ W<Ϭ W< ϭ E s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s E W<ϭϯ W<ϭϮ Wϱ
s^^ͺ,sͺ
K^
WtϮ Wtϯ
d
h
WYϮ WY Ϭ W'Ϯ W'ϭ W<Ϯ W<ϯ s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s W:ϭϱ W:ϭϰ yd> yd> WtϬ Wtϭ
h
s
E E W'ϰ W' ϯ WϭϮ Wϭϰ sͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s sͺ>s W:ϭϯ W:ϭϮ E
sͺ,sͺ
/Kͺ:d'
s^^ͺ,s
sͺ,sͺ
/Kͺ/
s
t
WZϭϰ WZϭϱ Wϭϱ Wϭϯ W/ϭ W<ϱ sͺ>s s^^ͺ>s E E s^^ͺ>s sͺ>s W:ϭϬ W:ϭϭ W&ϭϬ W&ϵ Wsϲ E
t
z
WZϭϮ WZϭϯ W/Ϭ Wϱ W<ϰ W<ϲ W:ϴ W:ϵ W&ϭϮ W&ϭϭ Wsϭϰ Wsϭϱ
z
Wzϯ WzϮ
sͺ,sͺ
Zͺ
s^^ͺ,sͺ
Zͺ
W<ϳ W<ϴ W<ϵ W'ϭϬ Wϰ Wϭϭ WϬ s^dz W>ϭϬ W>ϭϮ W>ϭϰ W:ϲ s^^ͺ,s W,ϲ W:ϰ W,ϱ WsϭϮ Wsϭϯ
WZϭϭ WZϭϬ W/Ϯ W/ϯ E W'ϳ W<ϭϭ W<ϭϬ Wϭϰ Wϯ Wϭ W>ϵ W>ϭϭ W>ϭϯ W>ϭϱ W:ϳ W:ϱ s^^ͺ,s W&ϴ W:ϯ WsϭϬ Wsϭϭ
Wzϭ WzϬ W/ϰ W/ϱ
sͺ,sͺ/
KͺD/E
W:Ϯ Wsϴ Wsϵ
WZϴ WZϵ W'ϱ W'ϲ W/ϲ W/ϳ W'ϴ W'ϵ W'ϭϭ Wϭϱ WϮ W/ϭϯ W/ϭϭ W&ϭ Wϵ Wϭϭ Wϵ Wϯ W&ϳ Wϭϱ s^^ͺ,s
sͺ,sͺ
/KͺD/E
Wsϳ Wsϱ
Wyϭϱ Wyϭϰ E Wϳ Wϲ
s^^ͺ,sͺ
s ^
sͺ,sͺ
s ^
sͺ,sͺ
Z ^
s^^ͺ,sͺ
Z ^
W'ϭϮ Wϭϯ W/ϭϮ W/ϭϬ W&Ϭ WϭϬ WϭϬ Wϴ Wϴ W&ϲ W:Ϭ W:ϭ s^^ͺ,s Wsϰ Wsϯ
&
WZϲ WZϳ WsϮ Wsϭ
&
'
sͺ,sͺ
Z Ϯ
s^^ͺ,sͺ
Z Ϯ
Wzϰ WsϬ
'
,
E E
sͺ,sͺ
/KͺD/E
sͺ,sͺ
/Kͺ/
,
:
E E E WZϰ WZϮ WyϭϮ WZϭ
s^^ͺ,sͺ
sͺ^
sͺ,sͺ
sͺ^
s^^ͺ,s
sͺ,sͺ
/Kͺ&>y
W^Ϭ W^Ϯ W^ϰ W^ϲ W^ϴ W^ϭϬ W^ϭϮ W^ϭϰ E WdϬ WdϮ Wdϰ Wdϲ Wdϴ WdϭϬ WdϭϮ Wdϭϰ s^^ͺ,s
sͺ,sͺ
/KͺD/E
:
<
E E WZϱ WZϯ Wyϭ ϯ WZϬ
s^^ͺ,sͺ
sͺ
sͺ,sͺ
sͺ
s^^ͺ,s
sͺ,sͺ
/Kͺ&>y
W^ϭ W^ϯ W^ϱ W^ϳ W^ϵ W^ϭϭ W^ϭϯ W^ϭϱ
sͺ,sͺ
/Kͺ&>y
Wdϭ Wdϯ Wdϱ Wdϳ Wdϵ Wdϭ ϭ Wdϭ ϯ Wdϭϱ
sͺ,sͺ
/Kͺ&>y
<
ϭϮϯϰϱϲϳϴϵϭϬϭϭϭϮϭϯϭϰϭϱϭϲϭϳϭϴϭϵϮϬϮϭϮϮϮϯϮϰϮϱϮϲϮϳϮϴϮϵϯϬ
MPC5777M Microcontroller Data Sheet, Rev. 6
Figure 5. 512-ball BGA production device pinout (top view)
Package pinouts and signal descriptions
Page 13
MPC5777M Microcontroller Data Sheet, Rev. 6
ϭϮϯϰϱϲϳϴϵϭϬϭϭϭϮϭϯϭϰϭϱϭϲϭϳϭϴϭϵϮϬϮϭϮϮϮϯϮϰϮϱϮϲϮϳϮϴϮϵϯϬ
sͺ,sͺ
/KͺD/E
E E WyϬ WDϭϱ WEϬ E E E Wyϰ Wyϯ Wyϭ WYϭϯ WYϭϭ WYϵ E WYϳ WYϱ WYϯ E Wyϭϭ Wyϵ Wyϳ E E E E
sͺ,sͺ
/KͺD/E
E s^^ͺ,s
sͺ,sͺ
/KͺD/E
E WDϭϰ WDϭϯ WDϭϮ WDϭϭ E E WyϮ WYϭϱ WYϭϰ WYϭϮ WYϭϬ WYϴ E WYϲ WYϰ E E WyϭϬ Wyϴ Wyϲ Wyϱ E E
sͺ,sͺ
/KͺD/E
s^^ͺ,s s^^ͺ,s
E E E E
E E E E
E E E E
&
WEϮ WEϭ s^^ͺ,s
sͺ,sͺ
/KͺD/E
W,ϭϯ W&Ϯ W&ϱ WDϭϬ W,ϭϱ Wϭϭ Wϭϯ WϭϮ WϬ WϮ W,ϵ W,ϯ Wϭϭ WDϵ WϬ Wϭ
sͺ,sͺ/
KͺD/E
s^^ͺ,s E E
&
'
WEϰ WEϯ Wϭϰ s^^ͺ,s
sͺ,sͺ
/KͺD/E
W,ϭϮ W&ϯ W,ϭϰ W&ϰ WϭϬ WϭϮ Wϭϱ Wϭ Wϯ W,ϰ WϭϬ Wϭϭ WϭϬ Wϭϯ
sͺ,sͺ
/KͺD/E
s^^ͺ,s WϮ E E
'
,
E E Wϵ Wϭϱ WϭϮ Wϵ s^^ͺ,s s^^ͺ,s
,
:
E WEϱ Wϳ Wϴ s^^ͺ,s
sͺ,sͺ
/Kͺ&>y
WDϮ WDϬ W<ϭϰ Wϭϰ WDϲ W,ϳ W,ϴ W,ϭϬ W,ϭ W,Ϭ
sͺ,sͺ
&>
s^^ͺ,s Wϱ W ϴ
sͺ,sͺ
/Kͺ/
sͺ,sͺ
/Kͺ/
:
<
WEϲ WEϳ Wϱ Wϲ W>ϭ s^^ͺ,s WDϯ WDϭ W<ϭϱ WDϰ WDϱ WDϳ WDϴ W,Ϯ W'ϭϱ
sͺ,sͺ
&>
s^^ͺ,s Wϲ Wϳ Wϰ Wtϭϰ Wtϭϱ
<
>
WEϴ WEϵ Wϯ Wϰ W>Ϯ W>Ϭ ^ZϬ W'ϭϯ W'ϭϰ Wϱ WtϭϮ Wtϭϯ
>
D
WEϭϭ WEϭϬ WϮ Wϭ W>ϯ W>ϰ
sͺ>sͺ
s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s sͺ>s Wϰ WKZ^d W,ϭϭ W&ϭϱ WtϭϬ Wtϭϭ
D
E
WEϭϯ WEϭϮ WϬ WϬ W>ϲ W>ϱ
sͺ>sͺ
s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s sͺ>s Wϵ Wϴ d^dDK W&ϭϰ Wtϴ Wtϵ
E
W
WEϭϱ WEϭϰ Wϭ WϮ WϭϮ W>ϳ s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s Wϲ W/ϭϱ Wϳ Wϭϰ Wtϲ Wtϳ
W
Z
E E Wϭϯ Wϰ Wϯ W'Ϭ dyϯW s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s
sͺ,sͺ
/Kͺ
Wϳ W/ϭϰ W&ϭϯ Wϲ Wtϰ Wtϱ
Z
d
W>ϴ WYϭ W/ϴ W/ϵ W<Ϭ W<ϭ dyϯE s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s E W<ϭϯ W<ϭϮ Wϱ
s^^ͺ,sͺ
K^
WtϮ Wtϯ
d
h
WYϮ WY Ϭ W'Ϯ W'ϭ W<Ϯ W<ϯ s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s W:ϭϱ W:ϭϰ yd> yd> WtϬ Wtϭ
h
s
E E W'ϰ W'ϯ WϭϮ Wϭϰ sͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s s^^ͺ>s sͺ>s W:ϭϯ W:ϭϮ E
sͺ,sͺ
/Kͺ:d'
s^^ͺ,s
sͺ,sͺ
/Kͺ/
s
t
WZϭϰ WZϭϱ Wϭϱ Wϭϯ W/ϭ W<ϱ sͺ>s s^^ͺ>s dyϮE dyϮW s^^ͺ>s sͺ>s W:ϭϬ W:ϭϭ W&ϭϬ W&ϵ Wsϲ E
t
z
WZϭϮ WZϭϯ W/Ϭ Wϱ W<ϰ W<ϲ W:ϴ W:ϵ W&ϭϮ W&ϭϭ Wsϭϰ Wsϭϱ
z
Wzϯ WzϮ
sͺ,sͺ
Zͺ
s^^ͺ,sͺ
Zͺ
W<ϳ W<ϴ W<ϵ W'ϭϬ Wϰ Wϭϭ WϬ s^dz W>ϭϬ W>ϭϮ W>ϭϰ W:ϲ s^^ͺ,s W,ϲ W:ϰ W,ϱ WsϭϮ Wsϭϯ
WZϭϭ WZϭϬ W/Ϯ W/ϯ E W'ϳ W<ϭϭ W<ϭϬ Wϭϰ Wϯ Wϭ dyϭE dyϭW dyϬE dyϬW ><E ><W s^^ͺ,s W&ϴ W:ϯ WsϭϬ Wsϭϭ
Wzϭ WzϬ W/ϰ W/ϱ
sͺ,sͺ/
KͺD/E
W:Ϯ Wsϴ Wsϵ
WZϴ WZϵ W'ϱ W'ϲ W/ϲ W/ϳ W'ϴ W'ϵ W'ϭϭ Wϭϱ WϮ W/ϭϯ W/ϭϭ W&ϭ Wϵ Wϭϭ Wϵ Wϯ W&ϳ Wϭϱ s^^ͺ,s
sͺ,sͺ
/KͺD/E
Wsϳ Wsϱ
Wyϭϱ Wyϭϰ E Wϳ Wϲ
s^^ͺ,sͺ
s ^
sͺ,sͺ
s ^
sͺ,sͺ
Z ^
s^^ͺ,sͺ
Z ^
W'ϭϮ Wϭϯ W/ϭϮ W/ϭϬ W&Ϭ WϭϬ WϭϬ Wϴ Wϴ W&ϲ W:Ϭ W:ϭ s^^ͺ,s Wsϰ Wsϯ
&
WZϲ WZϳ WsϮ Wsϭ
&
'
sͺ,sͺ
Z Ϯ
s^^ͺ,sͺ
Z Ϯ
Wzϰ WsϬ
'
,
E E
sͺ,sͺ
/KͺD/E
sͺ,sͺ
/Kͺ/
,
:
E E E WZϰ WZϮ WyϭϮ WZϭ
s^^ͺ,sͺ
sͺ^
sͺ,sͺ
sͺ^
s^^ͺ,s
sͺ,sͺ
/Kͺ&>y
W^Ϭ W^Ϯ W^ϰ W^ϲ W^ϴ W^ϭϬ W^ϭϮ W^ϭϰ E WdϬ WdϮ Wdϰ Wdϲ Wdϴ WdϭϬ WdϭϮ Wdϭϰ s^^ͺ,s
sͺ,sͺ
/KͺD/E
:
<
E E WZϱ WZϯ Wyϭ ϯ WZϬ
s^^ͺ,sͺ
sͺ
sͺ,sͺ
sͺ
s^^ͺ,s
sͺ,sͺ
/Kͺ&>y
W^ϭ W^ϯ W^ϱ W^ϳ W^ϵ W^ϭϭ W^ϭϯ W^ϭϱ
sͺ,sͺ
/Kͺ&>y
Wdϭ Wdϯ Wdϱ Wdϳ Wdϵ Wdϭϭ Wdϭϯ Wdϭϱ
sͺ,sͺ
/Kͺ&>y
<
ϭϮϯϰϱϲϳϴϵϭϬϭϭϭϮϭϯϭϰϭϱϭϲϭϳϭϴϭϵϮϬϮϭϮϮϮϯϮϰϮϱϮϲϮϳϮϴϮϵϯϬ
NXP Semiconductor s13
Figure 6. 512-ball BGA emulation device pinout (top view)
Package pinouts and signal descriptions
Page 14
Package pinouts and signal descriptions
2.2 Pin/ball descriptions
The following sections provide signal descriptions and related information about device functionality and configurat ion.
2.2.1 Power supply and reference voltage pins/balls
Table 2 contains information on power supply and reference pin functions for the devices.
NOTE
All ground supplies must be tied to ground. They can NOT float.
Table 2. Power supply and reference pins
Supply BGA ball
Symbol T ype Description 416PD 416ED 512PD 512ED
V
SS_HV
V
SS_LV
V
DD_LV
V
DD_LV_BD
Ground High voltage ground A26, B25, C24, D23,
D15, D8, J4, L23,
R23, T4, W23, AC23,
AC19
Ground Low voltage ground K10, K11, K12, K13,
K14, K15, K16, K17,
L10, L11, L12, L13,
L14, L15, L16, L17,
M10, M11, M12,
M13, M14, M15,
M16, M17, N10, N11,
N12, N13, N14,
N15,N 16, N17, P11,
P12, P13, P14, P15,
P16, R 11, R12, R13,
R14, R15, R16, T10,
T11, T12, T13, T14,
T15, T16, T17
Power Low voltage power supply for
production device
(PLL is also powered by this pin.)
Power Low voltage power supply for
buddy die
B26, C25, D9, D24,
E23, H4, P23, V23,
AB23, AC20
—R1, R4— M13,
B2, B29, B30, F6,
F25, G7, G24, H29,
H30, J9, J22, K10,
K21,V29, AA21,
AB22, AD24, AE25,
AJ10, AJ29, AK10
M14, M15, M16,
M17, N14, N15,
N16, N17, P12, P13,
P15, P16, P18, P19,
R13, R14, R15,
R16, R17, R18,
T13,T14, T15, T16,
T17, T18, U12, U13,
U 15, U16, U18,
U19, V14, V15 V16,
V17, W14, W17
M18, N19, V12,
V19, W13, W18
N12
V
DD_HV_PMC
V
DD_HV_IO_MAIN
V
DD_HV_IO_BD
V
SS_HV_OSC
V
DD_HV_JTAG
Power High voltage power supply for
internal power management unit
Power High voltage power supply for I/O A25, B24, C23, D22,
Power High voltage power supply for
buddy die I/O
Ground Oscillator ground supply F25 T25
Power JTAG/Oscillator power supply E26 V25
MPC5777M Microcontroller Data Sheet, Rev. 6
D14 —
A2, A29, B3, B28,
K4, AC16, AD16,
AE16, AF16
— P17 — R19
F7, F24, G8, G23,
AC24, AD25, AH29,
AJ30
NXP Semiconductors14
Page 15
Package pinouts and signal descriptions
Table 2. Power supply and reference pins (continued)
Supply BGA ball
Symbol T ype Description 416PD 416ED 512PD 512ED
V
DD_HV_IO_FLEX
V
DD_HV_IO_FLEXE
V
DD_HV_IO_EBI
V
DD_HV_FLA
V
SS_HV_ADV_S
V
DD_HV_ADV_S
V
SS_HV_ADV_D
V
DD_HV_ADV_D
V
SS_HV_ADR_S
V
DD_HV_ADR_S
V
SS_HV_ADR_D
V
DD_HV_ADR_D
V
DDSTBY
Power FlexRay/Ethernet 3.3 V I/O
Power FLexRay/Ethernet/EBI I/O
Power EBI Address/Control I/O Segment
Power Decoupling supply pin for flash A18, B18 J21, K20
Ground Ground supply for ADC SAR AF9 AE9, AJ8
Power Voltage supply for ADC SAR AE9 AE10, AJ9
Ground Ground supply for ADC SD AF5 AK8
Power Voltage supply for ADC SD AE5 AK9
Reference Ground reference for ADC SAR AE8 AE12
Reference Voltage reference for ADC SAR AF8 AE11
Reference Ground reference for ADC SD Y4, AC6 AA7
Reference Voltage reference for ADC SD W4, AD6 AA6
Power Standby RAM supply AD9 AA16
2.2.2 System pins/balls
supply
Segment Voltage Supply
Voltage Supply
D7 J10
AC18, AC22 AJ11, AK11, AK20,
AK29
M23,T23,Y23 J29, J30, V30, AH30
Table 3 contains information on system pin functions for the devices.
Table 3. System pins
Symbol Description Direction
PORST Power on reset with Schmitt trigger
characteristics and noise filter. PORST is
active low
ESR0 External functional reset with Schmitt
trigger characteristics and noise filter.
ESR0 is active low
TESTMODE Pin for testing purpose only. TESTMODE
pull-down is implemented to prevent the
device from entering TESTMODE. It is
recommended to connect the
TESTMODE pin to VSS_HV_IO on the
board. The value of the TESTMODE pin
is latched at the negation of reset and has
no affect afterward.
Note: The device will not exit reset with
the TESTMODE pin asserted
during power-up.
Bidirectional B22 M22
Bidirectional A23 L21
BGA ball
416PD 416ED 512PD 512ED
Input only B23 N24
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 15
Page 16
Package pinouts and signal descriptions
Symbol Description Direction
Table 3. System pins (continued)
BGA ball
416PD 416ED 512PD 512ED
XTAL Analog output of the oscillator amplifier
circuit
needs to be grounded if oscillator is used
in bypass mode.
EXT AL Analog input of the oscillator amplifier
circuit when oscillator is not in bypass
mode
Analog input for the clock generator when
oscillator is in bypass mode
Output G25 U24
Input G26 U25
2.2.3 LVDS pins/balls
The following table contains information on LVDS pin functions for the devices.
Table 4. LVDS pin descriptions
Functional block Port pin Signal Signal description
SIPI / LFAST
1
PA[14] SIPI_TXP Interprocessor Bus LFAST,
LVDS Transmit Positive
Terminal
PD[6] SIPI_TXN Interprocessor Bus LFAST,
LVDS Transmit Negative
Terminal
BGA ball
(416 PD,
416 ED)
Direction
OC26 P25
OD26 R25
BGA ball
(512 PD,
512 ED)
High-Speed
Debug (HSD) /
1,2
LFAST
PD[7] SIPI_RXP Interprocessor Bus LFAST,
LVDS Receive Positive
Terminal
PF[13] SIPI_RXN Interprocessor Bus LFAST,
LVDS Receive Negative
Terminal
PA[7] DEBUG_TXP Debug LFAST, LVDS
Transmit Positive Terminal
PA[8] DEBUG_TXN Debug LFAST, LVDS
Transmit Negative Terminal
PA[9] DEBUG_RXP Debug LFAST , L VDS Receive
Positive Terminal
PA[5] DEBUG_RXN Debug LFAST , L VDS Receive
Negative Terminal
MPC5777M Microcontroller Data Sheet, Rev. 6
IG23 P24
IH23 R24
OF24 R21
OE25 N22
ID25 N21
IF23 T24
NXP Semiconductors16
Page 17
Package pinouts and signal descriptions
Table 4. LVDS pin descriptions (continued)
Functional block Port pin Signal Signal description
DSPI 4
Microsecond Bus
DSPI 5
Microsecond Bus
DSPI 6
Microsecond Bus
PD[2] SCK_P DSPI 4 Microsecond Bus
Serial Clock, LVDS Positive
Terminal
PD[3] SCK_N DSPI 4 Microsecond Bus
Serial Clock, LVDS Negative
Terminal
PD[0] SOUT_P DSPI 4 Microsecond Bus
Serial Data, LVDS Positive
Terminal
PD[1] SOUT_N DSPI 4 Microsecond Bus
Serial Data, LVDS Negative
Terminal
PF[10] SCK_P DSPI 5 Microsecond Bus
Serial Clock, LVDS Positive
Terminal
PF[9] SCK_N DSPI 5 Microsecond Bus
Serial Clock, LVDS Negative
Terminal
PF[12] SOUT_P DSPI 5 Microsecond Bus
Serial Data, LVDS Positive
Terminal
PF[1 1] SOUT_N DSPI 5 Microsecond Bus
Serial Data, LVDS Negative
Terminal
PQ[9] SCK_P DSPI 6Microsecond Bus
Serial Clock, LVDS Positive
Terminal
PQ[8] SCK_N DSPI 6 Microsecond Bus
Serial Clock, LVDS Negative
Terminal
PQ[1 1] SOUT_P DSPI 6 Microsecond Bus
Serial Data, LVDS Positive
Terminal
PQ[10] SOUT_N DSPI 6 Microsecond Bus
Serial Data, LVDS Negative
Terminal
BGA ball
(416 PD,
416 ED)
Direction
OC18 F17
OC17 G17
OC16 F16
OD17 G16
OJ24 W24
OK23 W25
OJ26 Y24
OJ25 Y25
OA17 A16
OB17 B16
OB16 A15
OA16 B15
BGA ball
(512 PD,
512 ED)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 17
Page 18
Package pinouts and signal descriptions
Table 4. LVDS pin descriptions (continued)
Functional block Port pin Signal Signal description
Differential DSPI 2PD[2] SCK_P Differential DSPI 2 Clock,
LVDS Positive Terminal
PD[3] SCK_N Differential DSPI 2 Clock,
LVDS Negative Terminal
PD[0] SOUT_P Differential DSPI 2 Serial
Output, L VDS Positive
Terminal
PD[1] SOUT_N Differential DSPI 2 Serial
Output, L VDS Negative
Terminal
PD[7] SIN_P Differential DSPI 2 Serial
Input, LVDS Positive Terminal
PF[13] SIN_N Differential DSPI 2 Serial
Input, LVDS Negative
Terminal
Differential DSPI 5PF[10] SCK_P Differential DSPI 5 Clock,
LVDS Positive Terminal
PF[9] SCK_N Differential DSPI 5 Clock,
LVDS Negative Terminal
PF[12] SOUT_P Diff erential DSPI 5 Serial
Output, L VDS Positive
Terminal
PF[11] SOUT_N Differential DSPI 5 Serial
Output, L VDS Negative
Terminal
PD[7] SIN_P Differential DSPI 5 Serial
Input, LVDS Positive Terminal
PF[13] SIN_N Differential DSPI 5 Serial
Input, LVDS Negative
Terminal
PI[15] SIN_P Differential DSPI 5 Serial
Input, LVDS Positive Terminal
BGA ball
(416 PD,
Direction
416 ED)
BGA ball
(512 PD,
512 ED)
OC18 F17
OC17 G17
OC16 F16
OD17 G16
IG23 P24
IH23 R24
OJ24 W24
OK23 W25
OJ26 Y24
OJ25 Y25
IG23 P24
IH23 R24
IG24 P22
PI[14] SIN_N Differential DSPI 5 Serial
IJ23 R22
Input, LVDS Negative
Terminal
1
DRCLK and TCK/DRCLK usage for SIPI LFAST and Debug LFAST are described in the MPC5777M
Microcontroller Reference Manual SIPI LFAST and Debug LFAST chapters.
2
Pads use special enable signal form DCI block: DCI driven enable for Debug LFAST pads is transparent to user .
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors18
Page 19
Table 5. Aurora pin descriptions
Package pinouts and signal descriptions
Functional
Block
Nexus Aurora
High Speed
Trace
PAD Signal Signal Description
— TX0P Nexus Aurora High Speed
Trace Lane 0, LVDS Positive
Terminal
— TX0N Nexus Aurora High Speed
Trace Lane 0, LVDS Negative
Terminal
— TX1P Nexus Aurora High Speed
Trace Lane 1, LVDS Positive
Terminal
— TX1N Nexus Aurora High Speed
Trace Lane 1, LVDS Negative
Terminal
— TX2P Nexus Aurora High Speed
Trace Lane 2, LVDS Positive
Terminal
— TX2N Nexus Aurora High Speed
Trace Lane 2, LVDS Negative
Terminal
— TX3P Nexus Aurora High Speed
Trace Lane 3, LVDS Positive
Terminal
— TX3N Nexus Aurora High Speed
Trace Lane 3, LVDS Negative
Terminal
— CLKP
(BD-AGB
TCLKP)
—CLKN
(BD-AGB
TCLKN)
Nexus Aurora High Speed
Trace Clock, LVDS Positive
Terminal
Nexus Aurora High Speed
Trace Clock, LVDS Negative
Terminal
BGA
416PD 416ED 512PD 512ED
Direction
O— U15 —AB19
O— U14 —AB18
O— U13 —AB17
O— U12 —AB16
O— U11 —W16
O— U10 —W15
O— P10 —R12
O— R10 — T12
I—U17—AB21
I—U16—AB20
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 19
Page 20
Electrical characteristics
3 Electrical characteristics
3.1 Introduction
This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications.
In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” (Controller
Characteristics) is included in the “Symbol” column.
In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol
“SR” (System Requirement) is included in the “Symbol” column.
NOTE
Within this document, V
V
DD_HV_IO_JTAG
V
DD_HV_FLA
V
DD_HV_ADV_D
V
DD_HV_ADR_D
V
SS_HV_ADV_D
V
SS_HV_ADR_D
, V
DD_HV_IO_FLEX, VDD_HV_IO_FLEXE
. V
DD_HV_ADV
. V
DD_HV_ADR
. V
SS_HV_ADV
. V
SS_HV_ADR
.
DD_HV_IO
refers to supply pins V
, V
refers to ADC supply pins V
refers to ADC reference pins V
refers to ADC ground pins V
refers to ADC reference pins V
DD_HV_IO_MAIN
DD_HV_IO_EBI
DD_HV_ADV_S
DD_HV_ADR_S
SS_HV_ADV_S
SS_HV_ADR_S
and
,
, and
and
and
and
3.2 Absolute maximum ratings
Table 6 describes the maximum ratings of the device.
Table 6. Absolute maximum ratings
Symbol Parameter Conditions
Cycle SR Lifetime power cycles — — 1000 k —
V
DD_LV
V
DD_LV_BD
V
DD_HV_IO
V
DD_HV_PMC
V
DD_HV_FLA
V
DDSTBY
V
SS_HV_ADV
V
DD_HV_ADV
V
SS_HV_ADR
V
DD_HV_ADR
V
DD_HV_IO_JTAG
SR 1.2 V core supply voltage
SR Emulation module voltage
SR I/O supply voltage
SR Power Management Controller
supply voltage
5
SR Flash core voltage
SR RAM standby supply voltage
8
SR SAR and S/D ADC ground voltage Reference to V
9
SR SAR and S/D ADC supply voltage Reference to corresponding
10
SR SAR and S/D ADC low reference Reference to V
11
SR SAR and S/D ADC high reference Reference to corresponding
SR Crystal oscillator , FEC MDIO/MDC,
LFAST, JTAG
5
2,3,4
2,3,4
5,6
7
1
Value
Unit
Min Max
—–0.31.5V
—–0.31.5V
—–0.36.0V
—–0.36.0V
—–0.34.5V
5
—–0.36.0V
SS_HV
–0.3 0.3 V
–0.3 6.0 V
V
SS_HV_ADV
SS_HV
–0.3 0.3 V
–0.3 6.0 V
V
SS_HV_ADR
Reference to V
SS_HV
–0.3 6.0 V
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors20
Page 21
Table 6. Absolute maximum ratings1 (continued)
Symbol Parameter Conditions
Electrical characteristics
Value
Unit
Min Max
V
DD_HV_IO_EBI
V
DD_LV_BD–VDD_LV
SR External Bus Interface supply
voltage
SR Emulation module supply
—–0.36.0V
—–0.31.5V
differential to 1.2 V core supply
V
I
INJD
I
INJA
I
MAXD
IN
SR I/O input voltage range
SR Maximum DC injection current for
digital pad
SR Maximum DC injection current for
analog pad
SR Maximum output DC current when
driven
12
Relative to V
Relative to V
Per pin, applies to all digital
—–0.36.0V
SS_HV_IO
DD_HV_IO
13,14
13,14
–0.3 —
—0.3
–5 5 mA
pins
Per pin, applies to all analog
–5 5 mA
pins
Medium 78mA
Strong –10 10
Very strong –11 11
I
MAXSEG
T
STG
SR Maximum current per power
segment
15
SR Storage temperature range and
— –90 90 mA
— –55 175 °C
non-operating times
STORAGE SR Maximum storage time, assembled
part programmed in ECU
No supply; storage
temperature in range –40 °C
— 20 years
to 60 °C
T
SDR
SR Maximum solder temperature
16
——260°C
Pb-free package
18
17
——3—
At 160 KeV at max 5 mm — 3 min
MSL SR Moisture sensitivity level
t
XRAY
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
SR X-ray screen time
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2
Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ= 150 °C, remaining time as defined in note 3
and note 4
3
Allowed 1.38– 1.45 V– for 10 hours cumulative time at maximum TJ= 150 °C, remaining time as defined in note 4
4
1.32 – 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at
maximum T
5
Allowed 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset,
T
= 150 °C, remaining time at or below 5.5 V.
J
6
V
DD_HV_IO
=150°C.
J
applies to V
DD_HV_IO_MAIN
, V
DD_HV_IO_FLEX
, V
DD_HV_IO_FLEXE
, V
DD_HV_IO_JTAG
, and V
DD_HV_IO_EBI
power supplies.
7
Allowed 3.6–4.5 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset,
= 150 °C, remaining time at or below 3.6 V.
T
J
8
Includes ADC grounds V
SS_HV_ADV_S and VSS_HV_ADV_D
.
I/O
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 21
Page 22
Electrical characteristics
9
Includes ADC supplies V
DD_HV_ADV_S and VDD_HV_ADV_D
. V
DD_HV_ADV_S
is also the supply for the device
temperature sensor, RCOSC, and bandgap reference.
10
Includes ADC low references V
11
Includes ADC high references V
12
The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
SS_HV_ADR_S
DD_HV_ADR_S
and V
and V
SS_HV_ADR_D
DD_HV_ADR_D
.
.
condition on a pin, the voltage equals the supply plus the voltage drop across the internal ESD diode from I/O pin to
supply. The diode voltage varies significantly across process and temperature, but a value of 0.3V can be used for
nominal calculations.
13
V
DD_HV_IO/VSS_HV_IO
V
DD_HV_IO_JTAG
14
Relative value can be exceeded if design measures are taken to ensure injection current limitation (parameters I
and I
15
Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V
INJA
).
is defined as one or more GPIO pins located between two V
16
Solder profile per IPC/JEDEC J-STD-020D
17
Moisture sensitivity per JEDEC test method A112
18
Three Screen done, 1 minute each. No change in device parameters during characterization of at least 10 devices at
refers to supply pins and corresponding grounds: V
, V
DD_HV_OSC
, V
DD_HV_FLA.
DD_HV_IO
DD_HV_IO_MAIN
supply pins.
, V
DD_HV_IO_FLEX
DD_HV_IO
power segment
30 minutes exposure of 150 KeV at maximum 5 mm.
3.3 Electrostatic discharge (ESD)
The following table describes the ESD ratings of the device.
Table 7. ESD ratings
1,2
,
INJD
Parameter Conditions Value Unit
ESD for Human Body Model (HBM)
ESD for field induced Charged Device Model (CDM)
1
All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated
3
4
All pins 2000 V
All pins 500 V
Circuits.
2
Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot
temperature. Maximum DC parametrics variation within 10% of maximum specification”
3
This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing
4
This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level
3.4 Operating conditions
The following table describes the operating conditions for the device for which all specifications in the data sheet are valid,
except where explicitly noted.
The device operating conditions must not be exceeded or the functionality of the device is not guaranteed.
Table 8. Device operating conditions
Symbol Parameter Conditions
Frequency
f
SYS
SR Device operating
frequency
2
TJ40 °C to 150 °C — — 300 MHz
1
Value
Unit
Min Typ Max
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors22
Page 23
Table 8. Device operating conditions1 (continued)
Symbol Parameter Conditions
Temperature
Electrical characteristics
Value
Unit
Min Typ Max
T
J
SR Operating temperature
range - junction
(TL to TH) SR Ambient operating
T
A
temperature range
V
DD_LV
SR External core supply
voltage
V
DD_HV_IO_MAIN
V
DD_HV_IO_JTAG
10,11
SR I/O supply voltage LVD400/HVD600
SR JTAG I/O supply
voltage
V
DD_HV_IO_FLEX
SR FlexRay I/O supply
voltage
V
DD_HV_IO_FLEXE
SR FlexRay/EBI I/O supply
voltage
V
DD_HV_IO_EBI
SR External Bus Interface
supply voltage
V
DD_HV_OSC
SR Oscillator supply
voltage
21
V
DD_HV_PMC
SR Power Management
Controller (PMC)
supply voltage
3,4
6,19
6,20
— –40.0 — 150.0 °C
— –40.0 — 125.0 °C
Voltage
LVD/HVD enabled 1.24 — 1.38
LVD/HVD
disabled
enabled
LVD400/HVD600
disabled
LVD360/HVD600
disabled
6,7,8,9
18
6,13,14,15,18
6,13,14,16,17,18
1.19 — 1.38
4.5 — 5.5
4.2 — 5.5
3.0 — 5.5
5
5
12
5 V range 4.5 — 5.5 V
3.3 V range 3.0 — 3.6
5 V range 4.5 — 5.5 V
3.3 V range 3.0 — 3.6
5 V range 4.5 — 5.5 V
3.3 V range 3.0 — 3.6
5 V range 4.5 — 5.5 V
3.3 V range 3.0 — 3.6
5 V range 4.5 — 5.5 V
3.3 V range 3.0 — 3.6
Full functionality
22,23
Reduced internal
regulator output
capability
26
Supply monitoring
24,25
3.5
—5.5V
3.15 — 3.5
3.0 — 3.15
activity only (LVD/HVD)
V
V
V
DDSTBY
V
DD_HV_ADV
SR RAM standby supply
voltage
27,28,29
SR SARADC, SDADC,
Temperature Sensor,
and Bandgap
Reference supply
voltage
— 1.1 — 5.5 V
LVD400 enabled 4.5 — 5.5 V
LVD400
disabled
LVD300
disabled
30,31,34
6,30,31,33,34
4.0 — 5.5
3.7 — 5.5
32
32
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 23
Page 24
Electrical characteristics
Symbol Parameter Conditions
Table 8. Device operating conditions1 (continued)
Value
Unit
Min Typ Max
V
DD_HV_ADR_D
V
DD_HV_ADR_D
V
DD_HV_ADV_D
V
SS_HV_ADR_D
V
SS_HV_ADR_D
V
SS_HV_ADV_D
V
DD_HV_ADR_S
V
SS_HV_ADR_S
V
DD_HV_ADR_S
V
DD_HV_ADV_S
V
SS_HV_ADR_S
V
SS_HV_ADV_S
V
SS_HV_ADV
V
RAMP_LV
V
RAMP_HV
– V
SR SD ADC supply
reference voltage
–
SR SD ADC reference
Reduced SNR 3.0 V
Full SNR 4.5 5.5
———25mV
differential voltage
SR SD ADC ground
—V
reference voltage
–
SR V
SS_HV_ADR_D
— –25 — 25 mV
differential voltage
35
SR SARADC reference — 2.0 V
SR SAR ADC ground
—V
reference voltage
–
SR SARADC reference
———25mV
differential voltage
–
SR V
SS_HV_ADR_S
— –25 — 25 mV
differential voltage
SS
SR V
SS_HV_ADV
differential
— –25 — 25 mV
voltage
SR Slew rate on core
———100V/ms
power supply pins
SR Slew rate on HV power
———100V/ms
supply pins
DD_HV_ADV_D
SS_HV_ADV_D
DD_HV_ADV_S
4.5 V
4.0 V
4.0 5.5
SS_HV_ADV_S
32
V
32
V
V
por_rel
V
por_hys
V
IN
CC POR release trip point -40 °C < Tj < 150 °C 3.10 — 4.26 V
CC POR hysteresis -40 °C < Tj < 150 °C 150 — 300 mV
SR I/O input voltage range — 0 — 5.5 V
Injection current
I
IC
I
MAXSEG
1
The ranges in this table are design targets and actual data may vary in the given range.
2
Maximum operating frequency is applicable to the computational cores and platform for the device. See the Clocking chapter
SR DC injection current
(per pin)
SR Maximum current per
power segment
36,37,38
39
Digital pins and analog
pins
— –80 — 80 mA
–3.0 — 3.0 mA
in the MPC5777M Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks
on the device.
3
Core voltage as measured on device pin to guarantee published silicon performance.
4
During power ramp, voltage measured on silicon might be lower. maximum performance is not guaranteed, but correct
silicon operation is guaranteed. Refer to the Power Management and Reset Generation Module chapters in the MPC5777M
Microcontroller Reference Manual for further information.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors24
Page 25
Electrical characteristics
5
Although the maximum V
operating voltage is 1.38 V, reset is not entered at that voltage. An external voltage monitor
DD_LV
is needed or the HVD140_C can be monitored (via an interrupt or by polling the HVD140_C flag bit). Performance above
1.38 V is not guaranteed, and allowed operation above 1.38 V is defined in Absolute maximum ratings.
6
In the LVD/HVD disabled case, it is necessary for the system to be within a higher voltage range during destructive reset
events.
7
Maximum core voltage is not permitted for entire product life. See Absolute maximum rating.
8
When internal LVD/HVDs are disabled, external monitoring is required to guarantee correct devi c e operation.
9
Vdd_lv should be above 1.24 V during destructive resets or POR events.
10
VDD_HV_IO_MAIN range limited to 4.75–5.25 V when FERS = 1 to enable the fast erase time of the flash memory.
11
During power up operation, the minimum required voltage to come out of reset state is determined by the V
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V
to the V
12
When the LVD/HVDs are enabled, the V
13
Maximum voltage is not permitted for entire product life. See Absolute maximum rating.
14
When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor
DD_HV_IO_MAIN0
physical I/O segment.
DD_HV_IO_MAIN
must be less than 5.412 V to exit from a destructive reset.
PORUP_HV
PORUP_HV
monitor is connected
externally supply voltage may result in erroneous operation of the device.
15
When these LVD/HVDs are disabled, the V
16
Reduced output capabilities below 4.2 V. See performance derating values in I/O pad electrical characteristics.
17
When the LVD/HVDs are disabled, the VDD_HV_IO_MAIN must be between 3.024 V and 5.412 V.
18
The PMC supply voltage (V
19
When the LVD/HVDs are disabled, the HV I/O JTAG supply (V
20
When the LVD/HVDs are disabled, the HV OSC supply (V
21
Flash read operation is supported for a minimum V
are supported for a minimum V
22
When the LVD/HVDs are disabled, the V
23
A minimum of 4.5 V is required to guarantee correct user logic BIST operation.
24
During power up operation, the minimum required voltage to come out of reset state is determined by the V
DD_HV_PMC
DD_HV_PMC
DD_HV_IO_MAIN
) must be within the correct range (see the V
value of 3.5 V.
DD_HV_PMC
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V
to the V
25
Above Ta = 25°C, the minimum V
26
With the reduced internal regulator output capability, erases and writes to the device flash cannot be guaranteed for a single
DD_HV_IO_MAIN0
physical I/O segment.
DD_HV_PMC
voltage is 3.6 V.
supply must be between 3.182 V and 5.412 V.
specification).
DD_HV_OSC
DD_HV_PMC
DD_HV_PMC
DD_HV_IO_JTAG
) must be above 3.024 V.
) must be above 3.024 V.
value of 3.15 V. Flash read, program, and erase operations
must be below 5.412 V during destructive reset events.
PORUP_HV
monitor is connected
PORUP_HV
event and multiple erases and writes may be necessary. User logic BIST is not supported with reduced capability.
27
RAM data retention is guaranteed at a voltage that is always below the maximum brownout flag trip point voltage (see the
DC Electrical Specification table). The minimum V
and noise. There is no effect on RAM operation when V
voltage at the pin is larger in order to account for on-chip IR drop
DDSTBY
is below 1.1 V, and V
DDSTBY
is above the minimum operating
DD_LV
value.
28
Non-regulated supplies can be used on the VDDSTBY pin if the absolute maximum an d operating condition voltage limits
are met. There is no static clamp to a supply rail for the VDDSTBY pin, only dynamic protection for ESD events.
29
The VDDSTBY pin should be connected to ground in the application when the standby RAM feature is not used.
30
V
DD_HV_ADV_S
31
SAR ADC only. SDADC minimum is 4.5 V.
32
The ADC is functional up to 5.9V with no reliability issues, but performance is not guaranteed.
33
When the LVD/HVDs are disabled, the HV ADC supply (V
34
For supply voltages between 3.0 V and 4.0 V there is no guaranteed precision of ADC (accuracy/linearity). ADCs recover to
is required to be between 4.5 V and 5.5 V to read the internal Temperature Sensor and Bandgap Reference.
DD_HV_ADV
) must be above 3.182 V.
a fully functional state when the voltage rises above 4.0 V.
35
V
DD_HV_ADR_S
36
Full device lifetime without performance degradation
37
I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the
must be between 4.5 V and 5.5 V for accurate reading of the device Temperature Sensor.
Absolute maximum ratings table for maximum input current for reliability requirements.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 25
Page 26
Electrical characteristics
38
The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is above
the supply rail, current is injected through the clamp diode to the supply rail. For external RC network calculation, assume
typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
39
Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V
as one or more GPIO pins located between two V
DD_HV_IO
supply pins.
DD_HV_IO
power segment is defined
Table 9. Emulation (buddy) device operating conditions
1
Value
Symbol Parameter Conditions
Min Typ Max
Frequency
— SR Standard JTAG 1149.1/1149.7 frequency — — — 50 MHz
— SR High-speed debug frequency — — — 320 MHz
— SR Data trace frequency — — — 1250 MHz
Temperature
T
J_BD
SR Device junction operating temperature
— –40.0 — 150.0 °C
range
T
A _BD
SR Ambient operating temperature range — –40.0 — 125.0 °C
Voltage
V
DD_LV_BD
V
DD_HV_IO_BD
V
RAMP_LV_BD
V
RAMP_HV_BD
1
The ranges in this table are design targets and actual data may vary in the given range.
SR Buddy core supply voltage — 1.2 — 1.365 V
SR Buddy I/O supply voltage — 3.0 — 5.5 V
SR Buddy slew rate on core power supply pins — — — 100 V/ms
SR Buddy slew rate on HV power supply pins — — — 100 V/ms
Unit
3.5 DC electrical specifications
The following table describes the DC electrical specifications.
Table 10. DC electrical specifications
Symbol Parameter Conditions
I
DD_LV
I
DDAPP_LV
I
DD_LV_PE
CC Maximum operating
current on the V
2
supply
CC Application use case
operating current on the
supply
V
DD_LV
CC Operating current on
the V
DD_LV
supply for
flash program/erase
MPC5777M Microcontroller Data Sheet, Rev. 6
DD_LV
3
1
Value
Unit
Min Typ Max
TJ = 150oC
V
= 1.325 V
DD_LV
f
MAX
TJ = 150 °C
V
= 1.325 V
DD_LV
f
MAX
= 150oC——40mA
T
J
——1140mA
——950mA
NXP Semiconductors26
Page 27
Table 10. DC electrical specifications1 (continued)
Symbol Parameter Conditions
Electrical characteristics
Value
Unit
Min Typ Max
I
DD_HV_PMC
I
DD_MAIN_CORE_AC
I
DD_CHKR_CORE_AC
I
DD_HSM_AC
I
DDSTBY_RAM
I
DDSTBY_REG
CC Operating current on
the V
DD_HV_PMC
4,5
supply
7
CC Main Core 0/1 dynamic
Flash read — — 10 mA
Flash P/E — — 40
PMC only — — 25
6
300 MHz — — 115 mA
operating current
CC Checker Core 0
300 MHz — — 80 mA
dynamic operating
current
CC HSM platform dynamic
100 MHz — — 20 mA
operating current
CC 64 KB RAM Standby
Leakage Current
(RAM not
CC V
operational)
8,9,10,11
V
DDSTBY @
1.1 V
to 5.5 V, TJ =
150 °C
DDSTBY @
1.1 V
——350µA
——60
to 5.5 V, TA =
40 °C
CC V
DDSTBY @
1.1 V
——100
to 5.5 V, TA =
85 °C
CC 64 KB RAM Standby
Leakage Current
12
V
DDSTBY @
1.3 V
to 5.5 V, TA =
— — 50 µA
125 °C
I
DD_LV_BD
CC BD Debug/Emulation
low voltage supply
operating current
I
DD_HV_IO_BD
CC Debug/Emulation high
voltage supply
operating current
(Aurora +
JTAGM/LFAST)
I
DD_BD_STBY
CC BD Debug/Emulation
low voltage supply
standby current
CC V
I
SPIKE
CC Maximum short term
current spike
dI CC Current difference ratio
to average current
(dI/avg(I))
17
MPC5777M Microcontroller Data Sheet, Rev. 6
16
13
14,15
TJ = 150 °C
V
DD_LV_BD
=
——290mA
1.32 V
TJ = 150 °C — — 130 mA
V
DD_LV_BD
=
——230mA
1.32 V,
= 150 °C
T
J
DD_LV_BD
=
—— 5
1.32 V,
= 55 °C
T
J
< 20 µ s
——90mA
observation
window
20 µs
——20%
observation
window
NXP Semiconductors 27
Page 28
Electrical characteristics
Symbol Parameter Conditions
18
I
SR
Table 10. DC electrical specifications1 (continued)
CC Current variation during
power up/down
See footnote
19
Value
Unit
Min Typ Max
——90mA
I
BG
CC Bandgap reference
——600µA
current consumption
I
DDOFF
V
STBY_BO
CC Power-off current on
high voltage supply
20
rails
CC Standby RAM brownout
V
DD_HV
= 2.5 V 100 — — µA
———0.921V
flag trip point voltage
V
DD_LV_STBY_SW
CC Standby RAM switch
—0.93——V
VDD_LV voltage
threshold
V
REF_BG_T
CC Bandgap trimmed
reference voltage
TJ = 40 °C to
150 °C
V
DD_HV_ADV
1.200 — 1.237 V
=
5V ± 10%
V
REF_BG_TC
CC Bandgap temperature
coefficient
22
TJ = 40 °C to
150 °C
V
DD_HV_ADV
=
— — 50 ppm/°
5V
V
REF_BG_LR
CC Bandgap line
regulation
22
TJ = 40 °C
V
DD_HV_ADV
— — 8000 ppm/V
=
5V ± 10%
T
= 150 °C
J
V
DD_HV_ADV
=
— — 4000
5V ± 10%
1
All parameters in this data sheet are valid for operation within an operating range of -40° C TJ 150 °C except where
otherwise noted
2
f
as specified per IP. Excludes flash P/E and HSM dynamic current. Measured on an application specific pattern.
MAX
Calculation of total current for the device, all rails, is done by adding the applicable dynamic currents to the I
DD_LV
for the core supply, and summing the current s based on use case for the 5 V blocks, for which current consumption values
are defined in later sections of the DC electrical specification.
3
f
as specified per IP. Excludes flash P/E and HSM dynamic current. Measured on an application specific pattern.
MAX
4
V
DD_HV_PMC
external bypass capacitor connected to the V
to V
DD_HV_IO_MAIN
5
The flash read and flash P/E currents are mutually exclusive, and are not cumulative.
6
This includes PMC consumption, LFAST PLL regulator current, and Nwell bias regulator current. If the V
only available in the 416 BGA package. PMC supply is shorted to V
DD_HV_PMC_BYP
ball. The flash read and P/E current, and PMC current apply
for the 512 BGA.
DD_HV_IO_MAIN
in the 512 BGA, with an
auxiliary
DD_LV
regulator is enabled, the PMC supply may see short term (10 µs) spikes of up to 150 mA depending on transient current
conditions from use case of the device. The auxiliary regulator can be disabled at power-up in the user DCF clients in the
flash memory.
7
There is an additional 25 mA when FERS = 1 to enable the fast erase time of the flash memory.
8
Data is retained for full TJ range of -40 °C to 150 °C. RAM supply switch to the standby regulator occurs when the V
supply falls below 0.95V.
C
value
DD_LV
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors28
Page 29
Electrical characteristics
9
V
may be supplied with a non-regulated power supply, but the absolute maximum voltage on VDDSTBY given in
DDSTBY
the absolute maximum ratings table must be observed.
10
Standby current is reduced by a factor of two from TJ=150 °C, for approximately every ~20 °C drop in operating
temperature.
11
The maximum value for I
DDSTBY_ON
powering up the device and switching the RAM supply back to V
12
The standby RAM regulator current is present on the VDDSTBY pin whenever a voltage is applied to the pin. This also
is also valid when switching from the core supply to the standby supply, and when
.
DD_LV
applies to normal operation where the RAM is powered by the VDD_LV supply . Connecting the VDDSTBY pin to ground
when not using the standby RAM feature will remove the leakage current on the VDDSTBY pin.
13
If Aurora and JTAGM/LFAST not used, V
14
Applies to 2MB calibration RAM in the BD.
15
Buddy device leakage dependency on temperature can be estimated by dividing the 150 °C leakage by two for each
DD_LV_BD
current is reduced by ~20mA.
temperature drop of ~20 °C.
16
Current spike may occur during normal operation that are above average current, valid for I
and its conditions given
DDAPP
in Table 10 (DC electrical specificati ons). Internal schemes must be used (eg frequency ramping, feature enable) to
ensure that incremental demands are made on the external power supply. An internal fast regulator providing ~40mA peak
current within 1us to filter any core power supply droops is available on the device. Assumption is minimum 13.3 µF (20 µF
typical) capacitance on the core supply.]
17
Moving window, valid for I
and its conditions given in Table 10 (DC electrical specifications), with a maximum of
DDAPP
90 mA for the worst case applica tio n
18
This specification is the maximum value and is a boundary for the dl specification.
19
Condition1: For power on period from 0 V up to normal operation with reset asserted. Condition 2: From reset asserted
until PLL running free. Condition 3: Increasing PLL from free frequency to full frequency. Condition 4: reverse order for
power down to 0 V.
20
I
is the minimum guaranteed consumption of the device during power-up. It can be used to correctly size power-off
DDOFF
ballast in case of current injection during power-off state.Power up/down current transients can be limited by controlling
the clock ramp rates with the Progressive Clock Frequency Switching block on the device.
21
V
STBY_BO
RAM data retention is guaranteed to always be less than the V
22
The temperature coefficient and line regulation specifications are used to calculate the reference voltage drift at an
is the maximum voltage that sets the standby RAM brown-out flag in the device logic. The minimum voltage for
STBY_BO
maximum value.
operating point within the specified voltage and temperature operating conditions.
3.6 I/O pad specification
The following table describes the different pad type configurations.
Table 11. I/O pad specification descriptions
Pad type Description
Weak configuration Provides a good compromise between transition time and low electromagnetic emission.
Pad impedance is centered around 800
Medium configuration Provides transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Pad impedance is centered around 200
Strong configuration Provides fast transition speed; used for fast interface.
Pad impedance is centered around 50
Very strong configuration Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Used for fast interface including Ethernet, FlexRay, and the EBI data bus interfaces
requiring fine control of rising/falling edge jitter.
Pad impedance is centered around 40
EBI configuration Provides necessary speed for fast external memory interfaces on the EBI address and
control signals. Drive strength is matched to four selectable loads.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 29
Page 30
Electrical characteristics
V
IL
V
IN
V
IH
V
INTERNAL
V
DD
V
HYS
(SIUL register)
Table 11. I/O pad specification descriptions (continued)
Pad type Description
Differential configuration A few pads provide differential capability providing very fast interface together with good
EMC performances.
Input only pads These low input leakage pads are associated with the ADC channels.
NOTE
Each I/O pin on the device supports specific drive configurations. See the signal description
table in the device reference manual for the available drive configurations for each I/O pin.
The device supports both 3.3 V and 5 V nominal I/O voltages. In order to use 3.3 V on the
V
DD_HV_IO_MAIN0
physical I/O segment, the HV supply low voltage monitor (V
LVD400
)
must be disabled by DCF client. All other physical I/O segments are unaffected by the
LVD400.
3.6.1 I/O input DC characteristics
Table 12 provides input DC electrical characteristics as described in Figure 7.
TTL
Figure 7. I/O input DC electrical characteristics definition
Table 12. I/O input DC electrical characteristics
Symbol Parameter Conditions
V
IHTTL
V
ILTTL
V
HYSTTL
SR Input high level TTL 4.5 V < V
SR Input low level TTL 4.5 V < V
— Input hysteresis TTL 4.5 V < V
MPC5777M Microcontroller Data Sheet, Rev. 6
DD_HV_IO
DD_HV_IO
DD_HV_IO
1
<5.5V
<5.5V
<5.5V
Value
Unit
Min Typ Max
6
6
6
2—V
DD_HV_IO
+0.3
–0.3 — 0.8
0.275 — —
V
NXP Semiconductors30
Page 31
Table 12. I/O input DC electrical characteristics (continued)
Electrical characteristics
Symbol Parameter Conditions
V
DRFTTTL
— Input VIL/VIH temperature
drift TTL
AUTOMOTIVE
2
V
IHAUT
SR Input high level
4.5 V < V
AUTOMOTIVE
3
V
ILAUT
SR Input low level
4.5 V < V
AUTOMOTIVE
V
HYSAUT
— Input hysteresis
4.5 V < V
4
AUTOMOTIVE
V
DRFTAUT
— Input VIL/VIH temperature
4.5 V < V
drift
CMOS/EBI
V
IHCMOS_H
6
V
IHCMOS
V
ILCMOS_H
V
ILCMOS
V
HYSCMOS
SR Input high level CMOS
(with hysteresis)
6
SR Input high level CMOS
(without hysteresis)
6
SR Input low level CMOS
(with hysteresis)
6
SR Input low level CMOS
(without hysteresis)
— Input hysteresis CMOS 3.0 V < V
3.0 V < V
4.5 V < V
3.0 V < V
4.5 V < V
3.0 V < V
4.5 V < V
3.0 V < V
4.5 V < V
4.5 V < V
V
DRFTCMOS
INPUT CHARACTERISTICS
— Input VIL/VIH temperature
drift CMOS
8
3.0 V < VDD_HV_IO < 3.6 V — — 100
4.5 V < V
1
Value
Unit
Min Typ Max
———100mV
DD_HV_IO
< 5.5 V 3.8 — V
DD_HV_IO
V
+0.3
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO < 5.5 V
< 5.5 V –0.3 — 2.2 V
< 5.5 V 0.4 — — V
< 5.5 V — — 100
<3.6V 0.70*
V
<5.5V
DD_HV_IO
< 3.6 V 0.6 *
V
<5.5V
DD_HV_IO
—V
—V
5
DD_HV_IO
+0.3
DD_HV_IO
+0.3
< 3.6 V –0.3 — 0.35 *
V
<5.5V
DD_HV_IO
< 3.6 V –0.3 — 0.4 *
V
<5.5V
< 3.6 V 0.1 *
V
DD_HV_IO
7
<5.5V
——V
DD_HV_IO
5
mV
V
V
V
V
mV
I
LKG
CC Digital input leakage 4.5 V < V
V
SS_HV
DD_HV
< VIN < V
<5.5V
DD_HV
——750nA
TJ = 150 °C
I
LKG_EBI
CC Digital input leakage for
EBI pad
4.5 V < V
V
SS_HV
DD_HV
< VIN < V
<5.5V
DD_HV
——750nA
TJ = 150 °
C
CC Digital input capacitance GPIO input pins — — 7 pF
IN
EBI input pins — — 7
1
During power up operation, the minimum required voltage to come out of reset state is determined by the V
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V
connected to the V
DD_HV_IO_MAIN0
physical I/O segment.
PORUP_HV
monitor is
PORUP_HV
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 31
Page 32
Electrical characteristics
2
A good approximation for the variation of the minimum value with supply is given by formula
V
3
A good approximation for the variation of the maximum value with supply is given by formula
V
4
A good approximation of the variation of the minimum value with supply is given by formula
V
5
In a 1 ms period, assuming stable voltage and a temperature variation of ±30 °C, VIL/VIH shift is within ±50 mV. For
IHAUT
ILAUT
HYSAUT
=0.69×V
=0.49×V
=0.11×V
DD_HV_IO.
DD_HV_IO.
DD_HV_IO.
SENT requirement refer to NOTE on page 41.
6
Only for V
DD_HV_IO_JTAG
VSIO[VSIO_xx] = 0 in the range 3.0 V < V
4.5 V < V
7
Only for V
8
For LFAST, microsecond bus and LVDS input characteristics, refer to dedicated communication module chapters.
DD_HV_IO
DD_HV_IO_JTAG
and V
<5.5V.
and V
DD_HV_IO_FLEX
DD_HV_IO
DD_HV_IO_FLEX
power segment. The TTL threshold are controlled by the VSIO bit.
< 4.0 V, VSIO[VSIO_xx] = 1 in the range
power segment.
Table 13 provides weak pull figures. Both pull-up and pull-down current specifications are provided.
Table 13. I/O pull-up/pull-down DC electrical characteristics
Symbol Parameter Conditions
CC Weak pull-up current
I
WPU
absolute value
2
VIN = 0 V
V
DD_POR
V
IN>VIL
3
< V
DD_HV_IO
=1.1V(TTL)
4.5 V < VDD<5.5V
V
= 0.75*V
R
CC Weak pull-up
WPU
IN
3.0 V < V
= 0.35* V
V
IN
3.0 V < V
V
= 0.35* V
IN
3.0 V < V
V
= 0.69* V
IN
4.5 V < V
= 0.49* V
V
IN
4.5 V < V
V
= 0.35* V
IN
4.5 V < V
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
< 3.6 V
DD_HV_IO
< 3.6 V
DD_HV_IO
< 3.6 V
DD_HV_IO
< 5.5 V
DD_HV_IO
< 5.5 V
DD_HV_IO
< 5.5 V
—34—62k
resistance
1
< 3.0 V
(AUTO)
(AUTO)
(CMOS)
(AUTO)
(AUTO)
(CMOS)
4,5
10.6 * V
Value
Unit
Min Typ Max
– 10.6 — — µA
DD_HV
——130
10 — —
——70
25 — 80
23 — —
——82
40 — 120
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors32
Page 33
Electrical characteristics
Table 13. I/O pull-up/pull-down DC electrical characteristics (continued)
Value
Symbol Parameter Conditions
1
Min Typ Max
I
CC Weak pull-down
WPD
current absolute value
R
CC Weak pull-down
WPD
VIN<VIL=0.9V (TTL)
4.5 V < V
V
= 0.75* V
IN
3.0 V < V
V
= 0.35* V
IN
3.0 V < V
= 0.65* V
V
IN
3.0 V < V
V
= 0.69* V
IN
4.5 V < V
V
= 0.49* V
IN
4.5 V < V
= 0.65* V
V
IN
4.5 V < V
<5.5V
DD
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
< 3.6 V
< 3.6 V
< 3.6 V
< 5.5 V
< 5.5 V
< 5.5 V
—30—55k
(AUTO)
(AUTO)
(CMOS)
(AUTO)
(AUTO)
(CMOS)
16 — — µA
——92
19 — —
25 — 80
——130
40 — —
40 — 120
resistance
1
During power up operation, the minimum required voltage to come out of reset state is determined by the
V
PORUP_HV
monitor is connected to the V
2
Weak pull-up/down is enabled within t
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the V
DD_HV_IO_MAIN0
physical I/O segment.
= 1 µs after internal/external reset has been asserted. Output voltage
WK_PU
PORUP_HV
will depend on the amount of capacitance connected to the pin.
3
V
is the minimum V
DD_POR
DD_HV_IO
supply voltage for the activation of the device pull-up/down, and is given in the
Reset electrical characteristics table of Section Reset pad (PORST, ESR0) electrical characteristics in this Data
Sheet.
4
V
is defined in the Reset electrical characteristics table of Section Reset pad (PORST, ESR0) electrical
DD_POR
characteristics in this Data Sheet.
5
Weak pull-up behavior during power-up. Operational with V
DD_HV_IO>VDD_POR
.
Unit
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 33
Page 34
Electrical characteristics
V
DD_HV_IO
V
DD_POR
RESET
(INTERNAL)
pull-up
RESET
PAD
POWER-UP Application defined Application defined
POWER-DOWN
enabled
YES
NO
t
WK_PU
t
WK_PU
(1)
(1)
(1)
1. Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply.
Figure 8. Weak pull-up electrical characteristics definition
3.6.2 I/O output DC characteristics
The figure below provides description of output DC electrical characteristics.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors34
Page 35
Electrical characteristics
10%
V
out
V
INTERNAL
V
HYS
(SIUL register)
20%
80%
90%
t
R10-90
t
R20-80
t
F10-90
t
F20-80
tTR(max) = MAX(t
R10-90;tF10-90
)
t
TR
(min) = MIN(t
R10-90;tF10-90
)
t
TR20-80
(max) = MAX(t
R20-80;tF20-80
)
t
TR20-80
(min) = MIN(t
R20-80;tF20-80
)
t
SKEW20-80
=t
R20-80-tF20-80
t
SKEW20-80
50%
t
PD50-50 t
PD50-50
Figure 9. I/O output DC electrical characteristics definition
The following tables provide DC characteristics for bidirectional pads:
• Table 14 provides output driver characteristics for I/O pads when in WEAK configuration.
• Table 15 provides output driver characteristics for I/O pads when in MEDIUM configuration.
• Table 16 provides output driver characteristics for I/O pads when in STRONG configuration.
• Table 17 provides output driver characteristics for I/O pads when in VERY STRONG configuration.
• Table 18 provides output driver characteristics for the EBI pads.
NOTE
Driver configuration is controlled by SIUL2_MSCRn registers. It is available within two
PBRIDGEA_CLK clock cycles after the associated SIUL2_MSCRn bits have been written.
Table 14 shows the WEAK configuration output buffer electrical characteristics.
Table 14. WEAK configuration output buffer electrical characteristics
Symbol Parameter Conditions
R
R
OH_W
OL_W
CC PMOS output impedance
weak configuration
CC NMOS output impedance
weak configuration
4.5 V < V
Push pull, I
4.5 V < V
Push pull, I
DD_HV_IO
< 0.5 mA
OH
DD_HV_IO
< 0.5 mA
OL
1,2
< 5.5 V
< 5.5 V
Value
Unit
Min Typ Max
520 800 1052
520 800 1052
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 35
Page 36
Electrical characteristics
Table 14. WEAK configuration output buffer electrical characteristics (continued)
Value
Symbol Parameter Conditions
1,2
Min Typ Max
f
MAX_W
t
TR_W
t
SKEW_W
CC Output frequency
weak configuration
CC Transition time output pin
weak configuration
4
CC Difference between rise and
CL = 25 pF
C
= 50 pF
L
= 200 pF
C
L
CL = 25 pF,
4.5 V < V
C
= 50 pF,
L
4.5 V < V
C
= 200 pF,
L
4.5 V < V
= 25 pF,
C
L
3.0 V < V
C
= 50 pF,
L
3.0 V < V
C
= 200 pF,
L
3.0 V < V
3
3
3
—— 2MHz
—— 1
— — 0.25
40 — 120 ns
DD_HV_IO
< 5.5 V
80 — 240
DD_HV_IO
< 5.5 V
320 — 820
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
< 5.5 V
< 3.6 V
< 3.6 V
< 3.6 V
5
5
5
50 — 150
100 — 300
350 — 1050
———25%
fall time
I
DCMAX_W
1
All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V
CC Maximum DC current — — — 4 mA
are valid for VSIO[VSIO_xx] = 0
2
During power up operation, the minimum required voltage to come out of reset state is determined by the
V
PORUP_HV
V
PORUP_HV
3
CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added
to calculate total signal capacitance (C
4
Transition time maximum value is approximated by the following formula:
0 pF < C
50 pF < C
5
Only for V
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the
monitor is connected to the V
< 50 pF t
L
< 200 pF t
L
DD_HV_IO_JTAG
(ns) = 22 ns + CL(pF) 4.4 ns/pF
TR_W
(ns) = 50 ns + CL(pF) 3.85 ns/pF
TR_W
segment when VSIO[VSIO_IJ] = 0 or V
DD_HV_IO_MAIN0
= CL + CIN).
TOT
physical I/O segment.
DD_HV_IO_FLEX
segment when VSIO[VSIO_IF] = 0.
Unit
Table 15 shows the MEDIUM configuration output buffer electrical characteristics.
Table 15. MEDIUM configuration output buffer electrical characteristics
Symbol Parameter Conditions
R
R
OH_M
OL_M
CC PMOS output impedance
MEDIUM configuration
CC NMOS output impedance
MEDIUM configuration
4.5 V < V
Push pull, I
4.5 V < V
Push pull, I
DD_HV_IO
OH
DD_HV_IO
OL
MPC5777M Microcontroller Data Sheet, Rev. 6
1,2
< 5.5 V
< 2 mA
< 5.5 V
< 2 mA
Value
Unit
Min Typ Max
135 200 260
135 200 260
NXP Semiconductors36
Page 37
Electrical characteristics
Table 15. MEDIUM configuration output buffer electrical characteristics (continued)
Value
Symbol Parameter Conditions
1,2
Min Typ Max
f
MAX_M
t
TPD50-50
CC Output frequency
MEDIUM configuration
4
CC 50-50 % Output pad
propagation delay time
CL =25pF
C
=50pF
L
= 200 pF
C
L
V
DD_HV_IO
= 25 pF
V
DD_HV_IO
3
3
3
= 5 V +/- 10 %, CL
= 5.0 V +/- 10 %,
——12MHz
—— 6
——1.5
— — 21/17 ns
— — 35/27 ns
CL = 50 pF
t
TR_M
t
SKEW_M
CC Transition time output pin
MEDIUM configuration
5
CC Difference between rise and fall
CL = 25 pF
4.5 V < V
=50pF
C
L
4.5 V < V
C
= 200 pF
L
4.5 V < V
C
= 25 pF,
L
3.0 V < V
= 50 pF,
C
L
3.0 V < V
C
= 200 pF,
L
3.0 V < V
10 — 30 ns
DD_HV_IO
< 5.5 V
20 — 60
DD_HV_IO
< 5.5 V
60 — 200
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
< 5.5 V
< 3.6 V
< 3.6 V
< 3.6 V
12 — 42
6
24 — 86
6
70 — 300
6
———25%
time
I
DCMAX_M
1
All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V
CC Maximum DC current — — — 4 mA
are valid for VSIO[VSIO_xx] = 0
2
During power up operation, the minimum required voltage to come out of reset state is determined by the
V
PORUP_HV
V
PORUP_HV
3
CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added
to calculate total signal capacitance (C
4
If two values are given for propagation delay, the first value is for rising edge signals and the second for falling
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the
monitor is connected to the V
TOT
DD_HV_IO_MAIN0
= CL + CIN).
physical I/O segment.
edge signals.
5
Transition time maximum value is approximated by the following formula:
0 pF < C
50 pF < C
6
Only for V
< 50 pF t
L
< 200 pF t
L
DD_HV_IO_JTAG
(ns) = 5.6 ns + CL(pF) 1.11ns/pF
TR_M
(ns) = 13 ns + CL(pF) 0.96 ns/pF
TR_M
segment when VSIO[VSIO_IJ] = 0 or V
DD_HV_IO_FLEX
segment when VSIO[VSIO_IF] = 0
Unit
Table 16 shows the STRONG configuration output buffer electrical characteristics.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 37
Page 38
Electrical characteristics
Table 16. STRONG configuration output buffer electrical characteristics
Value
Symbol Parameter Conditions
1,2
Min Typ Max
R
OH_S
R
OL_S
f
MAX_S
t
TPD50-50
CC PMOS output impedance
STRONG configuration
CC NMOS output impedance
STRONG configuration
CC Output frequency
STRONG configuration
4
CC 50-50 % Output pad
propagation delay time
4.5 V < V
Push pull, I
4.5 V < V
Push pull, I
CL = 25 pF
CL = 50 pF
C
= 200 pF
L
V
DD_HV_IO
= 25 pF
V
DD_HV_IO
DD_HV_IO
OH
DD_HV_IO
OL
3
3
< 5.5 V
< 8 mA
< 5.5 V
< 8 mA
3
= 5 V +/- 10 %, CL
= 5.0 V +/- 10 %,
30 50 77
30 50 77
——40MHz
——20
—— 5
——8/7ns
——11/9ns
CL = 50 pF
t
TR_S
t
SKEW_S
CC Transition time output pin
STRONG configuration
5
CC Difference between rise and fall
= 25 pF
C
L
4.5 V < V
C
= 50 pF
L
4.5 V < V
C
= 200 pF
L
4.5 V < V
= 25 pF,
C
L
3.0 V < V
C
= 50 pF,
L
3.0 V < V
C
= 200 pF,
L
3.0 V < V
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
DD_HV_IO
< 5.5 V
< 5.5 V
< 5.5 V
< 3.6 V
< 3.6 V
< 3.6 V
———25%
3 — 10 ns
5—16
17 — 50
4—15
6
6—27
6
20 — 83
6
time
I
DCMAX_S
1
All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V
CC Maximum DC current — — — 10 mA
are valid for VSIO[VSIO_xx] = 0
2
During power up operation, the minimum required voltage to come out of reset state is determined by the
V
PORUP_HV
V
PORUP_HV
3
CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be
added to calculate total signal capacitance (C
4
If two values are given for propagation delay, the first value is for rising edge signals and the second for falling
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the
monitor is connected to the V
DD_HV_IO_MAIN0
= CL + CIN).
TOT
physical I/O segment.
edge signals.
5
Transition time maximum value is approximated by the following formula: t
6
Only for V
DD_HV_IO_JTAG
segment when VSIO[VSIO_IJ] = 0 or V
DD_HV_IO_FLEX
(ns) = 4.5 ns + CL(pF) x 0.23 ns/pF.
TR_S
segment when VSIO[VSIO_IF] = 0
Unit
Table 17 shows the VERY STRONG configuration output buffer electrical characteristics.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors38
Page 39
Electrical characteristics
Table 17. VERY STRONG configuration output buffer electrical characteristics
Symbol Parameter Conditions
R
OH_V
R
OL_V
f
MAX_V
t
TPD50-50
CC PMOS output impedance
VERY STRONG configuration
CC NMOS output impedance
VERY STRONG configuration
CC Output frequency
VERY STRONG configuration
6
CC 50-50 % Output pad
propagation delay time
V
DD_HV_IO
= 5.0 V ± 10%,
VSIO[VSIO_xx] = 1
= 8 mA
I
OH
V
DD_HV_IO
VSIO[VSIO_xx] = 0,
I
OH
V
DD_HV_IO
= 7 mA
=3.3V±10%,
4
= 5.0 V ± 10%,
VSIO[VSIO_xx] = 1
I
= 8 mA
OL
V
DD_HV_IO
VSIO[VSIO_xx] = 0,
I
= 7 mA
OL
V
DD_HV_IO
CL = 25 pF
VSIO[VSIO_xx] = 1,
= 15 pF
C
L
V
DD_HV_IO
=3.3V±10%,
4
= 5.0 V ± 10%,
5
4,5
= 5 V +/- 10 %, CL =
25 pF
2,3
1
Value
Unit
Min Typ Max
20 40 72
30 50 90
20 40 72
30 50 90
——50MHz
——50
——5.5ns
t
TR_V
t
TR20-80
t
TRTTL
t
TR20-80
t
SKEW_V
CC 10–90% threshold transition
time output pin VERY
STRONG configuration
CC 20–80% threshold transition
7
time
output pin VERY
STRONG configuration
CC TTL threshold transition time8
for output pin in VERY
STRONG configuration
CC Sum of transition time
20–80% output pin VERY
STRONG configuration
9
CC Difference between rise and
fall time at 20–80%
V
DD_HV_IO
= 50 p F
V
DD_HV_IO
= 15 p F
V
DD_HV_IO
CL = 25 p F
V
DD_HV_IO
CL = 50 p F
V
DD_HV_IO
= 200 pF
C
L
V
DD_HV_IO
C
= 25 p F
L
V
DD_HV_IO
CL = 15 p F
V
DD_HV_IO
= 25 p F
C
L
V
DD_HV_IO
=25pF
C
L
V
DD_HV_IO
=15pF
C
L
V
DD_HV_IO
= 25 pF
C
L
= 5.0 V +/- 10 %, CL
= 3.3 V +/- 10 %, CL
= 5.0 V ± 10%,
5
= 5.0 V ± 10%,
5
= 5.0 V ± 10%,
5
= 5.0 V ± 10%,
5
= 3.3 V ± 10%,
5
= 3.3 V ± 10%,
5
= 5.0 V ± 10%,
= 3.3 V ± 10%,
5
= 5.0 V ± 10%,
5
——6.5ns
— — 7.3/7.6 ns
1—5.3ns
3—12
14 — 45
0.8 — 4 ns
1—5
1—5ns
—— 9ns
—— 9
0—1ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 39
Page 40
Electrical characteristics
Table 17. VERY STRONG configuration output buffer electrical characteristics1 (continued)
Symbol Parameter Conditions
I
DCMAX_VS
1
Refer to FlexRay section for parameter dedicated to this interface.
2
All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V
CC Maximum DC current — — — 10 mA
are valid for VSIO[VSIO_xx] = 0.
3
During power up operation, the minimum required voltage to come out of reset state is determined by the
V
PORUP_HV
V
PORUP_HV
4
Only available on the V
5
CL is the sum of external capacitance. Add device and package capacitances (CIN, defined in the I/O input DC
monitor, which is defined in the voltage monitor electrical characteristics table. Note that the
monitor is connected to the V
DD_HV_IO_JTAG
DD_HV_IO_MAIN0
, V
DD_HV_IO_FLEXE
electrical characteristics table in this Data Sheet) to calculate total signal capacitance (C
6
If two values are given for propagation delay, the first value is for rising edge signals and the second for falling
edge signals.
7
20–80% transition time as per FlexRay standard.
8
TTL transition time as for Ethernet standard.
9
For specification per Electrical Physical Layer Specification 3.0.1, see the dCCTxD
Rise and Fall time of TxD signal at the output pin) specification in TxD output characteristics table in Section TxD
of this Data Sheet.
Table 18 shows the EBI pad electrical specification.
Table 18. EBI pad output electrical specification
2,3
physical I/O segment.
, and V
DD_HV_IO_FLEX
Value
Min Typ Max
segments.
= CL + CIN).
TOT
+dCCTxD
RISE25
FALL25
Unit
(Sum of
Symbol Parameter Conditions
EBI Mode Output Specifications
C
CC External Bus Load Capacitance MSCR[OERC] = b101 — — 10 pF
DRV
1
MSCR[OERC] = b110 — — 20
MSCR[OERC] = b111 — — 30
f
MAX_EBI
CC External Bus Maximum Operat-
C
= 10/20/30 pF — — 66.7 MHz
DRV
ing Frequency
t
TR_EBI
CC 10%–90% threshold transition
C
= 10/20/30 pF 0.9 — 3.0 ns
DRV
time External Bus output pins
t
PD_EBI
CC 50%–50% threshold propaga-
C
= 10/20/30 pF 1.9 — 4.0 ns
DRV
tion delay time External Bus
output pins
t
SKEW_EB
I
DCMAX_E
CC Difference between rise and fall
I
time
CC Maximum DC current — — — 12 mA
BI
GPIO Mode Output Specifications - MSCR[OERC] = b100
Value
Unit
Min Typ Max
———25%
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors40
Page 41
Table 18. EBI pad output electrical specification (continued)
Symbol Parameter Conditions
Electrical characteristics
Value
Unit
Min Typ Max
R
OH_EBI_
GPIO
R
OL_EBI_
GPIO
f
MAX_EBI_
GPIO
I
DCMAX_E
BI_GPIO
1
All EBI mode specifications are valid for V
2
CL is the sum of the capacitance loading external to the device.
CC PMOS output impedance 4.5 V < V
DD_HV_IO_EBI
Push pull, I
CC NMOS output impedance 4.5 V < V
DD_HV_IO_EBI
Push pull, I
CC Output frequency CL =25pF
C
=50pF — — 6
L
= 200 pF — — 1.5
C
L
CC Maximum DC current — — — 4 mA
DD_HV_IO_EBI
= 3.3V +/- 10%.
OH
OH
2
< 5.5 V
< 2 mA
< 5.5 V
< 2 mA
100 225 400
100 200 400
——12MHz
3.7 I/O pad current specification
The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a VDD/VSS supply pair.
Table 19 provides I/O consumption figures.
In order to ensure device reliability, the average current of the I/O on a single segment remain below the I
MAXSEG
in the Table 6 (Absolute maximum ratings). Use the RMS current consumption values to calculate total segment current.
In order to ensure device functionality, the sum of the dynamic and static currents of the I/O on a single segment should remain
below the I
MAXSEG
value given in the Table 8 (Device operating conditions). Use the dynamic current consumption values to
calculate total segment current.
Pad mapping on each segment can be optimized using the pad usage information provided in the I/O Signal Description table.
The sum of all pad usage ratios within a segment should remain below 100%.
value given
NOTE
In order to maintain the required input thresholds for the SENT interface, the sum of all I/O
pad output percent IR drop as defined in the I/O Signal Description table, must be below
50 %. See the I/O Signal Description attachment.
NOTE
The MPC5777M I/O Signal Description and Input Multiplexing Tables are contained in a
Microsoft Excel
the left side of the PDF window, and click it. Double-click on the Excel file to open it and
select the I/O Signal Description Table tab.
NXP Semiconductors 41
workbook file attached to this document. Locate the paperclip symbol on
MPC5777M Microcontroller Data Sheet, Rev. 6
Page 42
Electrical characteristics
Table 19. I/O consumption
Symbol Parameter Conditions
I
RMS_W
I
RMS_M
I
RMS_S
I
RMS_V
I
RMS_EBI
CC RMS I/O current for WEAK
configuration
CC RMS I/O current for MEDIUM
configuration
CC RMS I/O current for STRONG
configuration
CC RMS I/O current for VERY STRONG
configuration
CC RMS I/O current for External Bus
output pins
CL = 25 p F, 2 MHz
= 5.0 V ± 10%
V
DD
C
= 50 pF, 1 MHz
L
= 5.0 V ± 10%
V
DD
C
= 25 pF, 2 MHz
L
V
= 3.3 V ± 10%
DD
C
= 50 pF, 1 MHz
L
V
= 3.3 V ± 10%
DD
CL = 25 pF, 12 MHz
= 5.0 V ± 10%
V
DD
C
= 50 pF, 6 MHz
L
V
= 5.0 V ± 10%
DD
C
= 25 pF, 12 MHz
L
V
= 3.3 V ± 10%
DD
= 50 pF, 6 MHz
C
L
= 3.3 V ± 10%
V
DD
CL = 25 pF, 50 MHz
V
= 5.0 V ± 10%
DD
C
= 50 pF, 25 MHz
L
V
= 5.0 V ± 10%
DD
= 25 pF, 50 MHz
C
L
= 3.3 V ± 10%
V
DD
C
= 50 pF, 25 MHz
L
V
= 3.3 V ± 10%
DD
CL = 25 pF, 50 MHz,
V
= 5.0V +/- 10%
DD
= 50 pF, 25 MHz,
C
L
= 5.0V ± 10%
V
DD
C
= 25 pF, 50 MHz,
L
V
= 3.3V ± 10%
DD
C
= 25 pF, 25 MHz,
L
V
= 3.3V ± 10%
DD
C
= 6 pF, f
DRV
V
DD_HV_IO_EBI
C
= 12 pF, f
DRV
V
DD_HV_IO_EBI
C
= 18 pF, f
DRV
V
DD_HV_IO_EBI
C
= 30 pF, f
DRV
V
DD_HV_IO_EBI
EBI
= 3.3 V ± 10%
EBI
= 3.3 V ± 10%
EBI
= 3.3 V ± 10%
EBI
= 3.3 V ± 10%
1
2
= 66.7 MHz,
= 66.7 MHz,
= 66.7 MHz,
= 66.7 MHz,
Value
Unit
Min Typ Max
——1.1mA
——1.1
——0.6
——0.6
——4.7mA
——4.8
——2.6
——2.7
——19mA
——19
——10
——10
——22mA
——22
——11
——11
—— 9mA
——15
——27
——42
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors42
Page 43
Electrical characteristics
Table 19. I/O consumption
Symbol Parameter Conditions
3
I
DYN_W
I
DYN_M
I
DYN_S
I
DYN_V
I
DYN_EBI
1
I/O current consumption specifications for the 4.5 V <= V
and VSIO[VSIO_xx] = 0 for 3.0 V <= V
CC Dynamic I/O current for WEAK
configuration
CC Dynamic I/O current for MEDIUM
configuration
CC Dynamic I/O current for STRONG
configuration
CC Dynamic I/O current for VERY
STRONG configuration
4
CC Dynamic I/O current for External Bus
output pins
DD_HV_IO
CL = 25 p F,
V
C
V
C
V
C
V
CL = 25 p F,
V
C
V
C
V
C
V
CL = 25 p F,
V
C
V
C
V
C
V
CL = 25 p F,
V
C
V
C
V
C
V
C
V
C
V
C
V
<= 3.6 V.
= 5.0 V ± 10%
DD
= 50 p F,
L
= 5.0 V ± 10%
DD
= 25 p F,
L
= 3.3 V ± 10%
DD
= 50 p F,
L
= 3.3 V ± 10%
DD
= 5.0 V ± 10%
DD
= 50 p F,
L
= 5.0 V ± 10%
DD
= 25 p F,
L
= 3.3 V ± 10%
DD
= 50 p F,
L
= 3.3 V ± 10%
DD
= 5.0 V ± 10%
DD
= 50 p F,
L
= 5.0 V ± 10%
DD
= 25 p F,
L
= 3.3 V ± 10%
DD
= 50 p F,
L
= 3.3 V ± 10%
DD
= 5.0 V ± 10%
DD
= 50 p F,
L
= 5.0 V ± 10%
DD
= 25 p F,
L
= 3.3 V ± 10%
DD
= 50 p F,
L
= 3.3 V ± 10%
DD
= 10 pF, f
DRV
DD_HV_IO_EBI
= 20 pF, f
DRV
DD_HV_IO_EBI
= 30 pF, f
DRV
DD_HV_IO_EBI
DD_HV_IO
1
2
Value
Unit
Min Typ Max
——5.0mA
——5.1
——2.2
——2.3
——15mA
——15.5
——7.0
——7.1
——50mA
——55
——22
——25
——60mA
——64
——26
——29
= 66.7 MHz,
EBI
——30mA
= 3.3 V ± 10%
= 66.7 MHz,
EBI
——50
= 3.3 V ± 10%
= 66.7 MHz,
EBI
——80
= 3.3 V ± 10%
<= 5.5 V range are valid for VSIO_[VSIO_xx] = 1,
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 43
Page 44
Electrical characteristics
V
IL
V
DD
V
DDMIN
PORST
V
IH
device start-up phase
V
DD_POR
PORST undriven.
Device reset by
internal power-on
reset.
PORST driven low by
internal power-on reset.
Device reset forced by
external circuitry.
2
During power up operation, the minimum required voltage to come out of reset state is determined by the V
monitor, which is defined in the voltage monitor electrical characterstics table. Note that the V
connected to the V
3
Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible
DD_HV_IO_MAIN0
physical I/O segment.
PORUP_HV
(timed output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.
4
For I
DYN_EBI_GPIO
dynamic current for EBI GPIO mode use the I
DYN_M
values.
3.8 Reset pad (PORST, ESR0) electrical characteristics
The device implements a dedicated bidirectional reset pin (PORST).
NOTE
PORST pin does not require active control. It is possible to implement an external pull-up
to ensure correct reset exit sequence. Recommended value is 4.7 k.
PORUP_HV
monitor is
Figure 10. St art-up reset requirements
Figure 11 describes device behavior depending on supply signal on PORST
1. PORST
2. PORST
3. PORST
a) PORST
b) PORST
low pulse amplitude is too low—it is filtered by input buffer hysteresis. Device remains in current state.
low pulse duration is too short—it is filtered by a low pass filter. Device remains in current state.
low pulse generates a reset:
low but initially filtered during at least W
potentially filtered until W
. Device state is unknown: it may either be reset or remains in current
NFRST
. Device remains initially in current state.
FRST
state depending on other factors (temperature, voltage, device).
c) PORST
asserted for longer than W
MPC5777M Microcontroller Data Sheet, Rev. 6
. Device is under reset.
NFRST
:
NXP Semiconductors44
Page 45
Electrical characteristics
V
IL
V
IH
V
DD
filtered by
hysteresis
filtered by
lowpass filter
W
FRST
W
NFRST
filtered by
lowpass filter
W
FRST
unknown reset
state
device under hardware reset
internal
reset
1 2 3a 3b 3c
V
HYS
V
PORST, VESR0
Figure 11. Noise filtering on reset signal
Table 20. Reset electrical characteristics
Symbol Parameter Conditions
V
IH
SR Input high level TTL
(Schmitt trigger)
V
SR Input low level TTL
IL
(Schmitt trigger)
V
HYS
CC Input hysteresis TTL
(Schmitt trigger)
V
DD_POR
CC Minimum supply for strong
pull-down activation
1
Value
Unit
Min Typ Max
—
2.2 — V
DD_HV_IO
+0.4
V
— –0.4 — 0.8 V
—300——mV
———1.2V
NXP Semiconductors 45
MPC5777M Microcontroller Data Sheet, Rev. 6
Page 46
Electrical characteristics
Symbol Parameter Conditions
I
OL_R
|I
WPU
CC Strong pull-down current
| CC Weak pull-up current absolute
value
|I
| CC Weak pull-down current
WPD
absolute value
W
FRST
SR PORST and ESR0 input
filtered pulse
Table 20. Reset electrical characteristics (continued)
Min Typ Max
2
Device under power-on reset
V
DD_HV_IO
= 0.35 * V
V
OL
= V
DD_HV_IO
DD_POR
,
Device under power-on reset
3.0 V < V
DD_HV_IO
<5.5V,
VOL>0.9V
ESR0 pin
= 0.69 * V
V
IN
ESR0
pin
VIN = 0.49 * V
DD_HV_IO
DD_HV_IO
PORST pin
VIN = 0.69 * V
PORST
= 0.49 * V
V
IN
DD_HV_IO
pin
DD_HV_IO
— — — 500 ns
0.2 — — mA
11 — — mA
23 — — µA
——82
——130µA
40 — —
Value
1
Unit
W
NFRST
SR PORST and ESR0 input not
— 2000 — — ns
filtered pulse
W
FNMI
W
NFNMI
1
An external 4.7 KOhm pull-up resistor is recommended to be used with the PORST and ESR0 pins for fast negation
SR ESR1 input filtered pulse — — — 15 ns
SR ESR1 input not filtered pulse — 400 — — ns
of the signals.
2
I
applies to both PORST and ESR0: Strong pull-down is active on PHASE0 for PORST. Strong pull-down is active
OL_R
on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for ESR0.
NOTE
PORST can optionally be connected to an external power-on supply circuitry.
NOTE
No restrictions exist on reset signal slew rate apart from absolute maximum rating
compliance.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors46
Page 47
Electrical characteristics
PLL0
PLL1
RCOSC
XOSC
PLL0_PHI1
PLL0_PHI
PLL1_PHI
3.9 Oscillator and FMPLL
The Reference PLL (PLL0) and the System PLL (PLL1) generate the system and auxiliary clocks from the main oscillator
driver.
Figure 12. PLL integration
Table 21. PLL0 electrical characteristics
Value
f
PLL0IN
PLL0IN
f
PLL0VCO
f
PLL0VCOFR
f
PLL0PHI
t
PLL0LOCK
PLL0PHISPJ
PLL0PHI1SPJ
Symbol Parameter Conditions
SR PLL0 input clock
SR PLL0 input clock duty cycle
1,2
—8—44MHz
2
—40—60%
CC PLL0 VCO frequency — 600 — 1250 MHz
CC PLL0 VCO free running
—35—400MHz
frequency
CC PLL0 output frequency — 4.762 — 400 MHz
CC PLL0 lock time — — — 110 µs
| CC PLL0_PHI single period jitter
fPLL0IN = 20 MHz (resonator)
| CC PLL0_PHI1 single period jitter
fPLL0IN = 20 MHz (resonator)
3
3
f
PLL0PHI
6-sigma
f
PLL0PHI1
6-sigma
= 400 MHz,
= 40 MHz,
Min Typ Max
——200ps
— — 300
Unit
4
ps
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 47
Page 48
Electrical characteristics
Symbol Parameter Conditions
PLL0LTJ
Table 21. PLL0 electrical characteristics (continued)
3,4
CC PLL0 output long term jitter
f
= 20 MHz (resonator),
PLL0IN
VCO frequency = 800 MHz
10 periods
accumulated jitter
(80 MH z eq uivalent
frequency), 6-sigma
pk-pk
16 periods
accumulated jitter
(50 MH z eq uivalent
frequency), 6-sigma
pk-pk
Value
Unit
Min Typ Max
——±250ps
——±300ps
long term jitter
——±500ps
(< 1 MHz equivalent
frequency), 6-sigma
pk-pk)
CC PLL0 consumption FINE LOCK state — — 5 mA
1
I
PLL0
f
frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range 8
PLL0IN
MHz–20 MHz.
2
PLL0IN clock retrieved directly from either internal RCOSC or external XOSC clock. Input characteristics are granted when
using internal RCOSC or external oscillator is used in functional mode.
3
PLL jitter is guaranteed when transient currents on the V
supply are within the I
DDLV
parameter value in Table 10 (DC
SPIKE
electrical specifications).
4
Noise on the V
V
supply with frequency content in the range of 40 KHz – 50 MHz must be filtered externally to the device.
DD_LV
supply with frequency content below 40 KHz and above 50 MHz is filtered by the PLL. Noise on the
DD_LV
Table 22. PLL1 electrical characteristics
Value
Symbol Parameter Conditions
Min Typ Max
f
PLL1IN
PLL1IN
f
PLL1VCO
f
PLL1VCOFR
f
PLL1PHI
t
PLL1LOCK
f
PLL1MOD
PLL1MOD
SR PLL1 input clock
SR PLL1 input clock duty cycle
CC PLL1 VCO frequency — 600 — 12 50 MHz
CC PLL1 VCO free running
frequency
CC PLL1 output clock PHI — 4.762 — 600 MHz
CC PLL1 lock time — — — 100 µs
CC PLL1 modulation frequency — — — 250 kHz
| CC PLL1 modulation depth (when
enabled)
1
1
—38—78MHz
—35—65%
— 35 — 400 MHz
Center spread 0.25 — 2 %
Down spread 0.5 — 4 %
Unit
I
PLL1
1
PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when
CC PLL1 consumption FINE LOCK state — — 6 mA
using internal PLL0 or external oscillator is used in functional mode.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors48
Page 49
Electrical characteristics
T able 23. External Oscillator electrical specifications
1
Value
Symbol Parameter Conditions
Min Max
f
XTAL
CC Crystal Frequency Range
2
—48MHz
—>820
— >20 40
t
V
IHEXT
V
ILEXT
t
cst
rec
CC Crystal start-up time
CC Crystal recovery time
CC EXTAL input high voltage
3,4
5
6,7
V
(External Clock Input)
CC EXTAL input low voltage
6,7
V
= 0.28 * V
REF
= 0.28 * V
REF
T
=150°C — 5 ms
J
——0.5ms
DD_HV_IO_JTAGVREF
+
—V
0.6
DD_HV_IO_JTAG
—V
- 0.6 V
REF
(External Clock Input)
C
S_xtal
V
EXTAL
V
HYS
I
XTAL
1
All oscillator specifications are valid for VDD_HV_IO_JTAG= 3.0 V – 5.5 V.
2
The range is selectable by UTEST miscellaneous DCF clients XOSC_LF_EN and XOSC_EN_40MHZ.
3
This value is determined by the crystal manufacturer and board design.
4
Proper PC board layout procedures must be followed to achieve specifications.
5
Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
CC Total on-chip stray capacitance
on XTA L/EXTAL pins
CC Oscillation Amplitude on the
EXTAL pin after startup
8
9
BGA416, BGA512 8 8.6 pF
= –40 °C to 1 50 °C 0.5 1.6 V
T
J
CC Comparator Hysteresis TJ= –40 °C to 150 °C 0.1 1.0 V
CC XTAL current
13,10
T
= –40 °C to 15 0 °C — 14 mA
J
capacitor value.
6
This parameter is guaranteed by design rather than 100% tested.
7
Applies to an external clock input and not to crystal mode.
8
See crystal manufacturer’s specification for recommended load capacitor (CL) values.The external oscillator requires
external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (C
S_EXTAL/CS_XTAL
and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load
capacitor value is selected via S/W to match the crystal manufacturer’s specification, while accounting for on-chip and PCB
capacitance.
9
Amplitude on the EXTAL pin after startup is determined by the ALC block, i.e., the Automatic Level Control Circuit. The
function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to
reduce power, distortion, and RFI, and to avoid over-driving the crystal. The operating point of the ALC is dependent on the
crystal value and loading conditions.
10
I
is the oscillator bias current out of the XTAL pin with both EXTAL and XT AL pins grounded. This is the maximum
XTAL
current during startup of the oscillator. The current after oscillation is typically in the 2–3 mA range and is dependent on the
load and series resistance of the crystal. Test circuit is shown in Figure 13.
Unit
)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 49
Page 50
Electrical characteristics
Table 24. Selectable load capacitance
load_cap_sel[4:0] from DCF record Load capacitance
1,2
(pF)
00000 1.032
00001 1.976
00010 2.898
00011 3.823
00100 4.751
00101 5.679
00110 6.605
00111 7.536
01000 8.460
01001 9.390
01010 10.317
01011 11.245
01100 12.173
01101 13.101
01110 14.029
01111 14.957
1
Values are determined from simulation across process corners and voltage and temperature
variation. Capacitance values vary ±12% across process, 0.25% across voltage, and no variation
across temperature.
2
Values in this table do not include the die and package capacitances given by Cs_xtal/Cs_extal in
Table 23 (External Oscill ator electrical specifications).
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors50
Page 51
Figure 13. Test circuit
V
+
-
A
I
XTAL
Bias
Current
Comparator
OFF
VSSOSC
XTAL
EXTAL
VSS
PCB
GND
Tester
ALC
Z = R + jL
Conditions
VEXTAL=0 V
VXTAL=0 V
ALC INACTIVE
VDDOSC
Electrical characteristics
Table 25. Internal RC Oscillator electrical specifications
Value
Symbol Parameter Conditions
Min Typ Max
f
Target
f
var_noT
f
var_T
var_SW
f
start_noT
T
start_T
I
AVDD5
I
DVDD12
1
f
T
1
IRC software trimmed accuracy is performed either with the CMU_0 clock monitor, using the XOSC as a reference or
through the CCCU (CAN clock control Unit), extracting reference clock from CAN master clock. Software trim must be
repeated as the device operating temperature varies in order to maintain the specified accuracy.
CC IRC target frequency — — 16 — MHz
CC IRC frequency variation
T < 150 oC–8 — 8 %
without temperature
compensation
CC IRC frequency variation with
T < 150 oC–3 — 3 %
temperature compensation
CC IRC software trimming
accuracy
Trimming
temperature
–1 — 1 %
IRC Software trimming step — -48 — +40 kHz
CC Startup time to reach within
f
var_noT
CC Startup time to reach within
f
var_T
No trimming — — 5 µs
Factory
— — 120 µs
trimming
already applied
CC Current consu mp tio n on 5 V
power supply
CC Current consumption on 1.2 V
power supply
After T
After T
start_T
start_T
— — 400 µA
— — 175 µA
Unit
NXP Semiconductors 51
MPC5777M Microcontroller Data Sheet, Rev. 6
Page 52
Electrical characteristics
R
SW1
C
P2
C
S
V
DD
Sampling
INTERNAL CIRCUIT SCHEME
R
SW1
Channel Selection Switch Impedance
R
AD
Sampling Switch Impedance
C
P
Pin Capacitance (two cont ributions, CP1 and CP2)
C
S
Sampling Capacitance
R
CMSW
Common mode switch
R
CML
Common mode resistive ladder
This figure can be used as approximation circuitry for external filtering definition.
C
P1
R
AD
Channel
Selection
Common mode
switch
Common mode
resistive ladder
R
SW1
C
P3
C
S
V
DD
Sampling
RSW: Channel Selection Switch Impedance (two contributions R
SW1
and R
SW2
)
R
AD
: Sampling Switch Impedance
C
P
: Pin Capacitance (three contributions, CP1, CP2 and CP3)
C
S
: Sampling Capacitance
R
CMSW:
Common mode switch
R
CML
: Common mode resistive ladder
The above figure can be used as approximation circuitry for external filtering definition.
C
P1
R
AD
Channel
Selection
C
P2
Extended
R
SW2
Switch
Common mode
switch
Common mode
resistive ladder
INTERNAL CIRCUIT SCHEME
3.10 ADC specifications
3.10.1 ADC input description
Figure 14 shows the input equivalent circuit for fast SARn channels.
Figure 14. Input equivalent circuit (Fast SARn channels)
Figure 15 shows the input equivalent circuit for SARB channels.
Figure 15. Input equivalent circuit (SARB channels)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors52
Page 53
Electrical characteristics
Table 26. ADC pin specification
Symbol Parameter Conditions
I
LK_INUD
I
LK_INUSD
I
LK_INREF
I
LK_INOUT
I
INJ
C
HV_ADC
C
P1
C
P2
CC Input leakage current, two ADC
channels input with weak pull-up and
weak pull-down
CC Input leakage current, two ADC
channels input with weak pull-up and
strong pull-down
CC Input leakage current, two ADC
channels input with weak pull-up and
weak pull-down and alternate reference
CC Input leakage current, two ADC
channels input, GPIO output buffer with
weak pull-up and weak pull-down
CC Injection current on analog input
preserving functionality
SR V
DD_HV_ADV
external capacitance
CC Pad capacitance — 0 10 pF
CC Internal routing capacitance SARn channels 0 0.5 pF
TJ< 40 °C — 50 nA
T
< 150 °C — 150
J
TJ< 40 °C — 80 nA
< 150 °C — 250
T
J
TJ<40°C — 160 nA
< 150 °C — 400
T
J
TJ<40°C — 140 nA
< 150 °C — 380
T
J
Applies to any analog pins –3 3 mA
2
SARB channels 0 1
1
Value
Unit
Min Max
12.2µF
R
C
C
SWn
P3
S
CC Internal routing capacitance Only for SARB channels 0 1 pF
CC SAR ADC sampling capacitance — 6 8.5 pF
CC Analog switches resistance SARn channels 0 1.1 k
SARB channels 0 1.7
R
R
CMSW
R
CMRL
R
SAFEPD
AD
CC ADC input analog switches resistance — 0 0.6 k
CC Common mode switch resistance — 0 2.6 k
CC Common mode resistive ladder — 0 3.5 k
3
CC Discharge resistance for AN7/AN35
—0300
channels (strong pull-down for safety)
1
All specifications in this table valid for the full input voltage range for the analog inputs.
2
For noise filtering, add a high frequency bypass capacitance of 0.1 µF between V
3
Safety pull-down is available for port pin PB[5] and PE[14].
DD_HV_ADV
and V
SS_HV_ADV
.
3.10.2 SAR ADC electrical specification
The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters with full capacitive DAC. The
SARn architecture allows input channel multiplexing.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 53
Page 54
Electrical characteristics
Table 27. SARn ADC electrical specification
Symbol Parameter Conditions
V
ALTREF
V
IN
f
ADCK
t
ADCPRECH
V
PRECH
V
INTREF
t
ADCSAMPLE
SR ADC alternate
reference voltage
SR ADC input signal 0 < VIN < V
SR Clock frequency TJ< 150 °C 7.5 14.6 MHz
SR ADC precharge time Fast SAR—fast precharge 135 — ns
SR Precharge voltage
precision
CC Internal reference
voltage precision
SR ADC sample time
V
ALTREF
< V
DD_HV_IO_MAIN
Fast SAR—full precharge 270 —
Slow SAR (SARADC_B)—fast
precharge
Slow SAR (SARADC_B)—full
precharge
Full precharge
V
T
PRECH
<150°C
J
= V
DD_HV_ADR_S
Fast precharge
V
T
PRECH
<150°C
J
= V
DD_HV_ADR_S
Applies to all internal reference
points (V
1/3 * V
2/3 * V
V
2
Fast SAR – 12-bit configuration 0.750 — µs
SS_HV_ADR_S
DD_HV_ADR_S
DD_HV_ADR_S
DD_HV_ADR_S
Slow SAR (SARADC_B) – 12-bit
configuration
DD_HV_IO_MAIN
,
,
,
)
1
Value
Unit
Min Max
2.0 V
V
SS_HV_ADR_SVDD_HV_ADR_S
DD_HV_ADV_S
V
V
270 —
540 —
–0.25 0.25 V
/2
–0.5 0.5 V
/2
0.20 0.20 V
1.500 —
t
ADCEVAL
I
ADCREFH
I
ADCREFL
SR ADC evaluation time 12-bit configuration (25 clock
cycles)
3,4
CC ADC high reference
current
Run mode t
conv
(average across all codes)
Run mode t
conv
(average across all codes)
Power Down mode — 6
5
conv
<= 5.5 V
conv
<= 5.5 V
4
CC ADC low reference
current
Bias Current
Run mode t
V
DD_HV_ADR_S
Run mode t
V
DD_HV_ADR_S
Power Down mode
V
DD_HV_ADR_S
<= 5.5 V
MPC5777M Microcontroller Data Sheet, Rev. 6
5µs
=2.5µs
5µs
=2.5µs
1.712 — µs
—7µA
—7
—+2
—15µA
—30
—1
NXP Semiconductors54
Page 55
Table 27. SARn ADC electrical specification1 (continued)
Symbol Parameter Conditions
4
I
ADV_S
TUE
12
CC V
DD_HV_ADV_S
power
supply current (each
ADC)
CC Total unadjusted error
in 12-bit configuration
Run mode t
Run mode t
5µs — 4.0 mA
conv
= 2.5 µs — 4.0
conv
Power Down mode — 1 .0
TJ<150°C,
6
V
DD_HV_ADV_S
V
DD_HV_ADR_S
>4V,
>4V
TJ<150°C,
V
DD_HV_ADV_S
4V>V
DD_HV_ADR_S
T
< 150 °C,
J
4V>V
DD_HV_ADV_S
>4V,
Electrical characteristics
Value
Unit
Min Max
–4 4 LSB
(12b)
–6 6
>2V
–12 12
>3.5V
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 55
Page 56
Electrical characteristics
Symbol Parameter Conditions
Table 27. SARn ADC electrical specification1 (continued)
Value
Unit
Min Max
TUE
CC TUE degradation due
12
to V
DD_HV_ADR_S
with respect to
V
DD_HV_ADV_S
offset
V
< V
IN
DD_HV_ADV_S
V
DD_HV_ADR_S
[0:25 mV]
V
< V
IN
DD_HV_ADV_S
V
DD_HV_ADR_S
[25:50 mV]
V
< V
IN
DD_HV_ADV_S
V
DD_HV_ADR_S
[50:75 mV]
V
< V
IN
DD_HV_ADV_S
V
DD_HV_ADR_S
[75:100 mV]
V
DD_HV_ADV_S
V
DD_HV_ADR_S
V
DD_HV_ADR_S
[0:25 mV]
V
DD_HV_ADV_S
V
DD_HV_ADR_S
V
DD_HV_ADR_S
[25:50 mV]
V
DD_HV_ADV_S
V
DD_HV_ADR_S
V
DD_HV_ADR_S
[50:75 mV]
V
DD_HV_ADV_S
V
DD_HV_ADR_S
V
DD_HV_ADR_S
[75:100 mV]
V
DD_HV_ADV_S
V
DD_HV_ADV_S
V
DD_HV_ADV_S
V
DD_HV_ADV_S
< V
<
IN
V
DD_HV_ADV_S
< V
<
IN
V
DD_HV_ADV_S
< V
<
IN
V
DD_HV_ADV_S
< V
<
IN
V
DD_HV_ADV_S
00LSB
–2 2
–4 4
–6 6
–2.5 2.5
–4 4
–7 7
–12 12
(12b)
DNL CC Differential
non-linearity
INL CC Integral non-linearity 4.0 V < V
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
V
DD_HV_ADV_S
V
DD_HV_ADR_S
4.0 V < V
V
DD_HV_ADV_S
V
DD_HV_ADR_S
DD_HV_ADV_S
DD_HV_ADR_S
> 4 V
> 4 V
= 2V
= 2 V
< 5.5 V
< 5.5 V
–1 2 LSB
–3 3 LSB
–5 5
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2
Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB
within the sampling window. Please refer to Figure 14 and Figure 15 for models of the internal ADC circuit, and the
values to use in external RC sizing and calculating the sampling window duration.
3
I
ADCREFH
and I
ADCREFL
are independent from ADC clock frequency. It depends on conversion rate: consumption is
driven by the transfer of charge between internal capacitances during the conversion.
4
Current parameter values are for a single ADC.
5
Extra bias current is present only when BIAS is selected.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors56
(12b)
(12b)
Page 57
Electrical characteristics
6
This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to
± 6 LSB.
3.10.3 S/D ADC electrical specification
The SDn ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps maximum output rate.
Table 28. SDn ADC electrical specification
Symbol Parameter Conditions
1
Value
Min Typ Max
Unit
V
V
IN_PK2PK
IN
SR ADC input signal — 0
2
SR Input range peak to
peak
V
IN_PK2PK=VINP
4
V
INM
Single ended
V
INM=VSS_HV_ADR_D
3
–
Single ended
=0.5*V
V
INM
DD_HV_ADR_D
GAIN = 1
Single ended
=0.5*V
V
INM
DD_HV_ADR_D
GAIN = 2,4,8,16
Differential,
f
ADCD_M
SR S/D modulator Input
0< VIN < V
—414.416MHz
DD_HV_IO_MAIN
Clock
f
ADCD_S
SR Output conversion
— — — 333 ksps
rate
—
CC Oversampling ratio Internal modulator 24 — 256 —
External modulator — — 256 —
RESOLUTION
CC S/D register
resolution
5
2’s complement notation 16 bit
GAIN SR ADC gain Defined via ADC_SD[PGA]
register. Only integer powers of 2
are valid gain values.
—V
V
DD_HV_ADR_D
±0.5*V
DD_HV_ADR_D
±V
DD_HV_ADR_D
±V
DD_HV_ADR_D
DD_HV_ADV
/GAIN V
/GAIN
/GAIN
_D
V
1— 16 —
CC Absolute value of the
GAIN
ADC gain error
6,7
Before calibration (applies to gain
setting = 1)
After calibration, V
DD_HV_ADR_D
—— 1.5 %
—— 5 mV
5%
V
DD_HV_ADV_D
T
50 °C
J
After calibration, V
10%
DD_HV_ADR_D
—— 7.5
5%
V
DD_HV_ADV_D
100 °C
T
J
After calibration, V
10%
DD_HV_ADR_D
—— 10
5%
V
DD_HV_ADV_D
150 °C
T
J
10%
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 57
Page 58
Electrical characteristics
Symbol Parameter Conditions
Table 28. SDn ADC electrical specification1 (continued)
Value
Unit
Min Typ Max
V
SNR
OFFSET
DIFF150
CC Input Referred Offset
Error
6,7,8
CC Signal to noise ratio in
differential mode
150 ksps output rate
Before calibration (applies to all
gain settings – 1, 2, 4, 8, 16)
After calibration,
V
DD_HV_ADR_D
50 °C
T
J
After calibration, V
10%
DD_HV_ADV_D
10%
100 °C
T
J
After calibration, V
DD_HV_ADV_D
10%
150 °C
T
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D=VDD_HV_ADV_D
GAIN = 1
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 2
T
< 150 °C
J
4.5 < V
V
DD_HV_ADR_D
= V
DD_HV_ADV_D
= V
GAIN = 4
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 8
T
< 150 °C
J
4.5 < V
V
DD_HV_ADR_D
GAIN = 16
T
< 150 °C
J
= V
DD_HV_ADV_D
= V
9,10,17
<5.5
9,10,17
<5.5
DD_HV_ADV_D
9,10,17
<5.5
DD_HV_ADV_D
9,10,17
<5.5
DD_HV_ADV_D
9,10,17
<5.5
DD_HV_ADV_D
— 10*
1+1/gain)
(
20 mV
—— 5
0.5 10
7.5
80 — — dBFS
77 — —
74 — —
71 — —
68 — —
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors58
Page 59
Table 28. SDn ADC electrical specification1 (continued)
Symbol Parameter Conditions
SNR
DIFF333
CC Signal to noise ratio in
differential mode
333 ksps output rate
SNR
SE150
CC Signal to noise ratio in
single ended mode
150 ksps output
11
rate
SFDR CC Spurious free
dynamic range
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 1
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 2
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 4
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 8
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 16
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 1
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 2
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 4
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D
GAIN = 8
T
< 150 °C
J
4.5 < V
DD_HV_ADV_D
V
DD_HV_ADR_D=VDD_HV_ADV_D
GAIN = 16
T
< 150 °C
J
GAIN = 1 60 — — dBc
GAIN = 2 60 — —
GAIN = 4 60 — —
<5.5
= V
DD_HV_ADV_D
<5.5
= V
DD_HV_ADV_D
<5.5
= V
DD_HV_ADV_D
<5.5
= V
DD_HV_ADV_D
<5.5
= V
DD_HV_ADV_D
<5.5
= V
DD_HV_ADV_D
<5.5
= V
DD_HV_ADV_D
<5.5
= V
DD_HV_ADV_D
<5.5
= V
DD_HV_ADV_D
9,10,17
9,10,17
9,10,17
9,10,17
9,10,17
9,10,17
9,10,17
9,10,17
9,10,17
<5.5
9,10,17
Electrical characteristics
Value
Unit
Min Typ Max
74 — — dBFS
71 — —
68 — —
65 — —
62 — —
74 — — dBFS
71 — —
68 — —
65 — —
62 — —
GAIN = 8 60 — —
GAIN = 16 60 — —
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 59
Page 60
Electrical characteristics
Symbol Parameter Conditions
Table 28. SDn ADC electrical specification1 (continued)
Value
Unit
Min Typ Max
V
V
Z
DIFF
Z
CM
R
BIAS
INTCM
V
BIAS
BIAS
V
cmrr
D Differential Input
impedance
1213
GAIN=1 1000 1250 1500 k
GAIN=2 600 800 1000
GAIN=4 300 400 500
GAIN=8 200 250 300
GAIN=16 200 250 300
D Common Mode Input
impedance14
15
GAIN=1 1400 1800 2200 k
GAIN=2 1000 1300 1600
GAIN=4 700 950 1150
GAIN=8 500 650 800
GAIN=16 500 650 800
D Bare Bias resistance — 110 144 180 k
D common mode input
reference voltage
16
CC Bias voltage — — V
—-12—+12%
DD_HV_
ADR_D
/2
—V
CC Bias voltage accuracy — –2.5 — +2.5 %
SR Common mode
—54——dB
rejection ratio
R
Caaf
f
PASSBAND
RIPPLE
F
rolloff
SR Anti-aliasing filter External series resistance — — 20 k
CC Filter capacitances 180 — — pF
CC Pass band
CC Pass band ripple
CC Stop band attenuation [0.5 * f
17
18
0.333 * f
[1.0 * f
[1.5 * f
[2.0 * f
[2.5 * f
ADCD_S
ADCD_S
ADCD_S
ADCD_S
ADCD_S
ADCD_S
— 0.01 — 0.333 *
f
ADCD_S
–1 — 1 %
, 1.0 * f
, 1.5 * f
, 2.0 * f
, 2.5 * f
, f
ADCD_M
]40— —dB
ADCD_S
]45— —
ADCD_S
]50— —
ADCD_S
]55— —
ADCD_S
/2] 60 — —
kHz
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors60
Page 61
Table 28. SDn ADC electrical specification1 (continued)
Symbol Parameter Conditions
Electrical characteristics
Value
Unit
Min Typ Max
GROUP
CC Group delay Within pass band – T clk is f
/ 2
OSR = 24 — — 238.5 Tclk
OSR = 28 — — 278
OSR = 32 — — 317.5
OSR = 36 — — 357
OSR = 40 — — 396.5
OSR = 44 — — 436
OSR = 48 — — 475.5
OSR = 56 — — 554.5
OSR = 64 — — 633.5
OSR = 72 — — 712.5
OSR = 75 — — 699
OSR = 80 — — 791.5
OSR = 88 — — 870.5
OSR = 96 — — 949.5
OSR = 112 — — 1107.5
OSR = 128 — — 1265.5
OSR = 144 — — 1423.5
ADCD_M
—— — —
f
HIGH
t
STARTUP
t
LATENCY
CC High pass filter 3dB
frequency
CC Start-up time from
power down state
CC Latency between
input data and
converted data when
input mux does not
19
change
MPC5777M Microcontroller Data Sheet, Rev. 6
OSR = 160 — — 1581.5
OSR = 176 — — 1739.5
OSR = 192 — — 1897.5
OSR = 224 — — 2213.5
OSR = 256 — — 2529.5
Distortion within pass band –0.5/
f
ADCD
_S
Enabled — 10e-5*
— +0.5/
f
ADCD_S
f
ADCD_S
——
— — — 100 µs
HPF = ON — —
HPF = OFF — —
GROUP
f
ADCD_S
GROUP
+
—
—
—
NXP Semiconductors 61
Page 62
Electrical characteristics
Symbol Parameter Conditions
Table 28. SDn ADC electrical specification1 (continued)
Value
Unit
Min Typ Max
t
SETTLING
t
ODRECOVERY
C
S_D
I
BIAS
I
ADV_D
I
ADR_D
SINAD
DIFF150
CC Settling time after
mux change
CC Overdrive recovery
time
Analog inputs are muxed
HPF = ON
——2*
3*f
HPF = OFF — — 2*
2*f
After input comes within range
——2*
from saturation
GROUP
ADCD_S
GROUP
ADCD_S
GROUP
f
ADCD_S
+
—
+
—
+
—
HPF = ON
CC S/D ADC sampling
capacitance after
sampling switch
20
HPF = OFF — — 2*
GROUP
GAIN = 1, 2, 4, 8 — — 75*GAIN fF
GAIN = 16 — — 600 fF
—
CC Bias consumption At least 1 ADCD enabled 3.5 mA
CC V
DD_HV_ADV_D
power
ADCD enabled — — 3.5 mA
supply current (each
ADC)
CC Sum of all ADC
reference
ADCD enabled, f
14.4 MHz
ADCD_M
=
— — 30 µA
consumption
CC Signal to Noise and
Distortion Ratio,
Differential Mode,
150 Ksps output rate
Gain = 1
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
= V
DD_HV_ADV_D
< 5.5 V
72 — — dBFS
Gain = 2
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 4
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 8
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 16
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
72 — —
< 5.5 V
69 — —
< 5.5 V
68.8 — —
< 5.5 V
64.8 — —
< 5.5 V
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors62
Page 63
Table 28. SDn ADC electrical specification1 (continued)
Symbol Parameter Conditions
Electrical characteristics
Value
Unit
Min Typ Max
SINAD
SINAD
DIFF333
SE150
CC Signal to Noise and
Distortion Ratio,
Single-ended Mode,
150Ksps output rate
CC Signal to Noise and
Distortion Ratio,
Single-ended Mode,
150Ksps output rate
Gain = 1
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 2
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 4
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 8
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 16
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 1
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 2
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
66 — — dBFS
< 5.5 V
66 — —
< 5.5 V
63 — —
< 5.5 V
62 — —
< 5.5 V
59 — —
< 5.5 V
66 — — dBFS
< 5.5 V
66 — —
< 5.5 V
Gain = 4
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
63 — —
Tj < 150 °C
Gain = 8
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
62 — —
Tj < 150 °C
Gain = 16
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
59 — —
Tj < 150 °C
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 63
Page 64
Electrical characteristics
Symbol Parameter Conditions
Table 28. SDn ADC electrical specification1 (continued)
Value
Unit
Min Typ Max
THD
THD
DIFF150
DIFF333
CC Total Harmonic
Distortion, Differential
Mode, 150Ksps
output rate
CC Total Harmonic
Distortion, Differential
Mode, 333Ksps
output rate
Gain = 1
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 2
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 4
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 8
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 16
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 1
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 2
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
65 — — dBFS
< 5.5 V
68 — —
< 5.5 V
74 — —
< 5.5 V
80 — —
< 5.5 V
80 — —
< 5.5 V
65 — — dBFS
< 5.5 V
68 — —
< 5.5 V
Gain = 4
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
74 — —
Tj < 150 °C
Gain = 8
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
80 — —
Tj < 150 °C
Gain = 16
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
80 — —
Tj < 150 °C
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors64
Page 65
Table 28. SDn ADC electrical specification1 (continued)
Symbol Parameter Conditions
Electrical characteristics
Value
Unit
Min Typ Max
THD
SE150
CC Total Harmonic
Distortion,
Single-ended Mode,
150Ksps output rate
Gain = 1
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
Tj < 150 °C
Gain = 2
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
< 5.5 V
68 — — dBFS
68 — —
Tj < 150 °C
Gain = 4
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
68 — —
Tj < 150 °C
Gain = 8
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
68 — —
Tj < 150 °C
Gain = 16
4.5 V < V
V
DD_HV_ADR_D
DD_HV_ADV_D
= V
DD_HV_ADV_D
< 5.5 V
68 — —
Tj < 150 °C
1
Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress
ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect
device reliability or cause permanent damage to the device.
2
For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and
the signal will only be ‘clipped’.
3
V
is the input voltage applied to the positive terminal of the SDADC.
INP
4
V
is the input voltage applied to the negative terminal of the SDADC.
INM
5
When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. The
gives an effective resolution of 15 bits.
6
Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.
7
Calibration of gain is possible when gain = 1.
Offset Calibration should be done with respect to 0.5*V
negative input=0.5*V
DD_HV_ADR_D
.
DD_HV_ADR_D
for differential mode and single ended mode with
Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0".
Both offset and Gain Calibration is guaranteed for ±5% variation of V
DD_HV_ADR_D
, ±10% variation of V
DD_HV_ADV_D
and ± 50 °C temperature variation.
8
Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred
offset error.
9
S/D ADC is functional in the range 3.6 V – 4.5 V, SNR p a rameter degrades by 3 dB. Degraded SNR value based on
simulation.
10
S/D ADC is functional in the range 3.0 V –4.5 V, SNR parameter degrades by 9 dB. Degraded SNR value ba sed on
simulation.
11
This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to
a value of 6 d B less.
12
Input impedance in differential mode ZIN(input impedance) = Z
DIFF
.
,
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 65
Page 66
Electrical characteristics
13
Impedance given at F
Z
DIFF(FADCD_M
14
Input impedance in single-ended mode ZIN = (2 * Z
15
Impedance given at F
Z
DIFF(FADCD_M
16
Vintcm is the common mode input reference voltage for the SDADC, and has a nominal value of (V
V
SS_HV_ADC
17
SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the
frequency range of f
f
ADCD_S
) = (16 MHz / F
) = (16 MHz / F
) / 2.
ADCD_M
is the output sample frequency. A proper external input filter should be used to remove any interfering signals
= 16 MHz. Impedance is inversely proportional to SDADC clock frequency.
ADCD_M
ADCD_M
= 16 MHz. Impedance is inversely proportional to SDADC clock frequency.
ADCD_M
ADCD_M
– f
ADCD_S
) * Z
) * Z
to f
, ZCM (F
DIFF
, ZCM (F
DIFF
ADCD_M
DIFF
+ f
ADCD_S
ADCD_M
) = (16MHz / F
* ZCM) / (Z
ADCD_M
) = (16MHz / F
, where f
DIFF
+ ZCM).
ADCD_M
ADCD_M
ADCD_M
) * ZCM.
) * ZCM.
is the input sampling frequency, and
DD_HV_ADC
in this frequency range.
18
The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB.
19
Propagation of the information from the pin to the register CDR[CDAT A] and flags SFR[DFEF], SFR[DFFF] is given by
the different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain
synchronizers. The time elapsed between data availability at pin and internal S/D module registers is given by the
below formula:
REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fPBRIDGEx_CLK
where fADCD_S is the frequency of the sampling clock, fADCD_M is the frequency of the modulator, and
fPBRIDGEx_CLK is the frequency of the peripheral bridge clock feeds to the ADC S/D module. The (~+1) symbol
refers to the number of clock cycles uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the
signal during clock domain crossing.
Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received
from the ADC S/D module.
20
This capacitance does not include pin capacitance, that can be considered together with external capacitance, before
sampling switch.
-
3.11 Temperature sensor
The following table describes the temperature sensor electrical characteristics.
Table 29. Temperature sensor electrical characteristics
Value
Symbol Parameter Conditions
Min Typ Max
— CC Temperature monitoring range — –40 — 150 °C
T
SENS
T
ACC
I
TEMP_SENS
CC Sensitivity — — 5.18 — mV/°C
CC Accuracy TJ 150 °C –3 — 3 °C
CC V
DD_HV_ADV_S
power supply
———700µA
current
Unit
3.12 LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical characteristics
The LF AST pad electrical characteristics apply to both the SIPI and high-speed debug serial interfaces on the device. The same
LVDS pad is used for the Microsecond Channel (MSC) and DSPI LVDS interfaces, with different characteristics given in the
following tables.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors66
Page 67
3.12.1 LFAST interface timing diagrams
Signal excursions above this level NOT allowed
Max. common mode input at RX
Signal excursions below this level NOT allowed
Min. common mode input at RX
Data Bit Period
Minimum Data Bit Time
Opening =
0.55 * T (LFAST)
0.50 * T (MSC/DSPI)
Max Differential Voltage =
285 mV p-p (LFAST)
400 mV p-p (MSC/DSPI)
Min Differential Voltage =
100 mV p-p (LFAST)
150 mV p-p (MSC/DSPI)
1743 mV
1600 mV
V
OS
= 1.2 V +/- 10%
TX common mode
V
ICOM
150 mV
0V
1743 mV
“No-Go” Area
T = 1 /F
DATA
VOD
VOD
PER
EYE
PER
EYE
Electrical characteristics
Figure 16. LFAST and MSC/DSPI LVDS timing definition
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 67
Page 68
Electrical characteristics
Data Valid
pad_p/pad_n
lfast_pwr_down
Differential TX
Data Lines
H
L
t
PD2NM_TX
Differential TX
Data Lines
pad_p/pad_n
t
TR
t
TR
90%
10%
V
IH
V
IL
Figure 17. Power-down exit time
3.12.2 LFAST and MSC/DSPI LVDS interface electrical characteristics
The following table contains the electrical characteristics for the LFAST interface.
t
t
Figure 18. Rise/fall time
Table 30. LVDS pad startup and receiver electrical characteristics
Symbol Parameter Conditions
3,4
STRT_BIAS
PD2NM_TX
CC Bias current reference startup time
CC Transmitter startup time (power
down to normal mode)
6
MPC5777M Microcontroller Data Sheet, Rev. 6
STARTUP
5
1,2
Value
Unit
Min Typ Max
— — 0.5 4 µs
——0.42.75µs
NXP Semiconductors68
Page 69
Electrical characteristics
Table 30. LVDS pad startup and receiver electrical characteristics
1,2
(continued)
Value
Symbol Parameter Conditions
Min Typ Max
t
SM2NM_TX
t
PD2NM_RX
t
PD2SM_RX
I
LVDS_BIAS
CC Transmitter startup time (sleep mode
to normal mode)
CC Receiver startup time (power down
to normal mode)
CC Receiver startup time (power down
to sleep mode)
7
8
9
Not applicable to the
MSC/DSPI LVDS pad
— — 20 40 ns
Not applicable to the
MSC/DSPI LVDS pad
—0.20.5µs
—2050ns
CC LVDS bias current consumption Tx or Rx enabled — — 0.95 mA
TRANSMISSION LINE CHARACTERISTICS (PCB Track)
Z
SR Transmission line characteristic
0
— 47.55052.5
impedance
Z
DIFF
SR Transmission line differential
— 95 100 105
impedance
RECEIVER
V
ICOM
|
V
HYS
R
C
I
LVDS_RX
1
The LVDS p ad startup and receiver electrical characteristics in this table apply to both the LFAST & High-speed De-
SR Common mode voltage — 0.15
| SR Differential input voltage
VI
12
— 100 — — mV
CC Input hysteresis — 25 — — mV
CC Terminating resistance 3.0 V–5.5 V 80 125 150
IN
CC Differential input capacitance
IN
13
— — 3.5 6.0 pF
CC Receiver DC current consumption Enabled — — 0.5 mA
10
—1.611V
bug (HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the conditions.
2
All LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3
All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in
the LVDS control registers (LCR) of the LF AST and High-Speed Debug modules. The value of the LCR bits for the
LFAST/HSD modules don’t take effect until the corresponding SIUL2 MSCR ODC bits are set to LFAST L VDS mode.
Startup times for MSC/DSPI LVDS are defined after 2 peripheral bridge clock delay after selecting MSC/DSPI L VDS
in the corresponding SIUL2 MSCR ODC field.
4
Startup times are valid for the maximum external loads CL defined in both the LF AST/HSD and MSC/DSPI transmitter electrical characteristic tables.
5
Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after
being enabled.
6
T otal transmitter startup time from power down to normal mode is t
STRT_BIAS
+ t
PD2NM_TX
+ 2 peripheral bridge clock
periods.
7
T otal transmitter st artup time from sleep mode to normal mode is t
SM2NM_TX
+ 2 peripheral bridge clock periods. Bias
block remains enabled in sleep mode.
8
Total receiver startup time from power down to normal mode is t
STRT_BIAS
+ t
PD2NM_RX
+ 2 peripheral bridge clock
periods.
9
Total receiver startup time from power down to sleep mode is t
PD2SM_RX
+ 2 peripheral bridge clock periods. Bias
block remains enabled in sleep mode.
10
Absolute min = 0.15 V – (285 mV/2) = 0 V
11
Absolute max = 1.6 V + (285 mV/2) = 1.743 V
Unit
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 69
Page 70
Electrical characteristics
12
The LXRXOP[0] bit in the LFAST L VDS Control Register (LCR) must be set to one to ensure proper LFAST receive
timing.
13
Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.
Table 31. LFAST transmitter electrical characteristics
1,2
Value
Symbol Parameter Conditions
Min Typ Max
f
DATA
V
OS
|
VOD
t
TR
C
I
LVDS_TX
1
The LFAST and High-S peed Debug LFAST pad electrical characteristics are based on worst case internal capacitance
SR Data rate — — — 312/3203Mbps
CC Common mode voltage — 1.08 — 1.32 V
| CC Differential output voltage swing
(terminated)
4,5
CC Rise/Fall time (absolute value of the
differential output voltage swing)
SR External lumped differential load
L
capacitance
3
4,5
V
V
— 110 171 285 mV
—0.26—1.5ns
DD_HV_IO
DD_HV_IO
= 4.5 V — — 10.0 pF
= 3.0 V — — 8.5
CC Transmitter DC current consumption Enabled — — 3.2 mA
values shown in Figure 19.
2
All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3
The 312 Mbps data rate is achieved with a 26 MHz reference clock, and 320 Mbps is achieved with a 10 or 20 MHz
reference clock.
4
Va lid for maximum data r ate f
. V alue given is the capacitance on each terminal of the differential pair , as shown in
DATA
Figure 19.
5
Valid for maximum external load CL.
Unit
Table 32. MSC/DSPI LVDS transmitter electrical characteristics
1,2
Value
Symbol Parameter Conditions
Min Typ Max
Data Rate
f
DATA
V
|
VOD
t
TR
C
I
LVDS_TX
1
The MSC and DSPI LVDS p ad electrical characteristics are based on the application circuit and typical worst case
SR Data rate — — — 80 Mbps
CC Common mode voltage — 1.08 — 1.32 V
OS
| CC Differential output voltage swing
(terminated)
3,4
CC Rise/Fall time (absolute value of the
differential output voltage swing)
SR External lumped differential load
L
capacitance
3
3,4
V
V
— 150 214 400 mV
— 0.8 — 4.0 ns
DD_HV_IO
DD_HV_IO
= 4.5 V — — 50 pF
= 3.0 V — — 39
CC Transmitter DC current consumption Enabled — — 4.0 mA
internal capacitance values given in Figure 19.
2
All MSC and DSPI LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
Unit
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors70
Page 71
3
Va lid for maximum data rate f
DATA
in Figure 19.
4
Valid for maximum external load CL.
*3,2'ULYHU
/9'6'ULYHU
Electrical characteristics
. Value given is the capacitance on each terminal of the differential pair , as shown
ERQGSDG
&
/
S)
S)
ȍ
WHUPLQDWRU
ERQGSDG
*3,2'ULYHU
S)
S)
'LH 3DFNDJH 3&%
Figure 19. LVDS pad external load diagram
3.12.3 LFAST PLL electrical characteristics
The following table contains the electrical characteristics for the LFAST PLL.
Table 33. LFAST PLL electrical characteristics
Symbol Parameter Conditions
f
RF_REF
ERR
DC
PN CC Integrated phase noise (single side band) f
SR PLL reference clock frequency — 10 — 26 MHz
CC PLL input reference clock frequency error — –1 — 1 %
REF
CC PLL input reference clock duty cycle — 45 — 55 %
REF
= 20 MHz — — –58 dBc
RF_REF
f
= 10 MHz — — –64
RF_REF
&
/
1
Value
Min Nominal Max
Unit
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 71
Page 72
Electrical characteristics
Table 33. LFAST PLL electrical characteristics1 (continued)
Value
Symbol Parameter Conditions
Min Nominal Max
f
VCO
t
LOCK
PER
PER
1
The specifications in this table apply to both the interprocessor bus and debug LFAST interfaces.
2
The 640 MHz frequency is achie v ed with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO
CC PLL VCO frequency — — 640
CC PLL phase lock
SR Input reference clock jitter (peak to peak) Single period,
REF
CC Output Eye Jitter (peak to peak)
EYE
3
f
RF_REF
Long term,
f
RF_REF
4
———40µs
=10MHz
–500 — 500 ps
=10MHz
———400ps
——300ps
frequency is 624 MHz.
3
The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device.
4
Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. See
Figure 19.
2
Unit
—MHz
3.13 Aurora LVDS electrical characteristics
The following table describes the Aurora LVDS electrical characteristics.
NOTE
The Aurora interface is AC coupled, so there is no common-mode voltage specification.
Table 34. Aurora LVDS electrical characteristics
Symbol Parameter Conditions
Transmitter
CC Transmit Data Rate — — — 1.25 Gbps
CC Differential output voltage swing
(terminated)
3
CC Rise/Fall time (10%–90% of swing) — 60 — — ps
SR Differential Terminating resistance — 81 100 120
CC Transmission Line Loss due to loading
effects
Transmission line characteristics (PCB track)
SR Transmission line length — — — 20 cm
SR Transmission line characteristic impedance — 45 50 55
SR Clock Receive Pin External AC Coupling
Capacitance
Values are nominal, valid
for +/– 50% tolerance
V
OD_LVDS
t
TR_LVDS
R
V_L_Tx
T
L
Z
C
F
TX
Loss
LINE
LINE
ac_clk
1,2
Value
Unit
Min Typ Max
— ±400 ±600 ±800 mV
———6
4
dB
100 — 270 pF
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors72
Page 73
Electrical characteristics
Table 34. Aurora LVDS electrical characteristics
1,2
(continued)
Value
Symbol Parameter Conditions
Min Typ Max
C
ac_tx
SR Transmit Lane External AC Coupling
Capacitance
Values are nominal, valid
for +/– 50% tolerance
250 — 2000 pF
Receiver
F
RX
V
I_L
R
V_L_Rx
1
All Aurora electrical characteristics are valid from –40 °C to 150 °C, except where noted.
2
All specifications valid for maximum transmit data rate FTX.
3
The minimum value of 400 mV is only valid for differential terminating resistance (R
differential output voltage swing tracks with the value of R
4
Transmission line loss maximum value is specified for the maximum drive level of the Aurora transmit pad.
CC Receive Clock Rate TJ= 150 °C — — 1.25 Gbps
SR Differential input voltage (peak to peak) — 200 — 1000 mV
CC Differential Terminating resistance — 81 100 120
) = 99 ohm to 101 ohm. The
V_L
V_L
.
Unit
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 73
Page 74
Electrical characteristics
C
HV_PMC
C
HV_FLA
VSS
VDD_HV_PMC
VDD_HV_FLA
MPC5777M
VDD_HV_IO
VSS
C
HV_IO
(2)
C
HV_ADC
VSS
VDD_LV
C
LV
(1)
VDD_HV_ADV
VSS_HV_ADV
(1) One capacitance near each V
DD_LV
pin
(2) One capacitance near each V
DD_HV
pin
3.14 Power management: PMC, POR/LVD, sequencing
3.14.1 Power management electrical characteristics
The power management module monitors the different power supplies. It also generates the internal supplies that are required
for correct device functionality. The power management is supplied by the V
DD_HV_PMC
3.14.2 Power management integration
In order to ensure correct functionality of the device, it is recommended to follow below integration scheme.
supply (see Table 8).
Figure 20. Recommended supply pin circuits
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors74
Page 75
Electrical characteristics
The following table describes the supply stability capacitances required on the device for proper operation.
Table 35. Device power supply integration
Symbol Parameter Conditions
Min Typ Max
Value
1
Unit
C
C
HV_IO
C
HV_FLA
C
HV_PMC
LV
SR Minimum VDD_LV external
capacitance
2
Bulk capacitance External regulator
Total bypass
capacitance at
external pin
3
bandwidth > 20 KHz
SR Mini mum VDD_HV_IO external capacitance — 4.7 — — µF
SR Mini mum VDD_HV_FLA external capacitance
SR Minimum V
DD_HV_PMC
External Capacitance
4,5
6,7
512 BGA ba lls A29,
—0.751.5—µF
10 — — µF
Note3——
2.2 4.7 — µF
B28, F24, and G23
C
HV_ADC
1
See Figure 20 for capacitor integration.
2
Recommended X7R or X5R ceramic low ESR capacitors, ±15% variation over voltage, temperature, and aging.
3
Each VDD_LV pin requires both a 0.1µF and 0.01µF capacitor for high-frequency bypass and EMC requirements.
4
The recommended flash regulator composition capacitor is 1.5 µF typical X7R or X5R, with –50% and +35% as min and
SR Minimum V
DD_HV_ADV
external capacitance
8
1.5 3.3 — µF
max. This puts the min cap at 0.75 µF.
5
Start-up time of the internal flash regulator from release of the LVD360 is worst case 500 us. This is based on the typical
CHV_FLA bulk capacitance value.
6
For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between V
V
.
SS_HV
7
In the 512BGA package, V
DD_HV_PMC
B28, F24, G3, in addition to the normal V
8
For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between V
V
SS_HV_ADV
.
is shorted to V
DD_HV_IO_MAIN
DD_HV_IO_MAIN
. Use a local 200 nF capacitor on 512BGA balls A29,
bulk and local external capacitance.
DD_HV_PMC
DD_HV_ADV
and
and
3.14.3 3.3 V flash supply
Table 36. Flash power supply
Value
Symbol Parameter Conditions
Min Typ Max
V
DD_HV_FLA
1
CC Flash regulator DC output voltage Before trimming 3.1
After trimming
2
3.3 3.5 V
3.15 3.3 3.4
–40°C TJ 25°C
After trimming
25°C T
1
Min value accounts for all static and dynamic variations of the regulator (min cap as 0,75uF).
2
Min value of 3.1 V for VDD_HV_REG at 3.15V assumes that the auxiliary regulator on VDD_LV does not actively provide
150°C
J
3.10 3.3 3.4
any current to the chip. If the auxiliary regulator actively provides current, the min value may go lower than 3.1 V drop to
IR drop caused by auxiliary current demanding on VDD_HV_REG supply.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 75
Unit
Page 76
Electrical characteristics
V
DD_xxx
V
LVD(fall)
HVD TRIGGER
t
VDRELEASE
V
LVD(rise)
t
VDASSERT
V
HVD(fall)
V
HVD(rise)
LVD TRIGGER
t
VDRELEASE
t
VDASSERT
(INTERNAL)
(INTERNAL)
3.14.4 Device voltage monitoring
The LVD/HVDs and their associated levels for the device are given in the following table. The figure below illustrates the
workings of voltage monitoring threshold.
Figure 21. Voltage monitor threshold definition
Table 37. Voltage monitor electrical characteristics
Symbol Parameter Conditions
2
V
PORUP_LV
V
LVD096
V
LVD108
V
LVD112
CC LV supply power on reset threshold Rising voltage (power up) 1111 — 1235 mV
Falling voltage (power down)
Hysteresis on power-up 50 — —
CC LV internal4 supply low voltage
See note
5
monitoring
CC Core LV internal4 supply low voltage
See note
6
monitoring
CC LV external7 supply low voltage
See note
5
monitoring
MPC5777M Microcontroller Data Sheet, Rev. 6
1
Value
Min Typ Max
3
1015 — 1125
1015 — 1145 mV
1 150 — 1220 mV
1 175 — 1235 mV
NXP Semiconductors76
Unit
Page 77
Table 37. Voltage monitor electrical characteristics1 (continued)
Symbol Parameter Conditions
V
HVD140
CC LV external10 supply high voltage
monitoring
See note
8
Electrical characteristics
Value
Unit
Min Typ Max
1385 — 1475 mV
V
HVD145
V
PORUP_HV
V
POR240
V
LVD270
V
LVD295
V
HVD360
V
LVD360
CC LV externa10 supply high voltage
— 1430 — 1510 mV
reset threshold
2
CC HV supply power on reset threshold9Rising voltage (power up) on
4040 — 448010mV
PMC/IO Main supply
Rising voltage (power up) on
2730 — 3030
IO JTAG and Osc supply
Rising voltage (power up) on
2870 — 3182
ADC supply
12
11
2850 — 3162
878 — 1630
CC HV supply power-on reset voltage
monitoring
Falling voltage (power down)
Hysteresis on power up
Rising voltage 2420 — 2780 mV
Falling voltage 2400 — 2760
CC HV supply low voltage monitoring Rising voltage 2750 — 3000 mV
Falling voltage 2700 — 2950
CC Flash supply low voltage
monitoring
13
Rising voltage — — 3120 mV
Falling voltage 2920 — 3100
CC Flash supply high voltage monitoring Rising voltage 3435 — 3650 mV
Falling voltage 3415 — —
CC HV supply low voltage monitoring Rising voltage — — 4000 mV
Falling voltage 3600 — 3880
V
LVD400
CC HV supply low voltage monitoring Rising voltage 4110 — 4410 mV
Falling voltage 3970 — 4270
V
HVD600
CC HV supply high voltage monitoring Rising voltage 5560 — 5960 mV
Falling voltage 5500 — 5900
t
VDASSERT
CC Voltage detector threshold crossing
—0.1—2µs
assertion
t
VDRELEASE
CC Voltage detector threshold crossing
—5—20µs
de-assertion
1
For V
levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR
DD_LV
drop is estimated by multiplying the supply current by 0.5 .
2
V
PORUP_LV
and V
PORUP_HV
threshold are untrimmed values before completion of the power-up sequence. All other
LVD/HVD thresholds are provided afte r tr i mmi ng .
3
Assume all of LVDs on LV supplies disabled.
4
LV internal supply levels are measured on device internal supply grid after internal voltage drop.
5
LVD is released after t
VDRELEASE
temporization when upper threshold is crossed, LVD is asserted t
VDASSERT
after
detection when lower threshold is crossed.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 77
Page 78
Electrical characteristics
6
This specification is driven by LVD108_C. There are additional LVDs on PLL and Flash VDD_LV supply nets which will
assert at voltage below LVD108_C.
7
LV external supply levels are measured on the die side of the package bond wire after package voltage drop. This is
monitoring external regulator supply voltage and board voltage drop. This does not guarantee device is working down
to minimum threshold. For minimum supply, refer to operating condition table.
8
HVD is released after t
VDRELEASE
temporization when lower threshold is crossed, HVD is asserted t
VDASSERT
detection when upper threshold is crossed. HVD140 does not cause reset.
9
This supply also needs to be below 5472 mV (untrimmed HVD600 min)
10
The PMC supply also needs to be below 5472 mV (untrimmed HVD600 mV).
11
Untrimmed LVD300_A will be asserted first on power down.
12
Hysteresis is implemented only between the VDD_HV_IO_MAIN High voltage Supplies and the ADC high voltage
supply. When these two supplies are shorted together, the hysteresis is as is shown in Table 37. If the supplies are not
shorted (VDD_IO_MAIN and ADC high voltage supply), then there will be no hysteresis on the high voltage supplies.
13
V
DD_HV_FLA
supply range is guaranteed by internal regulator.
3.14.5 Power up/down sequencing
Table 38 shows the constraints and relationships for the different power supplies
Table 38. Device supply relation during power-up/power-down sequence
after
Supply 2
V
DD_LVVDD_HV_PMCVDD_HV_IOVDD_HV_FLAVDD_HV_ADVVDD_HV_ADR
V
DD_LV
V
DD_HV_PMU
V
DD_HV_IO
1
V
DD_HV_FLA
V
DD_HV_ADV
Supply 1
V
DD_HV_ADR
ALTREFn 10 mA
V
DDSTBY
1
Red cells: supply1 (row) can exceed supply2 (column), granted that external circuitry ensure current flowing from supply1
2mA
3
4
1
5mA
10 mA
ALTREFn
4
2
V
is less than absolute maximum rating current value provided.
2
AL TREFn are the alternate references for the ADC that can be used in place of the default reference (V
DD_HV_ADR_*
are SARB.ALTREF and SAR2.ALTREF.
3
V
DD_HV_FLA
4
ADC performances is not guaranteed with ALTREFn above V
is generated internally in normal mode. Above current constraints is guaranteed.
DD_HV_IO/VDD_HV_ADV
During power-up, all functional terminals are maintained into a known state as described within the following table.
DDSTBY
). They
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors78
Page 79
Table 39. Functional terminals state during power-up and reset
Electrical characteristics
TERMINAL
TYPE
1
POWERUP
pad st ate
PORST Strong
pull-down
ESR0
5
Strong
2
4
RESET
pad state
DEFAULT
pad st ate
3
Weak pull-down Weak pull-down Power-on reset pad
Strong pull-down Weak pull-up Functional reset pad.
Comments
pull-down
ESR1 High impedance Weak pull-up Weak pull-up —
TESTMODE Weak pull-down Weak pull-down
GPIO Weak pull-up
4
Weak pull-up Weak pull-up
6
Weak pull-down
ANALOG High impedance High impedance High impedance
6
—
—
—
ERROR0 High impedance High impedance High impedance During functional reset, pad state
can be overridden by FCCU
JCOMP High impedance Weak pull-down Weak pull-down
—
TCK High impedance Weak pull-down Weak pull-down —
TMS High impedance Weak pull-up Weak pull-up —
TDI High impedance Weak pull-up Weak pull-up —
TDO High impedance Weak pull-up High impedance —
1
Refer to pinout information for terminal type
2
POWERUP state is guaranteed from V
threshold: V
3
Before software configuration
4
Pull-down and pull-up strength are provided as part of Table 13 in Section 3.6.1, I/O input DC characteristics.
PORUP_LV
for LV supply, V
DD_HV_IO
PORUP_HV
>1.1 V an d maintained until supply cross the power-on reset
for high voltage supply.
Pull-up/Pull-down are activated within 2 µs after internal reset has been asserted. Actual pad transition will depend
on external capacitance.
5
Unlike ESR0, ESR1 is provided as normal GPIO and implements weak pull-up during power-up.
6
An internal pull-down is implemented on the TESTMODE pin to prevent the device from entering test mode if the
package TESTMODE pin is not connected. It is recommended to connect the TESTMODE pin to V
board for maximum robustness, but not required. The value of TESTMODE is latched at the negation of reset and
has no affect afterward. The device will not exit functional reset with the TESTMODE pin asserted during power-up.
The TESTMODE pin can be connected externally directly to ground without any other components.
3.15 Flash memory electrical characteristics
The following sections contain flash memory electrical specifications.
3.15.1 Flash memory program and erase specifications
NOTE
All timing, voltage, and current numbers specified in this section are defined for a single
embedded flash memory within an SoC, and represent average currents for given supplies
and operations.
SS_HV_IO
on the
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 79
Page 80
Electrical characteristics
Table 40 shows the estimated Program/Erase times.
Table 40. Flash memory program and erase specifications (pending characterization)
Factory
Programming
Symbol Characteristic
1
Typ
2
20°C T
a
30°C
t
dwpgm
t
t
t
16kers
t
16kpgn
t
32kers
t
32kpgm
t
64kers
t
64kpgm
t
256kers
t
256kpgm
1
Doubleword (64 bits) program time 43 100 150 55 500 µs
Page (256 bits) program time 73 200 300 108 500 µs
ppgm
Quad-page (1024 bits) program time 268 800 1,200 396 2,000 µs
qppgn
16 KB Block erase time 168 290 320 250 1,0 00 ms
16 KB Block program time 34 45 50 40 1,000 ms
32 KB Block erase time 217 360 390 310 1,2 00 ms
32 KB Block program time 69 100 110 90 1.200 ms
64 KB Block erase time 315 490 590 420 1,6 00 ms
64 KB Block program time 138 180 210 170 1,600 ms
256 KB Block erase time 884 1,520 2,030 1,080 4,000 — ms
256 KB Block program time 552 720 880 650 4,000 — ms
Program times are actual hardware programming times and do not include software overhead. Block program times assume
3,4
Initial Max
Full Temp
-40°C T
150°C
-40°C T
J
Typical
End of
Life
150 °C
Field Update
5
1,000
J
cycles
Lifetime Max
250,000
cycles
6
UnitsInitial Max
quad-page programming.
2
Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
3
Conditions: 150 cycles, nominal voltage.
4
Plant Programming times provide guidance for timeout limits used in the factory.
5
Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical
End of Life program and erase values may be used for throughput calculations.
6
Conditions: -40°C TJ 150°C; full spec voltage.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors80
Page 81
Electrical characteristics
3.15.2 Flash memory FERS program and erase specifications
Table 41. Flash memory FERS program and erase specifications (pending characterization)
Factory Programming with FERS=1 and Vfers
pin is
30°C
A
2
Initial Max
Full Temp
4
-40°CTJ150°C
Units
4
5V ± 5%
Symbol Characteristic
1
Initial Max
Typ
3
20°CT
t
dwpgm
t
ppgm
t
qppgn
t
16kers
t
16kpgn
t
32kers
t
32kpgm
t
64kers
t
64kpgm
t
256kers
t
256kpgm
1
Program times are actual hardware programming times and do not include software overhead. Block program times assume
Doubleword (64 bits) program time 30 90 135 µs
Page (256 bits) program time 43 145 218 µs
Quad-page (1024 bits) program time 134 530 795 µs
16 KB erase time 160 782 782 ms
16 KB program time 18 24 35 ms
32 KB erase time 190 782 782 ms
32 KB program time 36 47 68 ms
64 KB erase time 250 782 782 ms
64 KB program time 72 94 135 ms
256 KB erase time 600 1,380 2,070 ms
256 KB program time 288 374 568 ms
quad-page programming.
2
Conditions: 150 cycles, nominal voltage.
3
Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.
4
Plant Programming times provide guidance for timeout limits used in the factory.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 81
Page 82
Electrical characteristics
3.15.3 Flash memory Array Integrity and Margin Read specifications
Table 42. Flash memory Array Integrity and Margin Read specifications (characterized but not tested)
Symbol Characteristic Min Typical Max
t
ai16kseq
Array Integrity time for sequential sequence on 16KB block. — — 512 ×
1
Units
Tperiod ×
Nread
t
ai32kseq
Array Integrity time for sequential sequence on 32KB block. — — 1024 ×
Tperiod ×
Nread
t
ai64kseq
Array Integrity time for sequential sequence on 64KB block. — — 2048 ×
Tperiod ×
Nread
t
ai256kseq
Array Integrity time for sequential sequence on 256KB block. — — 8192 ×
Tperiod ×
Nread
t
aifullseq
Array Integrity time for sequential sequence full array. — — 3.77e5 ×
Tperiod ×
Nread
t
aifullprop
Array Integrity time for proprietary sequence (applies to full
array or single block).
— — 9.96e6 ×
Tperiod ×
Nread
t
mr16kseq
t
mr32kseq
t
mr64kseq
t
mr256kseq
t
mrfull
1
Array Integrity times need to be calculated and are dependent on system frequency and number of clocks per read.
Margin Read time for sequential sequence on 16KB block. 73.81 — 110.7 µs
Margin Read time for sequential sequence on 32KB block. 128.43 — 192.6 µs
Margin Read time for sequential sequence on 64KB block. 237.65 — 356.5 µs
Margin Read time for sequential sequence on 256KB block. 893.01 — 1,339.5 µs
Margin Read time for sequential sequence full array. 45.21 — 60.26 ms
The equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal
5e-9) and Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup
that requires 6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read,
and has the address pipeline set to 2, Nread would equal 4 (or 6 - 2).)
2
The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.
2
—
—
—
—
—
—
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors82
Page 83
Electrical characteristics
3.15.4 Flash memory module life specifications
Table 43. Flash memory module life spec (pending characterization)
Symbol Characteristic Conditions Min Typical Units
Array P/E
cycles
Data
retention
Number of program/erase cycles per
block for 16 KB, 32 KB and 64 KB
1
blocks.
Number of program/erase cycles per
block for 256 KB blocks.
2
— 250,000 — P/E
— 1,000 250,000 P/E
Minimum data retention. Blocks with 0 – 1,000 P/E
cycles.
Blocks with 100,000 P/E
cycles
cycles
50 — Years
20 — Years
cycles.
Blocks with 250,000 P/E
10 — Years
cycles.
1
Program and erase supported across standard temperature specs.
2
Program and erase supported across standard temperature specs.
3.15.5 Data retention vs program/erase cycles
Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window
represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the
qualification limits.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 83
Page 84
Electrical characteristics
3.15.6 Flash memo ry AC timing specifications
Table 44. Flash memory AC timing specifications (characterized but not tested)
Symbol Characteristic Min Typical Max Units
t
psus
t
esus
t
res
t
done
t
dones
t
drcv
t
aistart
Time from setting the MCR-PSUS bit until MCR-DONE bit
— 7 plus four
is set to a 1.
Time from setting the MCR-ESUS bit until MCR-DONE bit
— 16 plus
is set to a 1.
Time from clearing the MCR-ESUS or PSUS bit with
——100ns
EHV = 1 until DONE goes low.
Time from 0 to 1 transition on the MCR-EHV bit initiating a
—— 5ns
program/erase until the MCR-DONE bit is cleared.
Time from 1 to 0 transition on the MCR-EHV bit aborting a
— 16 plus
program/erase until the MCR-DONE bit is set to a 1.
Time to recover once exiting low power mode. 16 plus
seven
system
clock
periods
Time from 0 to 1 transition of UT0-AIE initiating a Margin
—— 5ns
Read or Array Integrity until the UT0-AID bit is cleared.
This time also applies to the resuming from a suspend or
breakpoint by clearing AISUS or clearing NAIBP
9.1 plus
system
clock
system
periods
periods
20.8 plus
four
system
system
clock
periods
periods
20.8 plus
four
system
system
clock
periods
periods
— 45 plus
seven
system
periods
µs
four
clock
µs
four
clock
µs
four
clock
µs
clock
t
aistop
Time from 1 to 0 transition of UTO-AIE initiating an Array
Integrity abort until the UT0-AID bit is set. This time also
applies to the UT0-AISUS to UT0-AID setting in the event
of a Array Integrity suspend request.
—— 80
plus fifteen
system
clock
ns
periods
t
mrstop
Time from 1 to 0 transition of UTO-AIE initiating a Margin
Read abort until the UT0-AID bit is set. This time also
applies to the UT0-AISUS to UT0-AID setting in the event
of a Margin Read suspend request.
10.36
plus four
system
clock
periods
— 20.42
plus four
system
clock
periods
µs
3.15.7 Flash read wait state and address pipeline control settings
Table 45 describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic
flash access times of the C55FMC array at 150 °C.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors84
Page 85
Table 45. Flash Read Wait State and Address Pipeline Control Combinations
Flash Frequency RWSC setting APC setting
0 MHz < fFLASH 33 MHz 0 0
33 MHz < fFLASH 100 MHz 2 1
100 MHz < fFLASH 133 MHz 3 1
133 MHz < fFLASH 167 MHz 4 1
167 MHz < fFLASH 200 MHz 5 2
3.16 AC specifications
All AC timing specifications are valid up to 150 °C, except where explicitly noted.
3.16.1 Debug and calibration interface timing
3.16.1.1 JTAG interface timing
Table 46. JTAG pin AC electrical characteristics
Electrical characteristics
1,2
# Symbol Characteristic
Min Max
1t
2t
3t
4t
5t
6t
7t
8t
9t
10 t
11 t
12 t
13 t
14 t
15 t
1
2
JCYC
JDC
TCKRISE
TMSS, tTDIS
TMSH, tTDIH
TDOV
TDOI
TDOHZ
JCMPPW
JCMPS
BSDV
BSDVZ
BSDHZ
BSDST
BSDHT
These specifications apply to JTAG boundary scan only. See Table 47 for functional specifications.
JT AG timing specified at V
CC TCK cycle time 100 — ns
CC TCK clock pulse width 40 60 %
CC TCK rise and fall times (40%–70%) — 3 ns
CC TMS, TDI data setup time 5 — ns
CC TMS, TDI data hold time 5 — ns
CC TCK low to TDO data valid — 16
CC TCK low to TDO data invalid 0 — ns
CC TCK low to TDO high impedance — 15 ns
CC JCOMP assertion time 100 — ns
CC JCOMP setup time to TCK low 40 — ns
CC TCK falling edge to output valid — 600
CC TCK falling edge to output valid out of high impedance — 600 ns
CC TCK falling edge to output high impedance — 600 ns
CC Boundary scan input valid to TCK rising edge 15 — ns
CC TCK rising edge to boundary scan input invalid 15 — ns
DD_HV_IO_JTAG
= 4.0 V to 5.5 V, and maximum loading per pad type as specified in the
I/O section of the data sheet.
3
Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
Value
Unit
3
ns
4
ns
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 85
Page 86
Electrical characteristics
TCK
1
2
2
3
3
TCK
4
5
6
7
8
TMS, TDI
TDO
4
Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG
delay.
Figure 22. JTAG test clock input timing
Figure 23. JTAG test access port timing
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors86
Page 87
Figure 24. JTAG JCOMP timing
TCK
JCOMP
9
10
Electrical characteristics
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 87
Page 88
Electrical characteristics
TCK
Output
Signals
Input
Signals
Output
Signals
11
12
13
14
15
Figure 25. JTAG boundary scan timing
3.16.1.2 Nexus interface timing
Table 47. Nexus debug port timing
# Symbol Characteristic
7t
EVTIPW
8t
EVTOPW
9t
TCYC
9t
TCYC
CC EVTI pulse width 4 — t
CC EVTO pulse width 40 — ns
CC TCK cycle time 2
CC Absolute minimum TCK cycle time5 (TDO/TDOC sampled on posedge of
TCK)
Absolute minimum TCK cycle time
TCK)
8
11
t
NTDIS
CC TDI/TDIC data setup time 5 — ns
MPC5777M Microcontroller Data Sheet, Rev. 6
1
7
(TDO/TDOC sampled on negedge of
Value
Min Max
3,4
—t
6
40
20
—ns
6
—
NXP Semiconductors88
Unit
CYC
CYC
2
2
Page 89
Table 47. Nexus debug port timing1 (continued)
TCK
9
EVTI
EVTO
# Symbol Characteristic
Electrical characteristics
Value
Unit
Min Max
12 t
NTDIH
9
13
t
NTMSS
14 t
NTMSH
10
15
16 — C C TDO/TDOC hold time with respect to TCK falling edge (minimum
CC TDI/TDIC data hold time 5 — ns
CC TMS/TMSC data setup time 5 — ns
CC TMS/TMSC data hold time 5 — ns
— CC TDO/TDOC propagation delay from falling edge of TCK
11
—16ns
2.25 — ns
TDO/TDOC propagation delay)
1
Nexus timing specified at V
DD_HV_IO_JTAG
= 4.0 V to 5.5 V, and maximum loading per pad type as specified in the
I/O section of the data sheet.
2
t
is system clock period.
CYC
3
Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is
less than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral
frequency being used. T o ensure proper operation TCK frequency should be set to the peripheral frequency divided
by a number greater than or equal to that specified here.
4
This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the
Absolute minimum TCK period specification.
5
This value is TDO/TDOC propagation time 36ns + 4 ns setup time to sampling edge.
6
This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability
of the design (system frequency / 4) depending on the actual system frequency being used.
7
This value is TDO/TDOC propagation time 16ns + 4 ns setup time to sampling edge.
8
TDIC represents the TDI bit frame of the scan packet in compact JTAG 2-wire mode.
9
TMSC represents the TMS bit frame of the scan packet in compact JTAG 2-wire mode.
10
TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.
11
Timing includes TCK pad delay, clock tree delay, logic delay and TDO/TDOC output pad delay.
Figure 26. Nexus event trigger and test clock timings
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 89
Page 90
Electrical characteristics
TCK
11
12
15
TMS/TMSC,
TDO/TDOC
13
14
16
TDI/TDIC
Figure 27. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing
3.16.1.3 Aurora LVDS interface timing
Table 48. Aurora LVDS interface timing specifications
Symbol Parameter
— SR Data rate — — 1250 Mbps
t
STRT_BIAS
t
STRT_TX
t
STRT_RX
1
Startup time is defined as the time taken by L VDS current reference block for settling bias current after its pwr_down
CC Bias startup time
CC Transmitter startup time
CC Receiver startup time
1
2
3
(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.
2
Startup time is defined as the time taken by L VDS transmitter for settling after it s pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality
is guaranteed only after the startup time.
MPC5777M Microcontroller Data Sheet, Rev. 6
Data Rate
STARTUP
Value
Unit
Min Typ Max
—— 5µs
—— 5µs
—— 4µs
NXP Semiconductors90
Page 91
3
Startup time is defined as the time taken by L VDS receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality
is guaranteed only after the startup time.
3.16.1.4 Aurora debug port timing
Table 49. Aurora debug port timing
# Symbol Characteristic
Electrical characteristics
Value
Unit
Min Max
1t
1a t
2t
3J
4t
REFCLK
MCYC
RCDC
RC
STABILITY
CC Reference clock frequency 625 1250 MHz
CC Reference clock rise/fall time — 400 ps
CC Reference clock duty cycle 45 55 %
CC Reference clock jitter — 40 ps
CC Reference clock stability 50 — PPM
5 BER CC Bit error rate — 10
6J
7J
8S
9S
D
T
O
MO
10 OUI CC Aurora lane unit interval
SR Transmit lane deterministic jitter — 0.17 OUI
SR Transmit lane total jitter — 0.35 OUI
CC Differential output skew — 20 ps
CC Lane to lane output skew — 1000 ps
1
625 Mbps 1600 1600 ps
1.25 Gbps 800 800
1
± 100 PPM
–12
—
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 91
Page 92
Electrical characteristics
Tx Data [m]
Zero Crossover
CLOCK
REF
-
CLOCK
REF
+
2
Zero Crossover
1a 1a1a1a
2
1
Tx Data
-
Tx Data
+
Ideal Zero Crossover
Tx Data [n]
Zero Crossover
Tx Data [n+1]
Zero Crossover
99
88 8
Figure 28. Aurora timings
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors92
Page 93
Electrical characteristics
3.16.2 DSPI timing with CMOS and LVDS1 pads
DSPI channel frequency support is shown in Table 50. Timing specifications are shown in Table 51, Table 52, Table 54,
Table 55 and Table 56.
Table 50. DSPI channel frequency support
DSPI use mode
Max usable
frequency (MHz)
1,2
CMOS (Master mode) Full duplex – Classic timing (Table 51)17
Full duplex – Modified timing ( Table 52)30
Output only mode (SCK/SOUT/PCS) (Table 51 and Table 52)30
Output only mode TSB mode (SCK/SOUT/PCS) (Table 56)30
3
L VDS (Master mode)
Full duplex – Modified timing ( Table 54)33
Output only mode TSB mode (SCK/SOUT/PCS) (Table 55)40
1
Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
2
Maximum usable frequency does not take into account external device propagation delay.
3
µS Channel and LVDS timing is not supported for DSPI12.
3.16.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads
3.16.2.1.1 DSPI CMOS Master Mode – Classic Timing
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1
2
# Symbol Characteristic
Pad drive
Condition Value
3
Load (CL)Min Max
1
Unit
1t
CC SCK cycle time SCK drive strength
SCK
Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —
2t
CC PCS to SCK delay SCK and PCS drive strength
CSC
Very strong 25 pF (N4 × t
Strong 50 pF (N4 × t
Medium 50 pF (N4 × t
PCS medium
and SCK strong
PCS = 50 pF
SCK = 50 pF
(N4 × t
5
)–16 —ns
SYS
5
)–16 —
SYS
5
)–16 —
SYS
5
)–29 —
SYS
1. DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 93
Page 94
Electrical characteristics
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11
# Symbol Characteristic
3t
4t
5t
PCSC
CC After SCK delay SCK and PCS drive strength
ASC
CC SCK duty cycle7SCK drive strength
SDC
CC PCSx to PCSS
time
8
Condition Value
3
Pad drive
Load (CL)Min Max
Very strong PCS = 0 pF
(M6 × t
5
)–35 —ns
SYS
2
Unit
SCK = 50 pF
Strong PCS = 0 pF
(M6 × t
5
)–35 —
SYS
SCK = 50 pF
Medium PCS = 0 pF
(M6 × t
5
)–35 —
SYS
SCK = 50 pF
PCS medium
and SCK strong
PCS = 0 pF
SCK = 50 pF
Very strong 0pF
Strong 0pF
Medium 0pF
(M6 × t
5
)–35 —
SYS
1
/2t
–2
SCK
1
/2t
–2
SCK
1
/2t
–5
SCK
1
/2t
+2 ns
SCK
1
/2t
+2
SCK
1
/2t
+5
SCK
PCS strobe timing
PCS and PCSS drive strength
Strong 25 pF 16.0 —ns
6t
PASC
7t
SUI
8t
HI
9t
SUO
CC PCSS to PCSx
CC SIN setup time to
CC SIN hold time from
CC SOUT data valid
8
time
9
SCK
9
SCK
time from SCK
10
PCS and PCSS drive strength
Strong 25 pF 16.0 —ns
SIN setup time
SCK drive strength
Very strong 25 pF 25.0 — ns
Strong 50 pF 32.75 —
Medium 50 pF 52.0 —
SIN hold time
SCK drive strength
Very strong 0pF –1.0 — ns
Strong 0pF –1.0 —
Medium 0pF –1.0 —
SOUT data valid time (after SCK edge)
SOUT and SCK drive strength
Very strong 25 pF — 7.0 ns
Strong 50 pF — 8.0
Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors94
Page 95
Electrical characteristics
Table 51. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 11
2
# Symbol Characteristic
10 t
CC SOUT data hold
HO
time after SCK
Condition Value
3
Pad drive
SOUT and SCK drive strength
10
Load (CL)Min Max
Very strong 25 pF –7.7 — ns
Strong 50 pF –11.0 —
Medium 50 pF –15.0 —
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2
All timing values for output signals in this table are measured to 50% of the output voltage.
3
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds
and may cause incorrect operation.
4
N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CT ARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless
TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS
and SCK are driven by the same edge of DSPI_CLKn).
5
t
is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
SYS
t
=10ns).
SYS
6
M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
7
t
is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
SDC
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8
PCSx and PCSS using same pad configuration.
9
Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10
SOUT Data V alid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
Unit
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 95
Page 96
Electrical characteristics
Data
Last Data
First Data
First Data
Data
Last Data
SIN
SOUT
PCSx
SCK Output
SCK Output
(CPOL = 0)
(CPOL = 1)
t
SCK
t
SDC
t
SDC
t
CSC
t
ASC
t
SUI
t
HI
t
SUO
t
HO
Data
Last Data
First Data
SIN
SOUT
Last Data
Data
First Data
SCK Output
SCK Output
PCSx
(CPOL = 0)
(CPOL = 1)
t
SUI
t
HI
t
SUO
t
HO
Figure 29. DSPI CMOS master mode – classic timing, CPHA = 0
Figure 30. DSPI CMOS master mode – classic timing, CPHA = 1
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors96
Page 97
Electrical characteristics
PCSx
PCSS
t
PCSC
t
PASC
Figure 31. DSPI PCS strobe (PCSS) timing (master mode)
3.16.2.1.2 DSPI CMOS Master Mode – Modified Timing
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 1
1
# Symbol Characteristic
1t
2t
3t
4t
CC SCK cycle time SCK drive strength
SCK
CC PCS to SCK delay SCK and PCS drive strength
CSC
CC After SCK delay SCK and PCS drive strength
ASC
CC SCK duty cycle
SDC
7
Condition Value
Pad drive
3
Load (CL)Min Max
2
Unit
Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —
Very strong 25 pF (N4 × t
Strong 50 pF (N4 × t
Medium 50 pF (N4 × t
PCS medium
and SCK
PCS = 50 pF
SCK = 50 pF
(N4 × t
5
)–16 —ns
SYS
5
)–16 —
SYS
5
)–16 —
SYS
5
)–29 —
SYS
strong
Very strong PCS = 0 pF
(M6 × t
5
)–35 —ns
SYS
SCK = 50 pF
Strong PCS = 0 pF
(M6 × t
5
)–35 —
SYS
SCK = 50 pF
Medium PCS = 0 pF
(M6 × t
5
)–35 —
SYS
SCK = 50 pF
PCS medium
and SCK
PCS = 0 pF
SCK = 50 pF
(M6 × t
5
)–35 —
SYS
strong
SCK drive strength
Very strong 0pF
Strong 0pF
Medium 0pF
1
/2t
–2
SCK
1
/2t
–2
SCK
1
/2t
–5
SCK
1
/2t
+2 ns
SCK
1
/2t
+2
SCK
1
/2t
+5
SCK
PCS strobe timing
NXP Semiconductors 97
MPC5777M Microcontroller Data Sheet, Rev. 6
Page 98
Electrical characteristics
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11
# Symbol Characteristic
5t
6t
7t
CC PCSx to PCSS
PCSC
time
CC PCSS to PCSx
PASC
time
CC SIN setup time to
SUI
SCK
CPHA = 0
8
8
9
SIN setup time to
8t
HI
SCK
CPHA = 1
CC SIN hold time from
SCK
CPHA = 0
9
9
SIN hold time from
SCK
CPHA = 1
9
Condition Value
Pad drive
3
Load (CL)Min Max
2
Unit
PCS and PCSS drive strength
Strong 25 pF 16.0 —ns
PCS and PCSS drive strength
Strong 25 pF 16.0 —ns
SIN setup time
SCK drive strength
Very strong 25 pF 25 – (P10×t
Strong 50 pF 32.75 – (P10×t
S
Medium 50 pF 52 – (P10×t
5
)— ns
SYS
SY
5
)
5
)—
SYS
—
SCK drive strength
Very strong 25 pF 25.0 — ns
Strong 50 pF 32.75 —
Medium 50 pF 52.0 —
SIN hold time
SCK drive strength
Very strong 0pF –1 + (P9×t
Strong 0pF –1 + (P9×t
Medium 0pF –1 + (P9×t
4
)— ns
SYS
4
)—
SYS
4
)—
SYS
SCK drive strength
Very strong 0pF –1.0 — ns
Strong 0pF –1.0 —
9t
SUO
CC SOUT data valid
time from SCK
CPHA = 0
10
SOUT data valid
time from SCK
CPHA = 1
10
MPC5777M Microcontroller Data Sheet, Rev. 6
Medium 0pF –1.0 —
SOUT data valid time (after SCK edge)
SOUT and SCK drive strength
Very strong 25 pF — 7.0 + t
Strong 50 pF — 8.0 + t
Medium 50 pF — 16.0 + t
SYS
SYS
SYS
5
5
5
SOUT and SCK drive strength
Very strong 25 pF — 7.0 ns
Strong 50 pF — 8.0
Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
NXP Semiconductors98
ns
Page 99
Electrical characteristics
Table 52. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or 11
2
5
5
5
—ns
—
—
# Symbol Characteristic
10 t
CC SOUT data hold
HO
time after SCK
CPHA = 0
11
SOUT data hold
time after SCK
CPHA = 1
11
Condition Value
3
Pad drive
Load (CL)Min Max
SOUT and SCK drive strength
Very strong 25 pF –7.7 + t
Strong 50 pF –11.0 + t
Medium 50 pF –15.0 + t
SYS
SYS
SYS
SOUT and SCK drive strength
Very strong 25 pF –7.7 — ns
Strong 50 pF –11.0 —
Medium 50 pF –15.0 —
1
All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2
All timing values for output signals in this table are measured to 50% of the output voltage.
3
Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds
and may cause incorrect operation.
4
N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software
programmable using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless
TSB mode or Continuous SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS
and SCK are driven by the same edge of DSPI_CLKn).
5
t
is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min
SYS
=10ns).
t
SYS
6
M is the number of clock cycles added to time between SCK negation and PCS negation and is software
programmable using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB
mode or Continuous SCK clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and
SCK are driven by the same edge of DSPI_CLKn).
7
t
is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd
SDC
divide ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8
PCSx and PCSS using same pad configuration.
9
Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10
P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is
automatically set to 1.
11
SOUT Data V alid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the
same value.
Unit
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors 99
Page 100
Electrical characteristics
Data
Last Data
First Data
First Data
Data
Last Data
SIN
SOUT
PCSx
SCK Output
SCK Output
(CPOL = 0)
(CPOL = 1)
t
SCK
t
SDC
t
SDC
t
CSC
t
ASC
t
SUI
t
HI
t
SUO
t
HO
Data
Last Data
First Data
SIN
SOUT
Last Data
Data
First Data
SCK Output
SCK Output
PCSx
(CPOL = 0)
(CPOL = 1)
t
SUI
t
HI
t
SUO
t
HO
t
HI
Figure 32. DSPI CMOS master mode – modified timing, CPHA = 0
Figure 33. DSPI CMOS master mode – modified timing, CPHA = 1
MPC5777M Microcontroller Data Sheet, Rev. 6
NXP Semiconductors100
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