Datasheet MPC5746R Datasheet (NXP Semiconductors)

NXP Semiconductors

Data Sheet: Technical Data

SPC5746R Microcontroller
Data Sheet

Features

• This document provides electrical specifications, pin
assignments, and package diagrams for the MPC5746R
series of microcontroller units (MCUs).

Document Number MPC5746R

Rev. 6, 06/2017

MPC5746R

• For functional characteristics, see the MPC5746R
Microcontroller Reference Manual.

NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.

Table of Contents

1 Introduction........................................................................................3

1.1 Block diagram......................................................................... 3

2 Package pinouts and signal descriptions............................................5

3 Absolute maximum ratings................................................................ 6

4 Electromagnetic Compatibility (EMC)..............................................7

5 Electrostatic discharge (ESD)............................................................ 7

6 Operating conditions.......................................................................... 8

7 DC electrical specifications................................................................11

8 I/O pad specification.......................................................................... 12

8.1 Input pad specifications...........................................................12

8.2 Output pad specifications........................................................15

8.3 I/O pad current specifications................................................. 17

9 Reset pad (PORST, RESET) electrical characteristics...................... 18

10 Oscillator and FMPLL....................................................................... 22

11 ADC modules.....................................................................................26

11.1 ADC input description............................................................ 26

11.2 SAR ADC................................................................................26

11.3 S/D ADC................................................................................. 29

12 Temperature sensor............................................................................ 39

13 LVDS fast asynchronous serial transmission (LFAST) pad

electrical characteristics..................................................................... 40

13.1 LFAST interface timing diagrams...........................................40

13.2 LFAST and MSC /DSPI LVDS interface electrical

characteristics..........................................................................42

14 LFAST PLL electrical characteristics................................................45

15 Aurora LVDS electrical characteristics............................................. 46

16 Power management PMC POR LVD sequencing..............................47

16.1 Power management electrical characteristics..........................47

16.1.1 Recommended power transistors............................47

16.1.2 Power management integration.............................. 48

16.1.3 Regulator example for the NJD2873 transistor...... 50

16.1.4 Regulator example for the 2SCR574d transistor.... 51

16.1.5 Device voltage monitoring......................................51

16.1.6 Power up/down sequencing.................................... 53

17 Flash memory specifications..............................................................54

17.1 Flash memory program and erase specifications.................... 54

17.2 Flash memory Array Integrity and Margin Read

specifications...........................................................................55

17.3 Flash memory module life specifications................................55

17.4 Data retention vs program/erase cycles...................................56

17.5 Flash memory AC timing specifications................................. 57

17.6 Flash read wait state and address pipeline control settings..... 58

18 AC specifications............................................................................... 58

18.1 Debug and calibration interface timing................................... 58

18.1.1 JTAG interface timing............................................ 58

18.1.2 Nexus interface timing............................................61

18.1.3 Aurora LVDS interface timing............................... 63

18.2 DSPI timing with CMOS and LVDS...................................... 65

18.2.1 DSPI master mode full duplex timing with CMOS

and LVDS pads.......................................................66

18.2.2 DSPI CMOS slave mode........................................ 78

18.3 FEC timing.............................................................................. 80

18.3.1 MII-lite receive signal timing (RXD[3:0],

RX_DV, RX_ER, and RX_CLK)...........................80

18.3.2 MII-lite transmit signal timing (TXD[3:0],

TX_EN, TX_ER, TX_CLK)...................................81

18.3.3 MII-lite async inputs signal timing (CRS and

COL)....................................................................... 82

18.3.4 MII-lite serial management channel timing

(MDIO and MDC).................................................. 82

18.3.5 RMII serial management channel timing (MDIO

and MDC)............................................................... 83

18.3.6 RMII receive signal timing (RXD[1:0], CRS_DV)84

18.3.7 RMII transmit signal timing (TXD[1:0], TX_EN). 85

18.4 UART timings......................................................................... 86

18.5 eMIOS timing..........................................................................86

19 Obtaining package dimensions.......................................................... 86

20 Thermal characteristics...................................................................... 87

20.1 General notes for specifications at maximum junction

temperature..............................................................................89

21 Ordering information......................................................................... 90

22 Revision history................................................................................. 91

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

2 NXP Semiconductors

Introduction

1 Introduction

The MPC5746R family of 32-bit microcontrollers is the latest achievement in integrated
automotive application controllers. It belongs to an expanding range of automotive­focused products designed for flexibility to support a variety of applications. The
advanced and cost-efficient host processor core of the MPC5746R automotive controller
family complies with the Power Architecture embedded category. It operates at speeds as
high as 200 MHz and offers high-performance processing optimized for low power
consumption. It capitalizes on the available development infrastructure of current Power
Architecture devices and is supported with software drivers, operating systems, and
configuration code to assist with users' implementations. This section contains detailed
information on power considerations, DC/AC electrical characteristics, and AC timing
specifications.

Note

Within this document, V
V

DD_HV_IO_JTAG

, V

DD_HV_IO_FEC

DD_HV_IO

refers to supply pins V

, and V

DD_HV_IO_MSC

DD_HV_IO_MAIN

,

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 3

MPC5746R

Safety Lake

Ethernet

LFAST & SIPI

64ch. eDMA

w/ E2E Ecc

DMACHMUX

w/ E2E Ecc

64ch. eDMA

Delay

RCCU

Concentrator

w/ E2E Ecc

50 MHz

Nexus Data

Trace

Concentrator

w/ E2E Ecc

100 MHz

Nexus Data Trace

32 ADD
32 DATA

32 ADD
32 DATA

Slow Cross Bar Switch (AMBA 2.0 v6 AHB) - 32 bit - 100 MHz

System Memory Protection Unit (SMPU_1)

M3

M4

S0

S3

S7

M1M2

S2

S3

AIPS PBridge_0

E2E Ecc

Decorate Storage

50MHz

AIPS PBridge_1

E2E Ecc

Decorate Storage

50MHz

32 ADD

32 DATA

32 ADD

32 DATA

Peripheral
Cluster A

Peripheral
Cluster B

Peripherals allocation to the bridges is
based on safety and pinout
requirements

Double INTC

SWT_1
STM_1

E200 z425 - 200 MHz
Main Core_1

DSP

VLE

Scalar

SP-FPU

Nexus3p

I -Mem ctrl

I-Cache ctrl

16kB

IMEM

8kB - 2way

D -Mem ctrl

32kB

DMEM

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

32 ADD

64 DATA

Instruction

32 ADD

64 DATA

Load/
Store

32 ADD

64 DATA

Instruction

Load/
Store

32 ADD

64 DATA

M2

S2

M3

M0

S0

M1

S1 S4

Fast Cross Bar Switch (AMBA 2.0 v6 AHB) - 64 bit - 200 MHz

System Memory Protection Unit (SMPU_0)

SWT_0
STM_0

E200 z425 - 200 MHz
Main Core_0

DSP

VLE

Scalar

SP-FPU

Nexus3p

I -Mem ctrl

I-Cache ctrl

16kB

IMEM

8kB - 2way

D -Mem ctrl

32kB

DMEM

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

w/ E2E Ecc

Unified Backdoor I/F

w/ E2E Ecc

Unified Backdoor I/F

DSP

VLE

Scalar

SP-FPU

I -Mem ctrl

I-Cache ctrl

D -Mem ctrl

Core Memory Protection Unit (CMPU)

BIU with E2E ECC

w/ E2E Ecc

Unified Backdoor I/F

Nexus RWA

E200 z424 - 200 MHz

Checker Core_0s

Computational Shell - Fast Domain 200MHz

32 ADD

64 DATA

32 ADD

64 DATA

32 ADD

64 DATA

SRAM Ctrl

w/ E2E Ecc

Decorated

access

Intelligent
Bridging
Bus gasket

Standby

Supply

FLASH Controller

Dual Ported

Incl. Set-Associative

Prefetch Buffers

w/ E2E Ecc

Overlay
Backdoor
for
system
RAM

SRAM
224KB

Standby

SRAM

32KB

Standby

Regulator

Overlay

RAM
16kB

Flash

4MB

EEPROM

256k

256 Page Line

2 stage Pipeline

NVM (Single Module)

Calibration

Bus

Buddy

Device

Interface

JTAGM

JTAGC

DCI SPU

Nexus
Aurora
Router

Delayed Lock-step

with Redundnacy

Checkers

Delay

Delay

RCCU

RCCU

Safety Lake

Peripheral Domain - 50 MHz

Introduction

1.1 Block diagram

Figure 1. Core block diagram

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

4 NXP Semiconductors

DMAMUX_3

FlexCAN_3

FlexCAN_1

CRC_1

CMU

FCCU

eMIOS_1

DSPI_M1

DSPI_3

DSPI_1

SENT_1

LINFlex_M1

LINFlex_3

LINFlex_1

ADC_SD_1

ADC_SAR_3

ADC_SAR_1

LINFlex_M0

LINFlex_2

LINFlex_0

FlexCAN_2

FlexCAN_0

PMC

PCU

DECFILTER_1

BAR

SSCM

PASS

CFLASH

LFAST

Zipwire

SIUL2

ME

CGM

BCTU

PLLs

XOSC

RCOSC

RGM

PIT

DMAMUX_0

DMAMUX_1

DMAMUX_2

WKPU

DSPI_M0

DSPI_4

DSPI_2

DSPI_0

DECFILTER_0

PIT_RTI

ATX

MEMU

JTAGM

STCU2

JDC

TDM

ADC_SD_2

ADC_SD_0

ADC_SAR_2

ADC_SAR_0

SENT_0

DTS

CRC_0

REACM

eTPU_0 Reg.

eTPU_0 Code.

RAM

RAM

eTPU_0 Par.

eMIOS_0

FEC

eDMA

3x SWT

2x STM

INTC

SEMA4

PFLASH

PCM

PRAM

2 x SMPU

2x XBIC

PERIPHERAL CLUSTER B

PERIPHERAL CLUSTER A

IGF

PBRIDGE_1

2x XBAR

PBRIDGE_0

EIM

Package pinouts and signal descriptions

2

Package pinouts and signal descriptions

Figure 2. Peripherals allocation

For package pinouts and signal descriptions, refer to the Reference Manual.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 5

Absolute maximum ratings

3 Absolute maximum ratings

Functional operating conditions are given in the DC electrical specifications. Absolute
maximum voltages are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond listed maxima may affect device reliability or cause permanent
damage to the device.

Table 1. Absolute maximum ratings

Symbol Parameter Conditions

Cycle Lifetime power cycles — 1000k —

V

DD_LV

V

DD_LV_BD

V

DD_HV_IO_MAIN

V

DD_HV_IO_JTAG

V

DD_HV_IO_FEC

V

DD_HV_IO_MSC

V

DD_HV_PMC

V

DD_HV_FLA

V

DDSTBY

V

SS_HV_ADV_SD

V

SS_HV_ADV_SAR

V

DD_HV_ADV_SAR

V

DD_HV_ADV_SD

V

SS_HV_ADR_SD

V

SS_HV_ADR_SAR

V

DD_HV_ADR_SAR

V

DD_HV_ADR_SD

V

DD_LV_BD

- V

DD_LV

1.2 V core supply voltage
Emulation module voltage
I/O supply voltage

5

Crystal oscillator and JTAG supply Reference to V
FEC supply voltage Not using Ethernet Reference to

MSC supply voltage Reference to V
Power Management Controller supply

voltage

6

Decoupling pin for flash regulator
RAM standby supply voltage
S/D ADC ground voltage Reference to V
SAR ADC ground voltage Reference to V
SAR ADC supply voltage Reference to V
S/D ADC supply voltage Reference to V
S/D ADC ground reference Reference to V
SAR ADC ground reference Reference to V
SAR ADC alternate reference Reference to V
S/D ADC alternate reference Reference to V
Emulation module supply differential to 1.2

2, 3, 4

2, 3, 4

6

6

V core supply

VSS – V

VSS – V

VSS – V

VSS – V

SS_HV_ADR_SARVSS_HV_ADR_SAR

SS_HV_ADR_SDVSS_HV_ADR_SD

SS_HV_ADV_SARVSS_HV_ADV_SAR

SS_HV_ADV_SDVSS_HV_ADV_SD

V

I

INJD

IN

I/O input voltage range

Maximum DC injection current for digital

differential voltage — –0.3 0.3 V

differential voltage — –0.3 0.3 V

differential voltage — –0.3 0.3 V

differential voltage — –0.3 0.3 V

7

pad

1

Value

Min Max

Unit

— –0.3 1.5 V
— –0.3 1.5 V
— –0.3 6.0 V

SS

–0.3 6.0 V
–0.3 6.0 V

V

SS

SS

—

–0.3 6.0 V
–0.3 6.0 V

— –0.3 — V
— –0.3 6.0 V

SS

SS

SS_HV_ADV_SAR

SS_HV_ADV_SD

SS

SS

SS_HV_ADR_SAR

SS_HV_ADR_SD

—

–0.3 0.3 V
–0.3 0.3 V
–0.3 6.0 V
–0.3 6.0 V
–0.3 0.3 V
–0.3 0.3 V
–0.3 6.0 V
–0.3 6.0 V
–0.3 1.5 V

— –0.3 6.0 V
Relative to V
Relative to V

SS_HV_IO

DD_HV_IO

, 8, 9

8, 9

–0.3 —

— 0.3

Per pin, applies to all digital pins –5 5 mA

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

6 NXP Semiconductors

Electromagnetic Compatibility (EMC)

Table 1. Absolute maximum ratings (continued)

Symbol Parameter Conditions

I

INJA

Maximum DC injection current for analog

Per pin, applies to all analog pins –5 5 mA

1

Value

Min Max

Unit

pad

MAXSEG

T

STG

10, 11

Maximum current per I/O segment — –120 120 mA
Storage temperature range and non-

operating times

STORAGE Maximum storage time, assembled part

programmed in ECU

T

SDR

Maximum solder temperature

12

—

No supply; storage temperature
in range –40 °C to 60 °C

—

–55 175 °C

— 20 yrs

— 260 °C

I

Pb-free package

MSL Moisture sensitivity level

13

— — 3 —

1. Voltage is referenced to VSS unless otherwise noted.

2. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ = 150 °C, remaining time as defined in note -1 and
note -1.

3. Allowed 1.375 – 1.45 V for 10 hours cumulative time at maximum TJ = 150 °C, remaining time as defined in note -1.

4. 1.32 – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.275 V at
maximum TJ = 150 °C.

5. Allowed 5.5 – 6.0 V for 10 hours cumulative time at maximum TJ = 150 °C, remaining time at or below 5.0 V +10%.

6. Allowed 3.6 – 4.5 V for 10 hours cumulative time at maximum TJ = 150 °C, remaining time at or below 3.3 V +10%. This is
an internally regulated supply. Values given are for reference only.

7. The maximum input voltage on an I/O pin tracks with the associated I/P supply maximum. For the injection current
condition on a pin, the voltage will be equal to the supply plus the voltage drop across the internal ESD diode from I/O pin
to supply. The diode voltage varies greatly across process and temperature, but a value of 0.3V can be used for nominal
calculations.

8. Relative value can be exceeded, if design measures are taken to ensure injection current limitation (parameters I
I

).

INJA

9. V

DD_HV_IO/VSS_HV_IO

V

DD_HV_IO_MSC

10. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V

defined as one or more GPIO pins located between two V

refers to supply pins and corresponding grounds: V

.

DD_HV_IO

DD_HV_IO_MAIN

supply pins.

, V

DD_HV_IO_JTAG

DD_HV_IO

, V

DD_HV_IO_FEC

power segment is

INJD

and

,

11. The average current values given in the "I/O pad current specifications" section should be used to calculate total I/O

segment current.

12. Solder profile per IPC/JEDEC J-STD-020D.

13. Moisture sensitivity per JEDEC test method A112.

4 Electromagnetic Compatibility (EMC)

EMC measurements to IC-level IEC standards are available from NXP on request.

Electrostatic discharge (ESD)

5

The following table describes the ESD ratings of the device.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 7

Operating conditions

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for
Automotive Grade Integrated Circuits.

Device failure is defined as: "If after exposure to ESD pulses, the device does not meet
the device specification requirements, which includes the complete DC parametric and
functional testing at room temperature and hot temperature. Maximum DC parametrics
variation within 10% of maximum specification."

Table 2. ESD ratings

Parameter Conditions Value Unit

ESD for Human Body Model (HBM)
ESD for field induced Charged Device Model (CDM)

1. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing

2. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level

1

2

All pins 2000 V
All pins 500 V

6 Operating conditions

The following table describes the operating conditions for the device, and for which all
specifications in the data sheet are valid, except where explicitly noted.

The device operating conditions must not be exceeded in order to guarantee proper
operation and reliability.

NOTE

All power supplies need to be powered up to ensure normal
operation of the device.

Table 3. Device operating conditions

Symbol Parameter Conditions

Frequency

f

SYS

T

J

TA (TL to TH) Operating temperature range -

V

DD_LV

V

DD_HV_IO_MAIN

Device operating frequency

Operating temperature range ­junction

ambient

External core supply voltage

I/O supply voltage

7

Table continues on the next page...

1

Temperature

Voltage

2, 3

TJ -40 °C to 150 °C — — 200 MHz

LVD/HVD enabled 1.2 — 1.32 V
LVD/HVD disabled

4, 5, 6

Min Typ Max

–40.0 — 150.0 °C

–40.0 — 125.0 °C

1.18 — 1.38

3.5 — 5.5 V

Value

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

8 NXP Semiconductors

Table 3. Device operating conditions (continued)

Operating conditions

Symbol Parameter Conditions

V

DD_HV_IO_FEC

V

DD_HV_IO_MSC

V

DD_HV_IO_JTAG

I

IC

12

13

– VSSV

– VSSV

V

DD_HV_PMC

V

DDSTBY

V

STBY_BO

V

DD_LV_STBY_SW

V

DD_HV_ADV_SD

V

DD_HV_ADV_SAR

V

DD_HV_ADR_SD

V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

V

SS_HV_ADR_SD

V

SS_HV_ADV_SD

V

DD_HV_ADR_SAR

V

DD_HV_ADR_SAR

V

DD_HV_ADV_SAR

V

SS_HV_ADR_SAR

V

SS_HV_ADV_SAR

V

SS_HV_ADV_SD

V

SS_HV_ADV_SAR

V

RAMP_VDD_LV

V

RAMP_VDD_HV_IO_MAIN

V

RAMP_VDD_HV_PMC

I

MAXSEG

Value

Min Typ Max

FEC I/O supply voltage

8

5 V range 3.5 — 5.5 V

3.3 V range 3.0 — 3.6

MSC I/O supply voltage

9

5 V range 3.5 — 5.5 V

3.3 V range 3.0 — 3.6

10

JTAG I/O supply voltage

11

5 V range 3.5 — 5.5 V

3.3 V range 3.0 — 3.6

Power Management Controller

Full functionality 3.5 — 5.5 V

(PMC) supply voltage
RAM standby supply voltage

14

— 1.3 — 5.9 V
Standby RAM brownout voltage — — — 0.9 V
Standby RAM switch V

threshold
S/D ADC supply voltage
SAR ADC supply voltage

17

DD_LV

15, 16

voltage

—

0.95 — — V

— 4.5 — 5.5 V

3.0 — 5.5 V

—

S/D ADC reference — 3.0 — 5.5 V

–

S/D ADC reference differential
voltage

–

V

SS_HV_ADR_SD

differential voltage

—

—

— — 25 mV

–25 — 25 mV

SAR ADC reference — 3.0 — 5.5 V

–

SAR ADC reference differential
voltage

–

V

SS_HV_ADR_SAR

SS_HV_ADV_SD

SS_HV_ADV_SAR

differential voltage

differential voltage — –25 — 25 mV

differential voltage — –25 — 25 mV

Slew rate on power supply pins
(VDD_LV)

,

Slew rate on power supply pins
(VDD_HV_IO_MAIN,
VDD_HV_PMC)

—

—

Ramp up 0.069 — 100 V/ms

Ramp down 0.0345 — 100

Ramp up 0.148 — 100 V/ms

Ramp down 0.125 — 100

— — 25 mV

–25 — 25 mV

Injection current

DC injection current (per pin)
Maximum current per power

segment

21, 22

18, 19, 20

Digital pins and analog pins –3.0 — 3.0 mA

—

–80 — 80 mA

Unit

1. Maximum operating frequency is applicable to the computational cores and platform for the device.

2. Core voltage as measured on device pin to guarantee published silicon performance.

3. During power ramp, voltage measured on silicon might be lower. maximum performance is not guaranteed, but correct
silicon operation is guaranteed. See power management and reset management for description.

4. Maximum core voltage is not permitted for entire product life. See absolute maximum rating.

5. When internal LVD/HVDs are disabled, external monitoring is required to guarantee device operation. Failure to monitor
externally supply voltage may result in erroneous operation of the device.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 9

Operating conditions

6. This LVD/HVD disabled supply voltage condition only applies after LVD/HVD are disabled by the application during the
reset sequence, and the LVD/HVD are active until that point.

7. The pad are operative till 3.0V full performance. The IRC oscillator is supplied by this pin and it is setting the min voltage
limit.

8. FEC will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of
IO_MAIN.

9. MSC will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of
IO_MAIN.

10. If XOSC is enabled via DCF_UTEST_Miscellaneous[XOSC_EN], V

DD_HV_IO_JTAG

must be within the operating range

before RESET pin is released.

11. JTAG will be used only in 3.3V mode. In 5V mode the segment is a general IO segment with the same characteristics of

IO_MAIN.

12. The startup of flash regulator and memory initialization immediately after Phase0 of reset sequence could cause a drop of

the PMC supply. No LVD event will be generated as during this time the LVD monitors are not enabled.

13. V

supply must be present before and after power up/down of the device supplies and the ramp rate should be less

DDSTBY

than 33.3 kV/s.

14. RAM retention is not guaranteed below 1.3 V, but no effect on RAM operation for voltages below 1.3 V when V

DD_LV

is

above the minimum value.

15. For supply voltages between 3.6V and 4.5V there will be no guaranteed precision of ADC (accuracy/linearity). ADC will

recover to a fully functional state when the voltage rises above 4.5V.

16. V

DD_HV_ADV_SD

to connect the V

must be higher or equal than the V

DD_HV_ADV_SD

to V

DD_HV_ADV_SAR

DD_HV_ADV_SAR

at board level.

supply to guarantee full performance. It is recommended

17. Temperature Sensor and its associated Band-Gap reference are supplied by this pin. The temperature sensor

performance is guaranteed only between 4.5 V and 5.5 V.

18. Full device lifetime without performance degradation.

19. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the

absolute maximum ratings table for maximum input current for reliability requirements.

20. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is

above the supply rail, current will be injected through the clamp diode to the supply rail. For external RC network
calculation, assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature. For more
information, see the device characterization report.

21. Sum of all controller pins (including both digital and analog) must not exceed 200 mA. A V

defined as one or more GPIO pins located between two V

DD_HV_IO

supply pins.

DD_HV_IO

power segment is

22. The average current values given in the "I/O pad current specifications" section should be used to calculate total I/O

segment current.

Table 4. Emulation (buddy) device operating conditions

Symbol Parameter Conditions

Frequency

— Standard JTAG 1149.1/1149.7 frequency — — — 50 MHz
— High-speed debug frequency — — — 320 MHz
— Data trace frequency — — — 1250 MHz

Temperature

T

T

J_BD

A _BD

Device junction operating temperature range Packaged devices –40.0 — 150.0 °C
Ambient operating temperature range Packaged devices –40.0 — 125.0 °C

Voltage

V

DD_LV_BD

V

DD_HV_IO_B

D

V

RAMP_BD

Buddy core supply voltage — 1.18 — 1.32 V
Buddy I/O supply voltage — 3.0 — 5.5 V

Buddy slew rate on power supply pins — — — 500 V/ms

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

10 NXP Semiconductors

Value

Unit

Min Typ Max

7 DC electrical specifications

The following table describes the DC electrical specifications.

Table 5. DC electrical specifications

DC electrical specifications

Symbol Parameter Conditions

I

DD_LV

Maximum operating
current on the V

1

supply

DD_LV

MPC5746R/
MPC5745R

MPC5743R/
MPC5742R

I

DD_LV_PE

Operating current on the
V

supply for flash

DD_LV

—

program/erase

I

DD_HV_PMC

Operating current on the
V

DD_HV_PMC

supply

2

Flash read — — 40 mA
Flash P/E — — 70
PMC only — — 35

Operating current on the
V

DD_HV_PMC

supply

(internal core reg

Flash read — — 10 mA
Flash P/E — — 40

bypassed)

I

VRCCTRL

I

DDSTBY_ON

Core regulator DC current
output on VRC_CTRL pin

32 KB RAM Standby
Leakage Current
(standby regulator on,
RAM not operational)

3, 4, 5

—

V

DDSTBY @

5.9 V, TJ = 150 °C
V

DDSTBY @

5.9 V, TA = 40 °C
V

DDSTBY @

5.9 V, TA = 85 °C

I

DDSTBY_REG

I

DD_LV_BD

I

DD_HV_IO_BD

32 KB RAM Standby
Regulator Current

6

BD Debug/Emulation low
voltage supply operating

7

current

Debug/Emulation high

V

DDSTBY @

5.9 V, Tj = 150 °C
TJ = 150 °C
V

DD_LV_BD

V

TJ = 150 °C — — 130 mA
voltage supply operating
current (Aurora + JTAG/
LFAST)

I

BG

Bandgap reference
current consumption

I

DD_BD_STBY

I

VDDA

BD Debug/Emulation low
voltage supply standby
current

TJ = 150 °C

V

DD_LV_BD

V
VDDA supply current — 16 25 mA

1.3 V to

1.3 V to

1.3 V to

1.2 V to

= 1.32

= 1.32

Value

Unit

Min Typ Max

— — 700 mA

— — 610

— — 40 mA

— — 25 mA

— — 575 µA

— — 55

— — 65

— — 50 µA

— 250 mA

—

— — 600 µA

— — 120 mA

1. Value is derived from a typical application at 200MHz, Core 0 Data and Instruction Cache On, Core 1 in Lockstep mode,
typical usage for SARADC, SDADC, DMA, eTPU, eMIOS, CAN, MSC, SPI, SENT, PIT, and Flash reads.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 11

I/O pad specification

2. This value is considering the use of the internal core regulator with an external ballast with the minimum value of hFE of 60.

3. Data is retained for full TB range of -40 °C to 125 °C. RAM supply switch to the standby regulator occurs when the V
supply falls below 0.95V.

4. V
absolute maximum ratings table must be observed.

5. The maximum value for I
powering up the device and switching the RAM supply back to V

6. When the V
standby mode or not. No current is present on the pin when V

7. Worst case usage (data trace, data overlay, full Aurora utilization).

may be supplied with a non-regulated power supply, but the absolute maximum voltage on V

DDSTBY

DDSTBY_ON

pin is powered, the standby RAM regulator current is present on the pin, regardless if the device is in

DDSTBY

is also valid when switching from the core supply to the standby supply, and when

DD_LV

pin is set to 0V, disabling the standby regulator.

DDSTBY

DDSTBY

given in the

DD_LV

8 I/O pad specification

The following table describes the different pad type configurations.

Table 6. I/O pad specification descriptions

Pad type Description

General-purpose I/O pad General-purpose I/O pads with four selectable output slew

rate settings. The GPIO pads have CMOS input threshold

levels.
LVDS pads Low Voltage Differential Signal interface pads
Input only pads These pads, which ensure low input leakage, are associated

with the ADC channels. The digital inputs of these pads have

CMOS, and TTL input threshold levels.

8.1

Note

Each I/O pin on the device supports specific drive
configurations. See the signal description table in the device
reference manual for the available drive configurations for each
I/O pin.

Input pad specifications

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

12 NXP Semiconductors

V

IL

V

IN

V

DD

V

IH

V

INTERNAL

V

HYS

(SIUL register)

Figure 3. I/O input DC electrical characteristics definition

Table 7. I/O input DC electrical characteristics

Symbol Parameter

VIHTTL TTL input high level 3.0 V < V

VILTTL TTL input low level 3.0 V < V
VHYSTTL TTL level input hysteresis 3.0 V < V
VDRFTTTL TTL Input VIL/VIH

temperature drift

VIHCMOS_H CMOS input high level

(with hysteresis)

VIHCMOS CMOS input high level

(without hysteresis)

VILCMOS_H CMOS input low level (with

hysteresis)

VILCMOS CMOS input low level

(without hysteresis)

VHYSCMOS CMOS input hysteresis 3.0 V < V

VDRFTCMOSCMOS Input VIL/VIH

INPUT CHARACTERISTICS
I

LKG

C

IN

temperature drift

Digital input leakage GPIO pins

Input capacitance GPIO and Input pins — — 8 pF

1

— — — 100

3.0 V < V

3.0 V < V

3.0 V < V

3.0 V < V

— — — 100

4

VSS < VIN < V

Conditions Value

Min Typ Max

DD_HV_IO

DD_HV_IO

DD_HV_IO

DD_HV_IO

DD_HV_IO

DD_HV_IO

DD_HV_IO

DD_HV_IO

< 5.5 V 2.0 — V

< 5.5 V V

-0.3 — 0.6 V

SS

< 5.5 V 0.3 — — V

< 5.5 V 0.65 *

V

DD_HV_IO

< 5.5 V 0.55 *

V

DD_HV_IO

< 5.5 V V

< 5.5 V V

SS

SS

< 5.5 V 0.1 *

V

DD_HV_IO

-0.3 — 0.35 *

-0.3 — 0.4 *

— V

— V

— — V

-1.0 — 1.0 µA

DD_HV_IO

I/O pad specification

2

DD_HV_IO

+

0.3

3

DD_HV_IO

+ 0.3

DD_HV_IO

+

0.3

V

DD_HV_IO

V

DD_HV_IO

3

Unit

V

mV

V

V

V

V

mV

1. Supported input levels vary according to pad types. Pad type "pad_sr_hv" supports only the CMOS input level, while pad
type "pad_isatww_st_hv" supports TTL and CMOS levels. Refer to the IO spreadsheet attached to the Reference Manual
for the pad type of each pin.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 13

I/O pad specification

2. TTL level input specifications apply to the digital inputs on the analog input pins, and not the GPIO pins on the device.

3. In a 1 ms period, assuming stable voltage and a temperature variation of ±30 °C, VIL/VIH shift is within ±50 mV. For
SENT requirement, refer to Note in the "I/O pad current specifications" section.

4. For LFAST, microsecond bus, and LVDS input characteristics, refer to dedicated communication module chapters.

The following table provides the current specifications for the GPIO pad weak pull-up
and pull-down.

Table 8. GPIO Pull-Up/Down DC electrical characteristics

Symbol Parameter Conditions Value Unit

Min Typ Max

|IWPU| Weak pull-up current

absolute value

1

|IWPD| Weak pull-down current

absolute value

Vin = VIH = 0.65 * V

4.5V < V

3.0V < V

DD_HV_IO

DD_HV_IO

Vin = VIL = 0.35 * V

4.5V < V

3.0V < V

DD_HV_IO

DD_HV_IO

DD_HV_IO

< 5.5V 30 — —
< 3.6V 18 — —

DD_HV_IO

< 5.5V — — 120
< 3.6V — — 80

Vin = VIL = 1.1V (TTL)

4.5V < V

DD_HV_IO

Vin = VIH = 0.65 * V

4.5V < V

3.0V < V

DD_HV_IO

DD_HV_IO

Vin = VIL = 0.35 * V

4.5V < V

3.0V < V

DD_HV_IO

DD_HV_IO

< 5.5V — — 130

DD_HV_IO

< 5.5V — — 120
< 3.6V — — 80

DD_HV_IO

< 5.5V 30 — —
< 3.6V 18 — —

Vin = VIL = 0.9V (TTL)

4.5V < V

DD_HV_IO

< 5.5V 16 — —

µA

µA

1. Weak pull-up/down is enabled within tWK_PU = 1 µs after internal/external reset has been asserted. Output voltage will
depend on the amount of capacitance connected to the pin.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

14 NXP Semiconductors

DD_HV_IO

V

V

DD_POR

RESET

(INTERNAL)

pull-up

enabled

RESET

YES

NO

PAD

POWER-UP Application defined Application defined

POWER-DOWN

t

WK_PU

t

WK_PU

(1)

(1)

(1)

1

Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply.

I/O pad specification

Figure 4. Weak pull-up electrical characteristics definition

Analog input leakage and pull up/down information is located in the ADC input
description section.

8.2

Output pad specifications

The following figure provides the description of output DC electrical characteristics.

NXP Semiconductors 15

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

10%

V

out

V

INTERNAL

V

HYS

(SIUL2 register)

20%

80%

90%

t

R10-90

t

R20-80

t

F10-90

t

F20-80

tTR(max) = MAX(t

R10-90;tF10-90

)

t

TR

(min) = MIN(t

R10-90;tF10-90

)

t

TR20-80

(max) = MAX(t

R20-80;tF20-80

)

t

TR20-80

(min) = MIN(t

R20-80;tF20-80

)

t

SKEW20-80

= t

R20-80-tF20-80



t

SKEW20-80

50%

t

PD t

PD

I/O pad specification

Figure 5. I/O output DC electrical characteristics definition

Table 9. GPIO pad output buffer electrical characteristics

Symbol Parameter Conditions Value 1,

Min Typ Max

VOH GPIO pad output high voltage 4.5V < VDD_HV_IO < 5.0V

MSCR[OERC] = 11, IOH = 38mA
MSCR[OERC] = 10, IOH = 19mA
MSCR[OERC] = 01, IOH = 10mA

0.8 *
VDD_H
V_IO

— — V

MSCR[OERC] = 00, IOH = 5mA

3.0V < VDD_HV_IO < 3.6V
MSCR[OERC] = 11, IOH = 19mA
MSCR[OERC] = 10, IOH = 10mA
MSCR[OERC] = 01, IOH = 7mA

0.8 *
VDD_H
V_IO

— —

MSCR[OERC] = 00, IOH = 5mA

VOL GPIO pad output low voltage 4.5V < VDD_HV_IO < 5.0V

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

MSCR[OERC] = 11, IOL = 48mA
MSCR[OERC] = 10, IOL = 24mA
MSCR[OERC] = 01, IOL = 12mA

Table continues on the next page...

— — 0.2 *

16 NXP Semiconductors

2

VDD_H
V_IO

Unit

V

Table 9. GPIO pad output buffer electrical characteristics (continued)

Symbol Parameter Conditions Value 1,

Min Typ Max

MSCR[OERC] = 00, IOL = 6mA

tR_F GPIO pad output transition

time (rise/fall)

tPD GPIO pad output propagation

delay time

|t

SKEW_W

| Difference between rise and

fall time

3.0V < VDD_HV_IO < 3.6V
MSCR[OERC] = 11, IOL = 24mA
MSCR[OERC] = 10, IOL = 12mA
MSCR[OERC] = 01, IOL = 9mA
MSCR[OERC] = 00, IOL = 6mA
MSCR[OERC] = 11 CL = 25pF — — 1.5 ns

CL = 50pF — — 3
MSCR[OERC] = 10 CL = 50pF — — 6.5
MSCR[OERC] = 01 CL = 50pF — — 25
MSCR[OERC] = 00 CL = 50pF — — 40
MSCR[OERC] = 11 CL = 25pF — — 6 ns

CL = 50pF — — 7.5
MSCR[OERC] = 10 CL = 50pF — — 11.5
MSCR[OERC] = 01 CL = 50pF — — 45
MSCR[OERC] = 00 CL = 50pF — — 75

- — — 10 %

— — 0.2 *

I/O pad specification

2

VDD_H
V_IO

Unit

1. All GPIO pad output specifications are valid for 3.0V < VDD_HV_IO < 5.5V, except where explicitly stated.

2. All values need to be confirmed during device validation.

8.3 I/O pad current specifications

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD_HV_IO/VSS_HV_IO supply pair.

The following tables provides I/O consumption figures.

Table 10. I/O current consumption at VDD_HV_IO = 3.6 V

Cell VDD_HV_IO

(V)

pad_sr_hv 3.63 25 12 11 13 37

Load (pF) Period1 (ns) MSCR[OERC] Idde AVG (mA) Idde RMS (mA)

50 15 16 36

200 39 20 44

25 16 10 8 20
50 23 9 21

200 66 12 37

50 90 01 1.4 4

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 17

Reset pad (PORST, RESET) electrical characteristics

Table 10. I/O current consumption at VDD_HV_IO = 3.6 V (continued)

Cell VDD_HV_IO

(V)

Load (pF) Period1 (ns) MSCR[OERC] Idde AVG (mA) Idde RMS (mA)

200 130 3 9

50 150 00 1.6 4

200 200 4 11

Table 11. I/O current consumption at VDD_HV_IO = 5.5 V

Cell VDD_HV_IO

(V)

pad_sr_hv 5.5 25 9 11 37 83

Load (pF) Period1 (ns) MSCR[OERC] Idde AVG (mA) Idde RMS (mA)

50 10.2 42 89

200 26 46 92

25 10.5 10 25 53
50 16 21 44

200 44 26 49

50 54 01 6 14

200 80 15 35

50 80 00 4 9

200 130 9 22

In order to ensure device reliability, the average current of the I/O on a single segment
should remain below the I

MAXSEG

value given in the table "Absolute maximum ratings".

In order to ensure device functionality, the sum of the dynamic and static current of the
I/O on a single segment should remain below the I

MAXSEG

value given in the table

"Device operating conditions".

Note

The MPC5746R I/O Signal Description and Input Multiplexing
Tables are contained in a Microsoft Excel workbook file
attached to the Reference Manual.

9

Reset pad (PORST, RESET) electrical characteristics

The device implements a dedicated bidirectional reset pin (PORST).

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

18 NXP Semiconductors

V

IL

V

DD

V

DDMIN

PORST

V

IH

device start-up phase

V

DDPOR

PORST driven low

device reset
forced by external circuitry

PORST undriven
device reset by

by internal power-on reset

internal power-on reset

Reset pad (PORST, RESET) electrical characteristics

NOTE

PORST pin does not require active control. It is possible to
implement an external pull-up to ensure correct reset exit
sequence. Recommended value is 4.7 kohm.

PORST can optionally be connected to an external power-on
supply circuitry.

No restrictions exist on reset signal slew rate apart from
absolute maximum rating compliance.

Figure 6. Start-up reset requirements

The following figure describes device behavior depending on supply signal on PORST:

1. PORST low pulse amplitude is too low—it is filtered by input buffer hysteresis.
Device remains in current state.

2. PORST low pulse duration is too short—it is filtered by a low pass filter. Device
remains in current state.

3. PORST low pulse is generating a reset:

• a) PORST low but initially filtered during at least W

. Device remains

FRST

initially in current state.

• b) PORST potentially filtered until W

NFRST

. Device state is unknown. It may
either be reset or remains in current state depending on extra condition
(temperature, voltage, device).

• c) PORST asserted for longer than W

NFRST

. Device is under reset.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 19

V

PORST

V

IL

V

IH

V

DD

filtered by

hyst er esi s

filtered by

lowp ass filter

W

FRST

W

NFRST

filtered by

lowp ass filter

W

FRST

unknown reset

state

device under hardware reset

internal

reset

1 2 3a 3b 3c

V

HYS

Reset pad (PORST, RESET) electrical characteristics

Figure 7. Noise filtering on reset signal

Table 12. Reset electrical characteristics

Symbol Parameter Conditions Value

Min Typ Max

VIH Reset Input high level TTL 3.5 V < VDD_HV_IO < 5.5 V 2.0 — V

VIL Reset Input low level TTL 3.5 V < VDD_HV_IO < 3.6 V VSS - 0.3 — 0.6 V

4.5 V < VDD_HV_IO < 5.5 V VSS - 0.3 — 0.8

V

HYS

Input hysteresis TTL 3.5 V < VDD_HV_IO < 5.5 V 300 — — mV

Reset
V

IH

PORST
V

IL

Input high level CMOS 3.5 V < VDD_HV_IO < 5.5 V 0.65 *

V

DD_HV_IO

Input low level CMOS 3.5 V < VDD_HV_IO < 5.5 V VSS - 0.3 — 0.35 *

PORST
V

HYS

PORST
V

DD_POR

Input hysteresis CMOS 3.5 V < VDD_HV_IO < 5.5 V 0.1 *

V

DD_HV_IO

Minimum supply for strong pulldown

— — — 1.2 V

activation

1

DD_HV_IO

Unit

+

0.3

— V

DD_HV_IO

+

0.3

V

DD_HV_IO

— — mV

V

V

V

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

Table continues on the next page...

20 NXP Semiconductors

Reset pad (PORST, RESET) electrical characteristics

Table 12. Reset electrical characteristics (continued)

Symbol Parameter Conditions Value

Min Typ Max

I

OL_R

|I

|

WPU

Reset

|I

|

WPD

PORST

W

FRST

W

NFRST

W

FNMI

W

NFNMI

Strong pull-down current

Weak pull-up current absolute value RESET pin

Weak pull-down current absolute
value

PORST and RESET input filtered
pulse

PORST and RESET input not
filtered pulse

ESR1 input filtered pulse — — — 20 ns
ESR1 input not filtered pulse — 400 — — ns

2

Device under power-on reset
VOL = 0.35 * V

DD_HV_IO

14 — — mA

3.5 V < VDD_HV_IO < 3.6 V
Device under power-on reset
VOL = 0.35 * V

DD_HV_IO

35 — —

4.5 V < VDD_HV_IO < 5.5 V
30 — — μA

VIN = VIH = 0.65 * V

DD_HV_IO

4.5 V < VDD_HV_IO < 5.5 V

RESET pin
VIN = VIH = 0.65 * V

DD_HV_IO

18 — —

3.5 V < VDD_HV_IO < 3.6 V

RESET pin
VIN = VIL = 0.35 * V

DD_HV_IO

— — 120

4.5 V < VDD_HV_IO < 5.5 V

RESET pin
VIN = VIL = 0.35 * V

DD_HV_IO

— — 80

3.5 V < VDD_HV_IO < 3.6 V

PORST pin
VIN = VIH = 0.65 * V

DD_HV_IO

— — 120 μA

4.5 V < VDD_HV_IO < 5.5 V

PORST pin
VIN = VIH = 0.65 * V

DD_HV_IO

— — 80

3.5 V < VDD_HV_IO < 3.6 V

PORST pin
VIN = VIL = 0.35 * V

DD_HV_IO

30 — —

4.5 V < VDD_HV_IO < 5.5 V

PORST pin
VIN = VIL = 0.35 * V

DD_HV_IO

18 — —

3.5 V < VDD_HV_IO < 3.6 V

— — — 500 ns

— 2000 — — ns

1

Unit

1. An external 4.7 KOhm pull-up resistor is recommended to be used with the PORST and RESET pins for fast negation of
the signals.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 21

PLL0

PLL1

RCOSC

XOSC

PLL0_PHI0

PLL0_PHI1

PLL1_PHI0

Oscillator and FMPLL

2. Strong pull-down is enabled during power up / phase0 on both pads but after that a weak pull-down is enabled on PORST
and a weak pull-up is enabled on RESET.

10 Oscillator and FMPLL

Two on-chip PLLs, the peripheral clock and reference PLL (PLL0), and the frequency
modulated system PLL (PLL1) generate the system and auxiliary clocks from the
external oscillator.

Figure 8. PLL integration

Table 13. PLL0 electrical characteristics

Symbol Parameter Conditions

Min Typ Max

f

PLL0IN

Δ

PLL0IN

f

PLL0VCO

f

PLL0PHI0

t

PLL0LOCK

|

Δ

PLL0PHI1SPJ

Δ

PLL0LTJ

PLL0 input clock
PLL0 input clock duty cycle
PLL0 VCO frequency — 600 — 1250 MHz
PLL0 output clock PHI0 — 4.762 — 400 MHz
PLL0 lock time — — — 110 µs
PLL0_PHI1 single period jitter
f

= 20 MHz (resonator)

PLL0IN

|

PLL0 output long term jitter
f

= 20 MHz (resonator), VCO

PLL0IN

frequency = 800 MHz

1

1

— 8 — 40 MHz
— 40 — 60 %

f

PLL0PHI1

= 40 MHz, 6-

— — 300

sigma

2

10 periods accumulated

–250 — 250 ps
jitter (80 MHz frequency),
6-sigma pk-pk

16 periods accumulated

–300 — 300 ps
jitter (50 MHz frequency),
6-sigma pk-pk

long term jitter

–650 — 650 ps
(< 1MHz frequency), 6-

sigma pk-pk

I

PLL0

PLL0 consumption FINE LOCK state — — 5 mA

1. PLL0IN clock retrieved directly from either internal RCOSC or external FXOSC clock. Input characteristics are granted
when using internal RCOSC or external oscillator is used in functional mode.

Value

Unit

2

ps

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

22 NXP Semiconductors

Oscillator and FMPLL

2. V

noise due to application in the range V

DD_LV

= 1.25V (+/-5%) with frequency below PLL bandwidth (40 KHz) will be

DD_LV

filtered.

Table 14. FMPLL1 electrical characteristics

Symbol Parameter Conditions

Min Typ Max

f

PLL1IN

Δ

PLL1IN

f

PLL1VCO

f

PLL1PHI0

t

PLL1LOCK

f

PLL1MOD

|δ

PLL1MOD

PLL1 input clock
PLL1 input clock duty cycle
PLL1 VCO frequency — 600 — 1250 MHz
PLL1 output clock PHI0 — 4.762 — 200 MHz
PLL1 lock time — — — 100 µs
PLL1 modulation frequency — — — 250 kHz

| PLL1 modulation depth (when enabled) Center spread 0.25 — 2 %

1

1

— 38 — 78 MHz
— 35 — 65 %

Down spread 0.5 — 4 %

|

Δ

PLL1PHI0SPJ

I

PLL1

PLL1_PHI0 single period peak to peak
jitter

f

PLL1PHI0

= 200 MHz, 6-

sigma pk-pk

— — 500

|

PLL1 consumption FINE LOCK state — — 6 mA

1. PLL1IN clock retrieved directly from either internal PLL0 or external XOSC clock. Input characteristics are granted when
using internal PLL0 or external oscillator is used in functional mode.

2. 1.25V +/-5%, application noise below 40kHz at V

pin - no frequency modulation

DD_LV

Value

Unit

2

ps

All oscillator specifications are valid for V

DD_HV_IO_JTAG

Table 15. XOSC External Oscillator electrical specifications

Symbol Parameter Conditions

f

XTAL

t

cst

t

rec

V

IHEXT

V

ILEXT

C

S_EXTAL

C

S_XTAL

g

Crystal Frequency Range

Crystal start-up time
Crystal recovery time
EXTAL input high voltage

(External Reference)
EXTAL input low voltage

(External Reference)
Total on-chip stray capacitance

on EXTAL pin

Total on-chip stray capacitance
on XTAL pin

m

Oscillator Transconductance TJ = -40 °C to 150

6

6

1

16MHz < freq < 40MHz (at present, freq =

20M and 40M have been validated, but still

needs to be carried out for freq = 16MHz)

2, 3

4

5

TJ = 150 °C, 20 MHz ≤ f ≤ 40 MHz — 5 ms

V

= 0.28 * V

REF

V

= 0.28 * V

REF

BGA 4.75 5.25 pF

QFP 5.25 5.75

BGA 4.75 5.25 pF

QFP 5.25 5.75

°C

Table continues on the next page...

= 3.0 V to 5.5 V.

Value Unit

Min Max

— 4 8 MHz
— >8 20

>20 40

— — 0.5 ms

DD_HV_IO_JTAG

V

REF

+ 0.6

DD_HV_IO_JTAG

f

≤ 8 MHz 3 13 mA/V

XTAL

f

≤ 20 MHz 9 35

XTAL

— V

— V

-

REF

0.6

V

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 23

Oscillator and FMPLL

Table 15. XOSC External Oscillator electrical specifications

(continued)

Symbol Parameter Conditions

Value Unit

Min Max

f

≤ 40 MHz 12 43

XTAL

V

EXTAL

I

XTAL

Oscillation Amplitude on the
EXTAL pin after startup

XTAL current7,

8

7

TJ = –40 °C to 150

°C

TJ = –40 °C to 150

0.5 1.6 V

— 14 mA

°C

1. The range is selectable by UTEST miscellaneous DCF clients XOSC_LF_EN and XOSC_EN_40MHZ.

2. This value is determined by the crystal manufacturer and board design.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value.

5. This parameter is guaranteed by design rather than 100% tested.

6. See crystal manufacturer's specification for recommended load capacitor (CL) values.The external oscillator requires
external load capacitors when operating from 8 MHz to 16 MHz. Account for on-chip stray capacitance (C

S_EXTAL/CS_XTAL

and PCB capacitance when selecting a load capacitor value. When operating at 20 MHz/40 MHz, the integrated load
capacitor value is selected via S/W to match the crystal manufacturer's specification, while accounting for on-chip and PCB
capacitance. The capacitance on “EXTAL” and “XTAL” by internal capacitance array is controlled by the XOSC LOAD CAP
SEL field of the UTEST Miscellaneous DCF client. See the DCF Records chapter of the Reference Manual.

7. Amplitude on the EXTAL pin after startup is determined by the ALC block, i.e., the Automatic Level Control Circuit. The
function of the ALC is to provide high drive current during oscillator startup, but reduce current after oscillation in order to
reduce power, distortion, and RFI, and to avoid overdriving the crystal. The operating point of the ALC is dependent on the
crystal value and loading conditions.

8. IXTAL is the oscillator bias current out on the XTAL pin with both EXTAL and XTAL pins grounded. This is the maximum
current during startup of the oscillator. The current after oscillation is typically in the 2-3 mA range and is dependant on the
load and series resistance of the crystal. Test circuit is shown in the figure below.

)

Table 16. Selectable load capacitance

load_cap_sel[4:0] from DCF record Capacitance on EXTAL (C

00000 1.0
00001 2.0
00010 2.9
00011 3.8
00100 4.8
00101 5.7
00110 6.6
00111 7.5
01000 8.5
01001 9.4
01010 10.3
01011 11.2
01100 12.2
01101 13.1
01110 14.0

Table continues on the next page...

EXTAL

)/XTAL (C

XTAL

)

, 1, 2

(pF)

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

24 NXP Semiconductors

V

A

I

XTAL

Bias

XTAL

EXTAL

VSSOSC

VSS

Tester

PCB
GND

Current

Comparator

OFF

Z = R + j

L

Conditions

V
V
ALC INACTIVE

EXTAL
XTAL

=0 V

=0 V

V

ALC

DDOSC

Oscillator and FMPLL

Table 16. Selectable load capacitance (continued)

load_cap_sel[4:0] from DCF record Capacitance on EXTAL (C

EXTAL

)/XTAL (C

01111 15.0

10000-11111 N/A

1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values
vary ±12% across process, 0.25% across voltage, and no variation across temperature.

2. Values in this table do not include the internal stray capacitances C

xtal/Cextal

.

XTAL

)

, 1, 2

(pF)

Figure 9. Test circuit

Table 17. Internal RC Oscillator electrical specifications

Value

Symbol Parameter Conditions

f

Target

δf

var_noT

IRCOSC target frequency — — 16 — MHz
IRC frequency variation without

T < 150 °C –8 — 8 %

temperature compensation

δf

var_T

IRC frequency variation with

T < 150 °C –3 — 3 %

temperature compensation

δf

var_SW

δf

TRIM

T

start_noT

IRC software trimming accuracy Trimming

temperature
IRC software trimming step — — +40/-48 — kHz
Startup time to reach within fvar_noT Factory trimming

already applied

T

start_T

Startup time to reach within f

Table continues on the next page...

var_T

Factory trimming

already applied

Min Typ Max

–1 — 1 %

— — 5 µs

— — 120 µs

NXP Semiconductors 25

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

Unit

ADC modules

Table 17. Internal RC Oscillator electrical specifications (continued)

Symbol Parameter Conditions

I

AVDD5

I

DVDD12

Current consumption on 5 V power
supply

Current consumption on 1.2 V power
supply

After T

After T

start_T

start_T

Min Typ Max

— — 400 µA

— — 175 µA

Value

11 ADC modules

This device's analog sub-system contains a total of four independent 12-bit Successive
Approximation (SAR) ADCs and three independent 16-bit Sigma-Delta (S/D) ADCs.

11.1

The following table provides the current specifications for the analog input pad weak
pull-up and pull-down, and the resistance for the analog input bias/diagnostic pull up/
down.

ADC input description

Unit

Table 18. Analog Input Leakage and Pull-Up/Down DC electrical characteristics

Symbol Parameter Conditions Value Unit

Min Typ Max

ILK_AD Analog input leakage

current

RPUPD Analog input bias/

diagnostic pull up/down
resistance

ΔPUPD RPUPD pull up/down

resistance mismatch

Input channel off

4.5V < V
V

V
V
200KΩ

3.0V < V
100KΩ

3.0V < V
5KΩ

3.0V < V

3.0V < V

DD_HV_IO

SS_HV_ADV_SAR
DD_HV_ADV_SAR

SS_HV_ADV_SD

DD_HV_IO

DD_HV_IO

DD_HV_IO

DD_HV_IO

-200 — 200 nA

< 5.5V

< VIN <

< VIN < V

DD_HV_ADV_SD

130 200 280 KΩ

< 5.5V

65 100 140

< 5.5V

1.4 5 8.8
< 5.5V
< 5.5V — — 5 %

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

26 NXP Semiconductors

(2

)

(1)

(3

)

(4)

(5)

Offset Error OSE

Offset Error OSE

Gain Error GE

1 LSB (ideal)

V

in(A)

(LSB

ideal

)

(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) Differential non-linearity error (DNL)
(4) Integral non-linearity error (INL)
(5) Center of a step of the actual transfer

curve

code out

4095
4094

4093
4092

4091
4090

5
4
3
2

1

0

7
6

1 2 3 4 5 6 7 4089 4090 4091 4092 4093 4094 4095

1 LSB ideal =(VrefH-VrefL)/ 4096 =

3.3V/ 4096 = 0.806 mV
Total Unadjusted Error

TUE = +/- 6 LSB = +/- 4.84mV

ADC modules

11.2 SAR ADC

The device provides a 12-bit Successive Approximation Register (SAR) Analog-to­Digital Converter.

Figure 10. ADC characteristics and error definitions

NXP Semiconductors 27

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

R

F

C

F

R

S

R

L

R

SW1

C

P2

V

DD_HV_IO

Sampling

Source Filter Current Limiter

EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME

R

S

Source Impedance

R

F

Filter Resistance

C

F

Filter Capacitance

R

L

Current Limiter Resistance

R

SW1

Channel Selection Switch Impedance

R

AD

Sampling Switch Impedance

C

P

Pin Capacitance (two contributions, CP1and C

P2

)

C

S

Sampling Capacitance

C

P1

R

AD

Channel

Selection

V

A

C

S

ADC modules

11.2.1 Input equivalent circuit and ADC conversion characteristics

Figure 11. Input equivalent circuit

Table 19. ADC conversion characteristics

1

Min Typ Max Unit

Symbol Parameter Conditions

, 2

f

CK

ADC Clock frequency (depends

— 20 — 80 MHz
on ADC configuration) (The duty
cycle depends on AD_CK

3

frequency.)

f

s

t

sample

t

conv

, 6

C

S

6

C

P1

6

C

P2

6

R

SW1

6

R

AD

INL Integral non-linearity — –2 — 2 LSB

Sampling frequency — — — 1.00 MHz
Sample time
Conversion time

4

5

— 250 — — ns

80 MHz 700 — — ns
ADC input sampling capacitance — — 3 5 pF
ADC input pin capacitance 1 — — — 5 pF
ADC input pin capacitance 2 — — — 0.8 pF
Internal resistance of analog

source

Internal resistance of analog
source

V

range = 4.5 to 5.5 V — — 0.3 kΩ

REF

V

range = 3.0 to 3.6 V — — 875 Ω

REF

— — — 825 Ω

DNL Differential non-linearity — –1 — 1 LSB

OFS

GNE

7

7

Input (double ADC

channel)

Offset error — –6 — 6 LSB
Gain error — –6 — 6 LSB
Max leakage 150 °C — — 300 nA

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

28 NXP Semiconductors

ADC modules

Table 19. ADC conversion characteristics (continued)

Symbol Parameter Conditions

SNR Signal-to-noise ratio V

SNR Signal-to-noise ratio V

THD Total harmonic distortion @ 125 kHz 65 70 — dB

8

ENOB

SINAD Signal-to-noise and distortion Fin < 125 kHz (6.02*ENOB)+1.76 dB

TUE

IS1WINJ

TUE

IS1WWINJ

I

DD_VDDA

I

DD_VDDR

BG_REF

, 9

V

Effective number of bits Fin < 125 kHz 10.5 — — bits

Total unadjusted error for
IS1WINJ

Total unadjusted error for
IS1WWINJ

Maximum operating current on
VDDA

Maximum operating current on
VREF

Band gap reference for self test Trimmed,

= 3.3 V, Fin ≤ 125

REF

kHz

= 5.0 V, Fin ≤ 125

REF

kHz

Without current injection –6 — 6 LSB

Without current injection –6 — 6 LSB

Tj = 150C VDD_LV_COR

= 1.32 V

Tj = 150C VDD_LV_COR

= 1.32 V

INPSAMP=0xFF

1

Min Typ Max Unit

66 — — dB

68 — — dB

— 3.7 5 mA

— 150 600 μA

1.164 —

10

1.236 V

1. V

DD_HV_IO

V

AREF

2. SAR ADC performance is not guaranteed when IRC is used as clock source for PLL0 to generate SAR ADC clock.

3. AD_CK clock is always half of the ADC module input clock defined via the auxiliary clock divider for the ADC.

4. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal
resistance of the analog source must allow the capacitance to reach its final voltage level within t
sample time t
clock t

5. This parameter does not include the sample time t
load the result register with the conversion result.

6. See the above figure.

7. Subject to change with additional -40°C characterization on final silicon version.

8. Below 4.5V, ENOB - 9.5b, THD- 60dB at Fin= 125KHz

9. Band gap reference only applies to Cut 2 silicon.

10. Minimum and maximum values are typical +/-3%

= 3.3 V -5%,+10%, TJ = –40 to +150 °C, unless otherwise specified, and analog input voltage from V

, changes of the analog input voltage have no effect on the conversion result. Values for the sample

sample

depend on programming.

sample

, but only the time for determining the digital result and the time to

sample

sample

AGND

. After the end of the

NOTE

• For spec complaint operation, do not expose clock sources,
including crystal oscillator, IRC, PLL0, and PLL1 on the
CLKOUT pads while the SAR ADC is converting.

• The ADC performance specifications are not guaranteed if
two or more ADCs simultaneously sample the same shared
channel.

to

11.3

S/D ADC

The SD ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps
maximum output rate.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 29

ADC modules

Functional operating conditions are given in the DC electrical specifications. Absolute
maximum ratings are stress ratings only, and functional operation at the maxima is not
guaranteed. Stress beyond the listed maxima may affect device reliability or cause
permanent damage to the device.

Table 20. SDn ADC electrical specification

Symbol Parameter Conditions

V

V

IN_PK2PK

IN

ADC input signal — 0 — V

1

Input range peak to
peak

V

IN_PK2PK

, 3

V

INM

= V

INP

2

–

Single ended.
V

= V

INM

Single ended.
V

= 0.5*V

INM

SS_HV_ADR_SD

DD_HV_ADR_SD

Min Typ Max

DD_HV_

ADV_SD

V

DD_HV_ADR_SD

±0.5*V

DD_HV_ADR_SD

/GAIN

GAIN = 1
Single ended.

Value

V

= 0.5*V

INM

DD_HV_ADR_SD

±V

DD_HV_ADR_SD

/GAIN
GAIN = 2,4,8,16
Differential

f

ADCD_M

f

ADCD_S

±V

0 < VIN < V

DD_HV_IO_MAIN

DD_HV_ADR_SD

S/D clock frequency TJ < 150 °C 4 14.4 16 MHz
Conversion rate TJ < 150 °C — — 333 ksps

/GAIN

— Oversampling ratio Internal modulator 24 — 256 —

RESOLUTION S/D register resolution 2's complement notation 16

GAIN ADC gain Defined through ADC_SD[PGA] register.

1 — 16 —

4

Only integer power of 2 are valid gain.

|δ

| Absolute value of the

GAIN

ADC gain error

5

Before calibration (applies to gain
settings =1)

After calibration
Δ V

DD_HV_ADR_SD

Δ V

DD_HV_ADV_SD

6

< 5%
< 10%

— — 1 %

— — 0.1 %

TJ < 50 °C
After calibration
Δ V

DD_HV_ADR_SD

Δ V

DD_HV_ADV_SD

6

< 5%
< 10%

— — 0.2 %

TJ < 150 °C

V

SNR

OFFSET

DIFF150

Conversion offset Before calibration

(applies to all gain settings – 1, 2, 4, 8,

16)
After calibration

, 7

Signal to noise ratio in
differential mode 150
ksps output rate

4.5 < V
V

DD_HV_ADR_D

6

DD_HV_ADV_SD

= V

DD_HV_ADV_D

< 5.5

— 10*

(1+1/
gain)

— — 5 mV

7

78 — — dB

Table continues on the next page...

Unit

V

V

bit

20 mV

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

30 NXP Semiconductors

Table 20. SDn ADC electrical specification (continued)

ADC modules

Symbol Parameter Conditions

GAIN = 1
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 4
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 16
TJ < 150 °C

DIFF333

7

Signal to noise ratio in
differential mode 333
ksps output rate

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

SNR

GAIN = 1
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 4
TJ < 150 °C

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

Value

Min Typ Max

7

7

7

7

7

7

7

75 — —

72 — —

69 — —

65 — —

72 — — dB

69 — —

66 — —

Unit

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 31

ADC modules

Table 20. SDn ADC electrical specification (continued)

Symbol Parameter Conditions

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 16
TJ < 150 °C

SE150

7

Signal to noise ratio in
single ended mode 150
ksps output rate

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

SNR

GAIN = 1
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 4
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_DS
DD_HV_ADV_SD

V
GAIN = 16
TJ < 150 °C

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

Value

Min Typ Max

7

7

7

7

7

7

7

63 — —

60 — —

72 — — dB

69 — —

66 — —

63 — —

55 — —

Unit

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

32 NXP Semiconductors

Table 20. SDn ADC electrical specification (continued)

ADC modules

Symbol Parameter Conditions

THD

DIFF150

Total Harmonic
Distortion in differential
mode 150 ksps output
rate

4.5 < V
V

DD_HV_ADR_D

GAIN = 1
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 4
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 16
TJ < 150 °C

THD

DIFF333

Total Harmonic
Distortion in differential
mode 333 ksps output
rate

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 1
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

Table continues on the next page...

DD_HV_ADV_SD

= V

DD_HV_ADV_D

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

Value

Min Typ Max

7

7

7

7

7

7

7

7

65 — — dB

68 — —

74 — —

80 — —

80 — —

65 — — dB

68 — —

74 — —

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 33

ADC modules

Table 20. SDn ADC electrical specification (continued)

Symbol Parameter Conditions

GAIN = 4
TJ < 150 °C

4.5 < V

DD_HV_ADV_SD

V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V

DD_HV_ADV_SD

V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 16
TJ < 150 °C

THD

SE150

Total Harmonic
Distortion in single
ended mode 150 ksps
output rate

4.5 < V

DD_HV_ADV_SD

V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 1
TJ < 150 °C

4.5 < V

DD_HV_ADV_SD

V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V

DD_HV_ADV_SD

V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 4
TJ < 150 °C

4.5 < V

DD_HV_ADV_SD

V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V

DD_HV_ADV_SD

V

DD_HV_ADR_DS
DD_HV_ADV_SD

V
G

= 16

AIN

TJ < 150 °C

Value

Unit

< 5.5

Min Typ Max

7

80 — —

=

7

< 5.5

77 — —

=

7

< 5.5

68 — — dB

=

7

< 5.5

68 — —

=

7

< 5.5

68 — —

=

7

< 5.5

68 — —

=

7

< 5.5

68 — —

=

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

34 NXP Semiconductors

Table 20. SDn ADC electrical specification (continued)

ADC modules

Symbol Parameter Conditions

SINAD

DIFF150

Signal to Noise
Distortion Ratio in
differential mode 150
ksps output rate

4.5 < V
V

DD_HV_ADR_D

GAIN = 1
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 4
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 16
TJ < 150 °C

SINAD

DIFF333

Signal to Noise
Distortion Ratio in
differential mode 333
ksps output rate

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 1
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

Table continues on the next page...

DD_HV_ADV_SD

= V

DD_HV_ADV_D

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

Value

Min Typ Max

7

7

7

7

7

7

7

7

72 — — dB

72 — —

69 — —

68.8 — —

64.8 — —

66 — — dB

66 — —

63 — —

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 35

ADC modules

Table 20. SDn ADC electrical specification (continued)

Symbol Parameter Conditions

GAIN = 4
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 16
TJ < 150 °C

SINAD

SE150

Signal to Noise
Distortion Ratio in single
ended mode 150 ksps
output rate

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 1
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 2
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 4
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_SD

V

DD_HV_ADV_SD

GAIN = 8
TJ < 150 °C

4.5 < V
V

DD_HV_ADR_DS
DD_HV_ADV_SD

V
G

= 16

AIN

TJ < 150 °C

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

DD_HV_ADV_SD

=

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

< 5.5

Value

Min Typ Max

7

7

7

7

7

7

7

62 — —

59 — —

66 — — dB

66 — —

63 — —

62 — —

54 — —

Unit

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

36 NXP Semiconductors

Table 20. SDn ADC electrical specification (continued)

ADC modules

Symbol Parameter Conditions

SFDR Spurious free dynamic

Any GAIN 60 — — dB

Min Typ Max

range

Value

Z

DIFF

Differential input
impedance

8, 9

GAIN = 1 1000 1250 1500 kΩ
GAIN = 2 600 800 1000
GAIN = 4 300 400 500
GAIN = 8 200 250 300
GAIN = 16 200 250 300

Z

CM

Common Mode input
impedance

9, 10

GAIN = 1 1400 1800 2200 kΩ
GAIN = 2 1000 1300 1600
GAIN = 4 700 950 1150
GAIN = 8 500 650 800
GAIN = 16 500 650 800

ΔV

R

BIAS

INTCM

V

BIAS

Bare bias resistance — 110 144 180 kΩ
Common Mode input

reference voltage

11

Bias voltage — — VDD_

— –12 — +12 %

— V

HV_

ADR_S

D/2

δV

BIAS

CMRR Common mode

Bias voltage accuracy — –2.5 — +2.5 %

— 55 — — dB

rejection ratio

— Anti-aliasing filter External series resistance — — 20 kΩ

Filter capacitances 220 — — pF

δ

RIPPLE

Pass band ripple

— Stop band attenuation [0.5 * f

δ

GROUP

Group delay Within pass band – Tclk is f

12

0.333 * f

1.0 * f

ADCD_S]

[1.0 * f

1.5 * f

ADCD_S]

[1.5 * f

2.0 * f

ADCD_S

[2.0 * f

2.5 * f

ADCD_S

[2.5 * f

ADCD_S

ADCD_S

ADCD_S

ADCD_S

ADCD_S

ADCD_S

,

,

,

]

,

]

, f

ADCD_M

–1 — 1 %
40 — — dB

45 — —

50 — —

55 — —

/2] 60 — —

/ 2 — — — —

ADCD_M

OSR = 24 — — 235.5 Tclk
OSR = 28 — — 275
OSR = 32 — — 314.5
OSR = 36 — — 354

Unit

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 37

ADC modules

Table 20. SDn ADC electrical specification (continued)

Symbol Parameter Conditions

OSR = 40 — — 393.5
OSR = 44 — — 433
OSR = 48 — — 472.5
OSR = 56 — — 551.5
OSR = 64 — — 630.5
OSR = 72 — — 709.5
OSR = 75 — — 696
OSR = 80 — — 788.5
OSR = 88 — — 867.5
OSR = 96 — — 946.5
OSR = 112 — — 1104.5
OSR = 128 — — 1262.5
OSR = 144 — — 1420.5
OSR = 160 — — 1578.5
OSR = 176 — — 1736.5
OSR = 192 — — 1894.5
OSR = 224 — — 2210.5
OSR = 256 — — 2526.5
Distortion within pass band –0.5/

f

HIGH

High pass filter 3dB

Enabled — 10e-5*

frequency

t

STARTUP

Start-up time from

— — — 100 µs

power down state

t

LATENCY

Latency between input

HPF = ON — — δ

data and converted data
when input mux does

13

HPF = OFF — — δ
Analog inputs are muxed
HPF = ON

t

SETTLING

note change

Settling time after mux
change

HPF = OFF — — 2*δ

t

ODRECOVERY

Overdrive recovery time After input comes within range from

saturation
HPF = ON
HPF = OFF — — 2*δ

Table continues on the next page...

Value

Min Typ Max

— +0.5/

f

ADCD_S

f

ADCD_S

f

f

— — 2*δ

GROUP

3*f

GROUP

2*f

— — 2*δ

GROUP

f

ADCD_S

— —

GROUP

+

ADCD_S

GROUP

+

ADCD_

S

+

ADCD_

S

+

ADCD_S

GROUP

Unit

—

—

—
—

—

—

—

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

38 NXP Semiconductors

Table 20. SDn ADC electrical specification (continued)

Temperature sensor

Symbol Parameter Conditions

C

S_D

S/D ADC sampling

GAIN = 1, 2, 4, 8 — — 75*GAI

capacitance after

14

GAIN = 16 — — 600 fF

ADCD enabled — 2.5 8 mA

I

BIAS

I

ADV_D

sampling switch

Bias consumption At least 1 ADCD enabled — — 3.5 mA
ADCD supply

Min Typ Max

N

Unit

fF

consumption

Value

ΣI

ADR_D

Reference current for

ADCD enabled — 10 50 µA

one SDADC

1. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the
signal will only be 'clipped'.

2. VINP is the input voltage applied to the positive terminal of the SD ADC.

3. VINM is the input voltage applied to the negative terminal of the SD ADC.

4. For Gain=16, SDADC Resolution is 15 bit.

5. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.

6. Calibration of gain is possible when gain = 1. Offset Calibration should be done with respect to 0.5*V
differential "differential mode" and single ended mode with negative input=0.5*V

DD_HV_ADR_SD

". Offset Calibration should

DD_HV_ADR_SD

for

be done with respect to 0 for "single ended mode with negative input=0". Both Offset and Gain Calibration is guaranteed
for +/-5% variation of V

DD_HV_ADR_SD

7. S/D ADC is functional in the range 3.6V < V

, +/-10% variation of V

DD_HV_ADV_SD

DD_HV_ADV_SD

, +/-50 C temperature variation.

< 4.5V and 3.0V < V

DD_HV_ADR_SD

< 4.5 V, SNR paramter

degrades by 9 dB.

8. Input impedance in differential mode ZIN = Z

9. Input impedance given at f
(f

ADCD_M

) = (16 MHz / f

ADCD_M

= 16 MHz. Impedance is inversely proportional to SDADC clock frequency. Z

ADCD_M

) * Z

DIFF

10. Input impedance in single-ended mode ZIN = (2 * Z

11. V

is the Common Mode input reference voltage for the SDADC. It has a nominal value of (V

INTCM

, ZCM (f

DIFF

ADCD_M

) = (16 MHz / f

* ZCM) / (Z

DIFF

ADCD_M

+ ZCM)

DIFF

) * ZCM.

RH_SD

- V

RL_SD

DIFF

) / 2.

12. The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.873 dB.

13. Propagation of the information from the pin to the register CDR[CDATA] and flags SFR[DFEF], SFR[DFFF] is given by the

different modules that need to be crossed: delta/sigma filters, high pass filter, fifo module, clock domain synchronizers.
The time elapsed between data availability at pin and internal S/D module registers is given by the following formula:
REGISTER LATENCY = tLATENCY + 0.5/fADCD_S + 2 (~+1)/fADCD_M + 2(~+1)fPBRIDGEx_CLK where fADCD_S is
the frequency of the sampling clock, fADCD_M is the frequency of the modulator, and fPBRIDGEx_CLK is the frequency
of the peripheral bridge clock feeds to the ADC S/D module. The (~+1) symbol refers to the number of clock cycles
uncertainty (from 0 to 1 clock cycle) to be added due to resynchronization of the signal during clock domain crossing.
Some further latency may be added by the target module (core, DMA, interrupt) controller to process the data received
from the ADC S/D module.

14. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before

sampling switch.

12 Temperature sensor

The following table describes the temperature sensor electrical characteristics.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 39

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Table 21. Temperature sensor electrical characteristics

Symbol Parameter Conditions

— Junction temperature monitoring

range

T

T

SENS

ACC

Sensitivity — — 5.18 — mV/°C
Accuracy — –7 — 7 °C

—

Min Typ Max

–40 — 150 °C

Value

Unit

13 LVDS fast asynchronous serial transmission (LFAST) pad

electrical characteristics

The LFAST pad electrical characteristics apply to both the LFAST and high-speed debug
serial interfaces on the device. The same LVDS pad is used for the Microsecond Channel
(MSC) and DSPI LVDS interfaces, with different characteristics given in the following
tables.

13.1

LFAST interface timing diagrams

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

40 NXP Semiconductors

Signal excursions above this level NOT allowed

Max. common mode input at RX

Maximum Differential Voltage

TX common mode

T = 1 / F

= 1.2 V +/- 10%

285 mV p-p (LFAST)
400 mV p-p (MSC/DSPI)

150 mV p-p (MSC/SIPI)

100 mV p-p (LFAST)

Voltage =

V

Minimum Differential

Minimum Data Bit Time

Data Bit Period

Min. common mode input at RX

Signal excursions below this level NOT allowed

Opening =

"No-Go" Area

0.55 * T (LFAST)

0.50 * T (MSC/SIPI)

DATA

VOD

VOD

1743 mV

1600 mV

150 mV

0 V

I

I I

I

OS

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Figure 12. LFAST timing definition

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 41

Data Valid

Ifast_pwr_down

Differential
Data Lines

pad_p/pad_n

TX

H

L

t

PD2NM_TX

Differential

pad_p/pad_n

Data Lines

TX

rise

fall

90%

10%

V

V

t

t

IH

IL

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Figure 13. Power-down exit time

13.2

The following table contains the electrical characteristics for the LFAST interface.
The LVDS pad electrical characteristics in this table apply to both the LFAST and High-

speed Debug (HSD) LVDS pad, and the MSC/DSPI LVDS pad except where noted in the
conditions.

All LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

42 NXP Semiconductors

LFAST and MSC /DSPI LVDS interface electrical characteristics

Figure 14. Rise/fall time

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Table 22. LVDS pad startup and receiver electrical characteristics

Symbol Parameter Conditions

Value

Min Typ Max

t

PD2NM_TX

t

SM2NM_TX

t

PD2NM_RX

t

PD2SM_RX

I

LVDS_BIAS

Transmitter startup time (power
down to normal mode)

1

Transmitter startup time (sleep
mode to normal mode)

2

Receiver startup time (power down
to normal mode)

3

Receiver startup time (power down
to sleep mode)

4

—

Not applicable to the MSC/
DSPI LVDS pad

—

Not applicable to the MSC/
DSPI LVDS pad

— 0.4 0.55 µs

— 0.2 0.5 µs

— 20 40 ns

— 20 50 ns

LVDS bias current consumption Tx or Rx enabled — — 0.95 mA

TRANSMISSION LINE CHARACTERISTICS (PCB Track)

Z

Z

0

DIFF

Transmission line characteristic
impedance

Transmission line differential
impedance

—

—

47.5 50 52.5 Ω

95 100 105 Ω

RECEIVER

V

ICOM

Common mode voltage — 0.15

5

— 1.6

6

|ΔVI| Differential input voltage — 100 — — mV

V

HYS

R

IN

C

IN

I

LVDS_RX

Input hysteresis — 25 — — mV
Terminating resistance V

Differential input capacitance

7

DD_HV_IO

V

DD_HV_IO

— — 3.5 6.0 pF

= 5.0 V ± 10% 80 100 120 Ω
= 3.3 V ± 10% 80 115 150 Ω

Receiver DC current consumption Enabled — — 0.5 mA

Unit

V

1. Total transmitter startup time from power down to normal mode is t

STRT_BIAS

+ t

PD2NM_TX

+ 2 peripheral bridge clock
periods. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal
capacitance values.

2. Total transmitter startup time from sleep mode to normal mode is t

SM2NM_TX

+ 2 peripheral bridge clock periods. Bias block
remains enabled in sleep mode. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40
°C to 150 °C.

3. Total receiver startup time from power down to normal mode is t

4. Total receiver startup time from power down to sleep mode is t

STRT_BIAS

PD2SM_RX

+ t

PD2NM_RX

+ 2 peripheral bridge clock periods.

+ 2 peripheral bridge clock periods. Bias block

remains enabled in sleep mode.

5. Absolute min = 0.15 V – (285 mV/2) = 0 V

6. Absolute max = 1.6 V + (285 mV/2) = 1.743 V

7. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.

Table 23. LFAST transmitter electrical characteristics

Symbol Parameter Conditions

f

DATA

V

|VOD| Differential output voltage swing (terminated)

t

Data rate — — — 320 Mbps
Common mode voltage — 1.08 — 1.32 V

OS

Rise/Fall time (10%–90% of swing)

TR

1, 2

3, 4

— 100 200 285 mV
— 0.26 — 1.5 ns

Table continues on the next page...

Min Typ Max

Value

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 43

LVDS fast asynchronous serial transmission (LFAST) pad electrical characteristics

Table 23. LFAST transmitter electrical characteristics (continued)

Symbol Parameter Conditions

C

External lumped differential load capacitance

L

I

LVDS_TX

Transmitter DC current consumption Enabled — — 3.2 mA

1. Valid for maximum data rate f

. Value given is the capacitance on each terminal of the differential pair, as shown in the

DATA

1

V

DD_HV_IO

V

DD_HV_IO

Min Typ Max

= 4.5 V — — 10.0 pF
= 3.0 V — — 8.5

Unit

figure below.

2. Valid for maximum external load CL.

3. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance
values.

4. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

The MSC and DSPI LVDS pad electrical characteristics are based on the application
circuit and typical worst case internal capacitance values given in Figure 14.

All MSC and DSPI LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

Table 24. MSC/DSPI LVDS transmitter electrical characteristics

Value

Symbol Parameter Conditions

Data Rate

f

DATA

V

|

VOD

t

I

LVDS_TX

Data rate — — — 80 Mbps
Common mode voltage — 1.08 — 1.32 V

OS

| Differential output voltage swing (terminated)

Rise/Fall time (10%–90% of swing)

TR

C

External lumped differential load capacitance

L

3, 4

1, 2

3

V

DD_HV_IO

V

DD_HV_IO

— 150 200 400 mV
— 0.8 — 5.7 ns

= 4.5 V — — 40 pF
= 3.0 V — — 30

Transmitter DC current consumption Enabled — — 4.0 mA

Min Typ Max

Value

Unit

1. Valid for maximum data rate f

. Value given is the capacitance on each terminal of the differential pair, as shown in the

DATA

figure below.

2. Valid for maximum external load CL.

3. The LFAST and High-Speed Debug LFAST pad electrical characteristics are based on worst case internal capacitance
values.

4. All LFAST and High-Speed Debug LVDS pad electrical characteristics are valid from -40 °C to 150 °C.

NOTE

For optimum LVDS performance, it is recommended to set the
neighbouring GPIO pads to use Weak Drive.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

44 NXP Semiconductors

LVDS Driver

GPIO Driver

bond

bond

pad

pad

Die

Package

PCB

C

1pF

1pF

100 Ω

C

termination

2.5pF

2.5pF

L

L

GPIO Driver

LFAST PLL electrical characteristics

Figure 15. LVDS pad external load diagram

14

LFAST PLL electrical characteristics

The following table contains the electrical characteristics for the LFAST PLL.
The specifications in this table apply to both the interprocessor bus and debug LFAST

interfaces.

Symbol Parameter Conditions

f

RF_REF

ERR

REF

D

CREF

PN Integrated phase noise (single side band) f

f

VCO

t

LOCK

ΔPER

REF

PLL reference clock frequency — 10 — 26 MHz
PLL reference clock frequency error — –1 — 1 %
PLL reference clock duty cycle — 45 — 55 %

PLL VCO frequency — — 640
PLL phase lock
Input reference clock single period jitter

(peak to peak)

Table 25. LFAST PLL electrical characteristics

2

Table continues on the next page...

RF_REF

f

RF_REF

Single period,

f

RF_REF

Min Nominal Max

= 20 MHz — — –58 dBc
= 10 MHz — — –64

— — — 40 µs

— — 300 ps

= 10 MHz

Value

1

— MHz

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 45

Data Bit Period, T

Eye Jitter

Eye Jitter

TX+

TX-

Aurora LVDS electrical characteristics

Table 25. LFAST PLL electrical characteristics

(continued)

Symbol Parameter Conditions

Long term,

f

= 10 MHz

RF_REF

ΔPER

1. The 640 MHz frequency is achieved with a 10 MHz or 20 MHz reference clock. With a 26 MHz reference, the VCO
frequency is 624 MHz.

2. The time from the PLL enable bit register write to the start of phase locks is maximum 2 clock cycles of the peripheral
bridge clock that is connected to the PLL on the device.

3. Measured at the transmitter output across a 100 Ohm termination resistor on a device evaluation board. Refer to the figure
below.

Output Eye Jitter (peak to peak)

EYE

3

— — 550 — ps

Min Nominal Max

–500 — 500 ps

Value

Unit

Figure 16. LFAST output 'eye' diagram

15

Aurora LVDS electrical characteristics

The following table describes the Aurora LVDS electrical characteristics.
All Aurora electrical characteristics are valid from -40 °C to 150 °C.
All specifications valid for maximum transmit data rate FTX.

46 NXP Semiconductors

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

Table 26. Aurora LVDS electrical characteristics

Symbol Parameter Conditions

Transmitter

F

|V

OD_LVDS

t

TR_LVDS

R

T

L
Z

C

F

|Δ

R

TX

TV_L

Loss

LINE

LINE

AC

RX

VI_L

RV_L

Transmit Data Rate — — — 1.25 Gbps

| Differential output voltage swing

(terminated)
Rise/Fall time (10%–90% of swing) — 60 — — ps
Differential Terminating resistance — 81 100 120 Ω
Transmission Line Loss due to loading

effects

Transmission line length — — — 20 cm
Transmission line characteristic impedance — 45 50 55 Ω
External AC Coupling Capacitance Values are nominal, valid

Receive Data Rate — — — 1.25 GHz

| Differential input voltage — 200 — 1000 mV

Terminating resistance V

2

Transmission line characteristics (PCB track)

Receiver

DD_HV_IO_BD

— 400 600 800 mV

— — — 100

up to ±50%

= 5V ±10% 81 100 120 Ω

Power management PMC POR LVD sequencing

1

Value

Min Typ Max

100 — 270 pF

Unit

3

dB

1. All specifications valid for maximum transmit data rate FTX.

2. The minimum value of 400 mV is only valid for differential resistance (R
voltage swing tracks with the value of R

3. Transimission line loss maximum value is specified for the maximum drive level of the Aurora transmit pad.

16

16.1

Power management PMC POR LVD sequencing

Power management electrical characteristics

V_L

.

) = 99 ohm to 101 ohm. The differential output

V_L

The power management module monitors the different power supplies. It also generates
the internal supplies that are required for correct device functionality. The power
management is supplied by the V

16.1.1

Recommended power transistors

DD_HV_PMC

supply.

The following NPN transistors are recommended for use with the on-chip voltage
regulator controller: ON SemiconductorTM NJD2873. The collector of the external
transistor is preferably connected to the same voltage supply source as the V

DD_HV_PMC

pin.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 47

Power management PMC POR LVD sequencing

The following table describes the characteristics of the power transistors.

Table 27. Recommended operating characteristics

Symbol Parameter Value Unit

h

FE

P

I

CMaxDC

VCE

V

BE

V

D

SAT

C

DC current gain (Beta) 60-550 —
Absolute minimum power dissipation 1.60 W
Maximum DC collector current 2.0 A
Collector to emitter saturation voltage 300 mV
Base to emitter voltage 0.95 V
Minimum voltage at transistor collector 2.5 V

16.1.2 Power management integration

In order to ensure correct functionality of the device, it is recommended to follow the
integration scheme shown below.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

48 NXP Semiconductors

C

HV_PMC

C

HV_FLA

VSS

VDD_HV_FLA

VDD_HV_PMC

RAINIER

VDD_HV_IO

VSS

C

C

HV_ADC_D

VSS

VDD_LV

HV_IO

2

LV

1

VDD_HV_ADV_SD

VSS_HV_ADV_SD

1

One capacitance near each VDD_LV pin

2

One capacitance near each VDD_HV pin

HV_ADC_SAR

VDD_HV_ADV_SAR

VSS_HV_ADV_SAR

n x C

C

Power management PMC POR LVD sequencing

Figure 17. Recommended supply pin circuits

The following table describes the supply stability capacitances required on the device for
proper operation.

Table 28. Device power supply integration

Symbol Parameter Conditions

C

LV

C

HV_PMC

C

HV_IO

C

HV_FLA

C

HV_ADC_SA

R

Minimum V

2, 3

Minimum V
capacitance

Minimum VDD_HV_IO external
capacitance

Minimum V
Minimum V

capacitance

DD_LV

DD_HV_PMC

2, 4

2

DD_HV_FLA

DD_HV_ADV_SAR

, 6

external bulk capacitance

external bulk

external capacitance

external

,

— 4.7 — — µF

— 4.7 — — µF

— 4.7 — — µF

, 5

— 2.0 µF

Table continues on the next page...

1

Value

Min Typ Max

10 — — µF

Unit

NXP Semiconductors 49

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

VDD_HV_PMC

VRC_CTL

VDD_LV

VSS

VRC_CTL capacitor: may or

may not be required

MCU

Mandatory decoupling capacitor

network

C1

The bypass transistor
MUST be operated out

of saturation region.

Power management PMC POR LVD sequencing

Table 28. Device power supply integration (continued)

1

Symbol Parameter Conditions

C

HV_ADC_SD

1. See the above figure for capacitor integration.

2. Recommended X7R or X5R ceramic low ESR capacitors, ±15% variation over process, voltage, temperature, and aging.

3. Each V
capacitance to meet minimum CLV requirement should be placed near the emitter of NPN ballast (if using internal
regulation mode), or it should be evenly distributed across VDD_LV pins (if using external regulation mode).

4. Each V

5. The recommended flash regulator composition capacitor is 1.5µF typical X7R or X5R, with -50% and +35% as min and
max. This puts the min cap at 0.75 µF.

6. For noise filtering it is recommended to add high frequency bypass capacitors of three each 0.1 µF and three each 1nF
between V
have minimum PCB routing between pin/ball and the capacitors.

7. For noise filtering it is recommended to add a high frequency bypass capacitance of 0.1 µF between V
V

SS_HV_ADV_SD

Minimum V
capacitance

pin requires both a 47nF and 0.01µF capacitor for high-frequency bypass and EMC requirements. Remaining

DD_LV

DD_HV_PMC

DD_HV_ADV_SAR

DD_HV_ADV_SD

, 7

pin requires both a 47nF and 0.01µF capacitor for high-frequency bypass and EMC requirements.

and V

.

external

SS_HV_ADV_SAR

. These capacitors need to be placed very close to the MCU pins/balls to

Min Typ Max

1 2.2 — µF

Value

DD_HV_ADV_SD

Unit

and

16.1.3 Regulator example for the NJD2873 transistor

Figure 18. Regulator example

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

50 NXP Semiconductors

+

--

3.3V or Vcollector

VDDIO

Vdd_core

Vrctl

Vref

Lb= 50n, 100n

Cb= 0.6u, 1.4u
ESR= 15m, 150m

Cl= 4u, 14u
ESR= 15m, 150m

Le= 50n, 100n

Lc = 50n, 100n

Cc= 4u, 14u
ESR= 15m, 150m

Beta= 120, 360

ILoad

Power management PMC POR LVD sequencing

16.1.4 Regulator example for the 2SCR574d transistor

Figure 19. Regulator example

16.1.5

Device voltage monitoring

The LVD/HVDs for the device and their levels are given in the following table. Voltage
monitoring threshold definition is provided in the following figure.

NXP Semiconductors 51

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

V

V
V

V

DD_xxx

V

LVD(fall)

HVD TRIGGER

LVD TRIGGER

VDRELEASE

LVD(rise)

t

t

t

VDASSERT

HVD(fall)

HVD(rise)

VDRELEASE

t

VDASSERT

(INTERNAL)

(INTERNAL)

Power management PMC POR LVD sequencing

For V
the die. For other LVD, the IR drop is estimated by multiplying the supply current by 0.5
ohm.

LVD is released after t
asserted t

HVD is released after t
is asserted t

POR085_c1LV internal supply power on

Figure 20. Voltage monitor threshold definition

DD_LV

levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on

temporization when upper threshold is crossed, LVD is

temporization when lower threshold is crossed, HVD

VDASSERT

VDASSERT

VDRELEASE

after detection when lower threshold is crossed.

VDRELEASE

after detection when upper threshold is crossed.

Table 29. Voltage monitor electrical characteristics

Symbol Parameter Conditions

Rising voltage (power up) N/A No Enab.870 920 970 mV

reset

Falling voltage (power down) 850 900 950

Table continues on the next page...

Configuration Value

Trim

Mas

Pow

Min Typ Max

bits

Opt.

k

. Up

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

52 NXP Semiconductors

Table 29. Voltage monitor electrical characteristics (continued)

VDD_STDBY=0 VDD_LV=0 VDD_HV_PMC=0 VDD_HV_IO_MAIN=0 VDD_HV_IO_JTAG=0 VDD_HV_IO_FEC=0 VDD_HV_IO_MSC=0 VDD_HV_ADR_SD=0 VDD_HV_ADV_SD=0 VDD_HV_ADR_SAR=0 VDD_HV_ADV_SAR=0

VDD_STDBY
VDD_LV
VDD_HV_PMC
VDD_HV_IO_MAIN
VDD_HV_IO_JTAG
VDD_HV_IO_FEC
VDD_HV_IO_MSC
VDD_HV_ADR_SD Amps
VDD_HV_ADV_SD
VDD_HV_ADR_SAR Amps

VDD_HV_ADV_SAR 2mA

Symbol Parameter Conditions

POR098_c LV internal supply power on

reset

LVD_core_

hot

LVD_core_

cold

LV internal2 supply low voltage
monitoring

LV external3 supply low voltage
monitoring

HVD_core LV internal cold supply high

voltage monitoring

LVD_HV HV internal supply low voltage

monitoring

HVD_HV HV internal supply high voltage

monitoring

LVD_IO Main IO and RC oscillator

supply voltage monitoring

LVD_SAR SAR ADC supply low voltage

monitoring

t

VDASSERT

Voltage detector threshold
crossing assertion

t

VDRELEASE

Voltage detector threshold
crossing de-assertion

Rising voltage (power up) N/A No Enab.960 1010 1060 mV
Falling voltage (power down) 940 990 1040
Rising voltage (trimmed) 6bit No Enab.1146 1169 1193 mV
Falling voltage (trimmed) 1146 1169 1193
Rising voltage 6bit Yes Disab.1161 1185 1208 mV
Falling voltage 1161 1185 1208
Rising voltage 6bit Yes Disab.1353 1395 1438 mV
Falling voltage 1343 1385 1438
Rising voltage (trimmed) 6bit No Enab.3300 3400 3500 mV
Falling voltage (trimmed) 3270 3370 3470
Rising voltage 6bit Yes Disab.5530 5700 5870 mV
Falling voltage 5500 5670 5840
Rising voltage (trimmed) 6bit No Enab.3300 3400 3500 mV
Falling voltage (trimmed) 3270 3370 3470
Rising voltage 6bit Yes Disab.2820 2910 3000 mV
Falling voltage 2790 2880 2970
— — — — 0.1 — 2.0 µs

— — — — 5 — 20 µs

Power management PMC POR LVD sequencing

Configuration Value

Trim

Mas

Pow

bits

Min Typ Max

k

. Up

Unit

Opt.

1. POR085_c and POR096_c threshold are untrimmed value, before the completion of the power-up sequence. All other
LVD/HVD thresholds are provided after trimming.

2. LV internal supply levels are measured on device internal supply grid after internal voltage drop.

3. LV external supply levels are measured on the die size of the package bond wire after package voltage drop.

16.1.6 Power up/down sequencing

The following shows the constraints and relationships for the different power supplies.

Figure 21. Device supply relation during power-up/power-down sequence

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 53

Flash memory specifications

Each column indicates that the corresponding supply is 0 and the other supplies are UP.
For example, the "Amps" cell in the "V
V

DD_HV_ADR_SD

Amp flowing into V

supply is 0 and all other supplies are UP, this supply has a current in

DD_HV_ADR_SD

.

DD_HV_ADV_SD

=0" column shows that when

17

Flash memory specifications

17.1 Flash memory program and erase specifications

NOTE

All timing, voltage, and current numbers specified in this
section are defined for a single embedded flash memory within
an SoC, and represent average currents for given supplies and
operations.

Table 30 shows the estimated Program/Erase times.

Table 30. Flash memory program and erase specifications

Symbol Characteristic

t

dwpgm

t

ppgm

t

qppgm

t

16kers

t

16kpgm

t

32kers

t

32kpgm

t

64kers

t

64kpgm

t

256kers

t

256kpgm

Doubleword (64 bits) program time 43 100 150 55 500 μs
Page (256 bits) program time 73 200 300 108 500 μs
Quad-page (1024 bits) program

time
16 KB Block erase time 168 290 320 250 1,000 ms
16 KB Block program time 34 45 50 40 1,000 ms
32 KB Block erase time 217 360 390 310 1,200 ms
32 KB Block program time 69 100 110 90 1,200 ms
64 KB Block erase time 315 490 590 420 1,600 ms
64 KB Block program time 138 180 210 170 1,600 ms
256 KB Block erase time 884 1,520 2,030 1,080 4,000 — ms
256 KB Block program time 552 720 880 650 4,000 — ms

1

2

Typ

268 800 1,200 396 2,000 μs

Factory

Programming

Initial

Max

20°C ≤T

A

≤30°C

3, 4

Initial

Max, Full

Temp

-40°C ≤T
≤150°C

-40°C ≤T

J

Typical

End of

5

Life

≤150°C

Field Update Unit

Lifetime Max

≤ 1,000

J

cycles

6

≤ 250,000

cycles

1. Program times are actual hardware programming times and do not include software overhead. Block program times
assume quad-page programming.

2. Typical program and erase times represent the median performance and assume nominal supply values and operation at
25 °C. Typical program and erase times may be used for throughput calculations.

3. Conditions: ≤ 150 cycles, nominal voltage.

4. Plant Programing times provide guidance for timeout limits used in the factory.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

54 NXP Semiconductors

Flash memory specifications

5. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations.

6. Conditions: -40°C ≤ TJ ≤ 150°C, full spec voltage.

17.2 Flash memory Array Integrity and Margin Read

specifications

Table 31. Flash memory Array Integrity and Margin Read specifications

Symbol Characteristic Min Typical Max

1

Units

2

t

ai16kseq

t

ai32kseq

t

ai64kseq

tai256kseq

t

mr16kseq

t

mr32kseq

t

mr64kseq

t

mr256kseq

1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The
equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and
Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires
6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the
address pipeline set to 2, Nread would equal 4 (or 6 - 2).)

2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the
equation, the results of the equation are also unit accurate.

Array Integrity time for sequential sequence on 16 KB block. — — 512 x

Tperiod x

Nread

Array Integrity time for sequential sequence on 32 KB block. — — 1024 x

Tperiod x

Nread

Array Integrity time for sequential sequence on 64 KB block. — — 2048 x

Tperiod x

Nread

Array Integrity time for sequential sequence on 256 KB block. — — 8192 x

Tperiod x

Nread
Margin Read time for sequential sequence on 16 KB block. 73.81 — 110.7 μs
Margin Read time for sequential sequence on 32 KB block. 128.43 — 192.6 μs
Margin Read time for sequential sequence on 64 KB block. 237.65 — 356.5 μs
Margin Read time for sequential sequence on 256 KB block. 893.01 — 1,339.5 μs

—

—

—

—

17.3 Flash memory module life specifications

Table 32. Flash memory module life specifications

Symbol Characteristic Conditions Min Typical Units

Array P/E
cycles

Data
retention

NXP Semiconductors 55

Number of program/erase cycles per block
for 16 KB, 32 KB and 64 KB blocks.

Number of program/erase cycles per block
for 256 KB blocks.

Minimum data retention. Blocks with 0 - 1,000 P/E

2

1

Table continues on the next page...

— 250,000 — P/E

— 1,000 250,000 P/E

cycles.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

cycles

cycles

50 — Years

Flash memory specifications

Table 32. Flash memory module life specifications (continued)

Symbol Characteristic Conditions Min Typical Units

Blocks with 100,000 P/E
cycles.

Blocks with 250,000 P/E
cycles.

1. Program and erase supported across standard temperature specs.

2. Program and erase supported across standard temperature specs.

20 — Years

10 — Years

17.4 Data retention vs program/erase cycles

Graphically, Data Retention versus Program/Erase Cycles can be represented by the
following figure. The spec window represents qualified limits. The extrapolated dotted
line demonstrates technology capability, however is beyond the qualification limits.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

56 NXP Semiconductors

Flash memory specifications

17.5 Flash memory AC timing specifications

Table 33. Flash memory AC timing specifications

Symbol Characteristic Min Typical Max Units

t

psus

t

esus

t

res

t

done

t

dones

t

drcv

t

aistart

t

aistop

t

mrstop

Time from setting the MCR-PSUS bit until MCR-DONE bit is set

— 9.4

to a 1.

Time from setting the MCR-ESUS bit until MCR-DONE bit is set

— 16

to a 1.

Time from clearing the MCR-ESUS or PSUS bit with EHV = 1

— — 100 ns

until DONE goes low.
Time from 0 to 1 transition on the MCR-EHV bit initiating a

— — 5 ns

program/erase until the MCR-DONE bit is cleared.
Time from 1 to 0 transition on the MCR-EHV bit aborting a

— 16

program/erase until the MCR-DONE bit is set to a 1.

Time to recover once exiting low power mode. 16

plus seven

system

clock

periods.

Time from 0 to 1 transition of UT0-AIE initiating a Margin Read

— — 5 ns
or Array Integrity until the UT0-AID bit is cleared. This time also
applies to the resuming from a suspend or breakpoint by
clearing AISUS or clearing NAIBP

Time from 1 to 0 transition of UT0-AIE initiating an Array

— — 80
Integrity abort until the UT0-AID bit is set. This time also applies
to the UT0-AISUS to UT0-AID setting in the event of a Array
Integrity suspend request.

Time from 1 to 0 transition of UT0-AIE initiating a Margin Read
abort until the UT0-AID bit is set. This time also applies to the
UT0-AISUS to UT0-AID setting in the event of a Margin Read
suspend request.

10.36

plus four

system

clock

periods

plus four

system

clock

periods

plus four

system

clock

periods

plus four

system

clock

periods

— 45

— 20.42

11.5

plus four

system

clock

periods

20.8

plus four

system

clock

periods

20.8

plus four

system

clock

periods

plus seven

system

clock

periods

plus fifteen

system

clock

periods

plus four

system

clock

periods

μs

μs

μs

μs

ns

μs

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 57

AC specifications

17.6 Flash read wait state and address pipeline control settings

Table 34 describes the recommended RWSC and APC settings at various operating

frequencies based on specified intrinsic flash access times of the C55FMC array at 150
°C.

Table 34. Flash Read Wait State and Address Pipeline Control Guidelines

Operating Frequency

f

SYS

30 MHz 0 0 3 1
100 MHz 2 1 5 1
133 MHz 3 1 6 1
167 MHz 4 1 7 1
200 MHz 5 2 8 1

RWSC APC

Flash read latency on mini-

cache miss (# of f

periods)

SYS

clock

18 AC specifications

18.1 Debug and calibration interface timing

Flash read latency on mini-

cache hit (# of f

periods)

SYS

clock

18.1.1 JTAG interface timing

These specifications apply to JTAG boundary scan only. See Table 36 for functional
specifications.

Table 35. JTAG pin AC electrical characteristics

# Symbol Characteristic

1 t
2 t
3 t
4 t
5 t
6 t

TMSS

TMSH

JCYC

JDC

TCKRISE

, t

TDIS

, t

TDIH

TDOV

TCK cycle time 100 — ns
TCK clock pulse width 40 60 ns
TCK rise and fall times — 3 ns
TMS, TDI data setup time 5 — ns
TMS, TDI data hold time 5 — ns
TCK low to TDO data valid — 16

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

58 NXP Semiconductors

Value

Min Max

Unit

1

ns

Table 35. JTAG pin AC electrical characteristics (continued)

TCK

3

1

3

2

2

AC specifications

# Symbol Characteristic

7 t
8 t

9 t
10 t
11 t
12 t
13 t
14 t
15 t

TDOI

TDOHZ

JCMPPW

JCMPS

BSDV

BSDVZ

BSDHZ

BSDST

BSDHT

TCK low to TDO data invalid 0 — ns
TCK low to TDO high impedance — 15 ns
JCOMP assertion time 100 — ns
JCOMP setup time to TCK low 40 — ns
TCK falling edge to output valid — 600
TCK falling edge to output valid out of high impedance — 600 ns
TCK falling edge to output high impedance — 600 ns
Boundary scan input valid to TCK rising edge 15 — ns
TCK rising edge to boundary scan input invalid 15 — ns

Min Max

Unit

2

ns

1. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

2. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.

Value

Figure 22. JTAG test clock input timing

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 59

TCK

6

8

7

5

TMS, TDI

TDO

4

TCK

JCOMP

9

10

AC specifications

Figure 23. JTAG test access port timing

Figure 24. JTAG JCOMP timing

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

60 NXP Semiconductors

TCK

11

15

14

12

13

Output

Output

Input

Signals

Signals

Signals

AC specifications

Figure 25. JTAG boundary scan timing

18.1.2

Nexus interface timing

Nexus timing specified for the whole V

DD_LV

and V

DD_HV_IO

dynamic, TA = TL to TH,

and maximum loading per pad type as specified in the I/O section of the data sheet.

Table 36. Nexus debug port timing

# Symbol Characteristic

1 t
2 t
3 t
4 t

EVTIPW

EVTOPW

TCYC

TCYC

EVTI Pulse Width 4 — t
EVTO Pulse Width 40 — ns
TCK cycle time 4
Absolute minimum TCK cycle time4 (TDO sampled on posedge of

TCK)

Table continues on the next page...

Value Unit

Min Max

40

2, 3

5

— t
— ns

CYC

CYC

, 1

1

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 61

TCK

3

EVTI
EVTO

AC specifications

Table 36. Nexus debug port timing (continued)

# Symbol Characteristic

Value Unit

Min Max

Absolute minimum TCK cycle time6 (TDO sampled on negedge of

20

5

—

TCK)
5 t
6 t
7 t
8 t

NTDIS

NTDIH

NTMSS

NTMSH

9 — TDO propagation delay from falling edge of TCK

10 — TDO hold time with respect to TCK falling edge (minimum TDO

TDI data setup time 5 — ns

TDI data hold time 5 — ns

TMS data setup time 5 — ns

TMS data hold time 5 — ns

7

— 16 ns

2.25 — ns

propagation delay)

1. t

is system clock period.

CYC

2. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency
being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number
greater than or equal to that specified here.

3. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.

4. This value is TDO propagation time 36ns + 4ns setup time to sampling edge.

5. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the
design (system frequency / 4) depending on the actual system frequency being used.

6. This value is TDO propagation time 16ns + 4ns setup time to sampling edge.

7. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.

Figure 26. Nexus output timing

Figure 27. Nexus event trigger and test clock timings

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

62 NXP Semiconductors

TCK

5

10

9

8

6

TMS, TDI

TDO

7

AC specifications

Figure 28. Nexus TDI, TMS, TDO timing

18.1.3

Aurora LVDS interface timing

Table 37. Aurora LVDS interface timing specifications

Symbol Parameter

— Data rate — 1250 Mbps

t

STRT_BIAS

t

STRT_TX

t

STRT_RX

1. Startup time is defined as the time taken by LVDS current reference block for settling bias current after its pwr_down
(power down) has been deasserted. LVDS functionality is guaranteed only after the startup time.

2. Startup time is defined as the time taken by LVDS transmitter for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is
guaranteed only after the startup time.

Data Rate

Min Typ Max

STARTUP
Bias startup time
Transmitter startup time
Receiver startup time

1

2

3

— — 5 µs
— — 5 µs
— — 4 µs

Value

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 63

AC specifications

3. Startup time is defined as the time taken by LVDS receiver for settling after its pwr_down (power down) has been
deasserted. Here it is assumed that current reference is already stable (see Bias start-up time). LVDS functionality is
guaranteed only after the startup time.

18.1.3.1 Aurora debug port timing

Table 38. Aurora debug port timing

# Symbol Parameter

Value

Min Max

1 t

1a t

2 t
3 J
4 t

STABILITY

REFCLK

MCYC

RCDC

RC

Reference clock frequency 625 1200 MHz
Reference clock rise/fall time — 400 ps
Reference clock duty cycle 45 55 %
Reference clock jitter — 40 ps

Reference clock stability 50 — PPM
5 BER Bit error rate — 10
6 J
7 J
8 S
9 S

D

T

O

MO

10 OUI Aurora lane unit interval

Transmit lane deterministic jitter — 0.17 OUI

Transmit lane total jitter — 0.35 OUI

Differential output skew — 20 ps

Lane to lane output skew — 1000 ps

1

625 Mbps 1600 1600 ps

1.25Gbps 800 800 ps

1. ± 100 PPM

-12

Unit

—

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

64 NXP Semiconductors

Tx Data [m]

Zero Crossover

CLOCK

REF

CLOCK

REF

1a

1

2

8

9

9

8 8

2

1a

1a

1a

Zero Crossover

Tx Data

Tx Data

Tx Data [n]

Ideal Zero Crossover

Zero Crossover

Tx Data [n+1]

Zero Crossover

AC specifications

18.2

DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel
bus protocol.

DSPI channel frequency support is shown in Table 39. Timing specifications are shown
in Table 40, Table 41, Table 42, Table 43, Table 44.

NXP Semiconductors 65

Figure 29. Aurora timings

DSPI timing with CMOS and LVDS

Table 39. DSPI channel frequency support

DSPI use mode

CMOS (Master mode) Full duplex – Classic timing (Table 40) 17

Full duplex – Modified timing (Table 41) 30
Output only mode (SCK/SOUT/PCS) (Table 40 and Table 41) 30
Output only mode TSB mode (SCK/SOUT/PCS) (Table 44) 30

LVDS (Master mode) Full duplex – Modified timing (Table 42) 40

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

Max usable frequency

(MHz)1,

2

AC specifications

1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.

2. Maximum usable frequency does not take into account external device propagation delay.

18.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads

The values presented in these sections are target values. A complete performance
characterization of the pads (in all configuration combinations) is required before the
final specifications can be released.

18.2.1.1 DSPI CMOS master mode – classic timing

All output timing is worst case and includes the mismatching of rise and fall times of the
output pads.

NOTE

In Table 40, all output timing is worst case and includes the
mismatching of rise and fall times of the output pads.

Table 40. DSPI CMOS master classic timing (full duplex and output only) - MTFE = 0, CPHA

= 0 or 1

# Symbol Characteristic Condition Value

2

Table continues on the next page...

Load (CL) Min Max

PCS = 50 pF
SCK = 50 pF

SCK = 50 pF

SCK = 50 pF

SCK = 50 pF
PCS = 0 pF (M5 x t

(N3 x t

(M5 x t

(M5 x t

(M5 x t

, 4

) - 16 — ns

SYS

, 4

) - 16 —

SYS

, 4

) - 16 —

SYS

, 4

) - 29 —

SYS

4

) - 35 — ns

SYS

, 4

) - 35 —

SYS

, 4

) - 35 —

SYS

, 4

) - 35 —

SYS

1 t

2 t

3 t

SCK

CSC

ASC

Pad drive

SCK cycle time SCK drive strength

Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —

PCS to SCK delay SCK and PCS drive strength

Very strong 25 pF (N3 x t
Strong 50 pF (N3 x t
Medium 50 pF (N3 x t
PCS medium and

SCK strong

After SCK delay SCK and PCS drive strength

Very strong PCS = 0 pF

Strong PCS = 0 pF

Medium PCS = 0 pF

PCS medium and
SCK strong

1

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

66 NXP Semiconductors

AC specifications

Table 40. DSPI CMOS master classic timing (full duplex and output only) - MTFE = 0, CPHA

= 0 or 1 (continued)

# Symbol Characteristic Condition Value

Pad drive

2

Load (CL) Min Max

SCK = 50 pF

4 t

SDC

SCK duty cycle

6

SCK drive strength
Very strong 0 to 50 pF
Strong 0 to 50 pF
Medium 0 to 50 pF

1

/2t

- 2

SCK

1

/2t

- 2

SCK

1

/2t

- 5

SCK

PCS strobe timing
5 t

6 t

PCSC

PASC

PCSx to PCSS time

7

PCSS to PCSx time7PCS and PCSS drive strength

,

PCS and PCSS drive strength
Strong 25 pF 13.0 — ns

Strong 25 pF 13.0 — ns
SIN setup time
7 t

SUI

SIN setup time to

8

SCK

SCK drive strength

Very strong 25 pF 25.0 — ns

Strong 50 pF 31.0 —

Medium 50 pF 52.0 —
SIN hold time
8 t

HI

SIN hold time from

8

SCK

SCK drive strength

Very strong 0 pF -1.0 — ns

Strong 0 pF -1.0 —

Medium 0 pF -1.0 —
SOUT data valid time (after SCK edge)
9 t

SUO

SOUT data valid time
from SCK

9

SOUT and SCK drive strength

Very strong 25 pF — 7.0 ns

Strong 50 pF — 8.0

Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
10 t

HO

SOUT data hold time
after SCK

9

SOUT and SCK drive strength

Very strong 25 pF -7.7 — ns

Strong 50 pF -11.0 —

Medium 50 pF -15.0 —

1

1

/2t

+ 2 ns

SCK

1

/2t

+ 2

SCK

1

/2t

+ 5

SCK

Unit

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).

4. t

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t

SYS

SYS

= 10

ns).

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 67

Data

Data

Last Data

First Data

First Data

Last Data

SIN

SOUT

SCK Output

SCK OutputSCK Output

(CPOL = 0)

PCSx

(CPOL = 1)

t

SCK

t

SDC

t

SDC

CSC

t

t

ASC

t

t

SUI

HI

t

SUO

t

HO

AC specifications

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).

6. t

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

SDC

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. PCSx and PCSS using same pad configuration.

8. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds.

9. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

Figure 30. DSPI CMOS master mode – classic timing, CPHA = 0

68 NXP Semiconductors

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

SCK Output

SIN

SOUT

Fist Data

Fist Data

Last Data

Last Data

Data

Data

SCK Output

(CPOL = 0)

PCSx

(CPOL = 1)

t

t

t

t

SUI

HI

SUO

HO

Figure 31. DSPI CMOS master mode – classic timing, CPHA = 1

PCSx

PCSS

t

PCSC

t

PASC

AC specifications

Figure 32. DSPI PCS strobe (PCSS) timing (master mode)

18.2.1.2

DSPI CMOS master mode – modified timing

All output timing is worst case and includes the mismatching of rise and fall times of the
output pads.

NOTE

In Table 41, all output timing is worst case and includes the
mismatching of rise and fall times of the output pads.

Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1,

CPHA = 0 or 1

# Symbol Characteristic Condition Value

Pad drive

Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —

1 t

SCK

SCK cycle time SCK drive strength

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 69

2

Table continues on the next page...

Load (CL) Min Max

1

Unit

AC specifications

Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1,

CPHA = 0 or 1 (continued)

# Symbol Characteristic Condition Value

Pad drive

2

Load (CL) Min Max

Medium 50 pF 200.0 —

2 t

3 t

CSC

ASC

PCS to SCK delay SCK and PCS drive strength

Very strong 25 pF (N3 x t
Strong 50 pF (N3 x t
Medium 50 pF (N3 x t
PCS medium and

SCK strong

PCS = 50 pF
SCK = 50 pF

After SCK delay SCK and PCS drive strength

Very strong PCS = 0 pF

(N3 x t

(M5 x t

, 4

) - 16 — ns

SYS

, 4

) - 16 —

SYS

, 4

) - 16 —

SYS

, 4

) - 29 —

SYS

4

) - 35 — ns

SYS

SCK = 50 pF

Strong PCS = 0 pF

(M5 x t

, 4

) - 35 —

SYS

SCK = 50 pF

Medium PCS = 0 pF

(M5 x t

, 4

) - 35 —

SYS

SCK = 50 pF

, 4

) - 35 —

SYS

1

/2t

- 2

SCK

1

/2t

- 2

SCK

1

/2t

- 5

SCK

4 t

SDC

SCK duty cycle

PCS medium and
SCK strong

6

SCK drive strength
Very strong 0 to 50 pF
Strong 0 to 50 pF
Medium 0 to 50 pF

PCS = 0 pF
SCK = 50 pF

(M5 x t

PCS strobe timing
5 t

6 t

PCSC

PASC

PCSx to PCSS time

7

PCSS to PCSx time7PCS and PCSS drive strength

,

PCS and PCSS drive strength
Strong 25 pF 13.0 — ns

Strong 25 pF 13.0 — ns
SIN setup time
7 t

SUI

SIN setup time to
SCK

CPHA = 0

8

SIN setup time to
SCK

CPHA = 1

8

SCK drive strength

Very strong 25 pF 25 - (P9 x t

Strong 50 pF 31 - (P9 x t

Medium 50 pF 52 - (P9 x t

SYS

SYS

SYS

, 4

, 4

SCK drive strength

Very strong 25 pF 25.0 — ns

Strong 50 pF 31.0 —

Medium 50 pF 52.0 —
SIN hold time
8 t

HI

SIN hold time from
SCK

SCK drive strength

Very strong 0 pF -1 + (P8 x t

SYS

, 3

Table continues on the next page...

1

1

/2t

+ 2 ns

SCK

1

/2t

+ 2

SCK

1

/2t

+ 5

SCK

4

) — ns

) —
) —

) — ns

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

70 NXP Semiconductors

AC specifications

Table 41. DSPI CMOS master modified timing (full duplex and output only) - MTFE = 1,

CPHA = 0 or 1 (continued)

# Symbol Characteristic Condition Value

2

Load (CL) Min Max

, 3

SYS

, 3

SYS

CPHA = 0

9

SIN hold time from
SCK CPHA = 1

9

Pad drive

Strong 0 pF -1 + (P8 x t

Medium 0 pF -1 + (P8 x t

SCK drive strength

Very strong 0 pF -1.0 — ns

Strong 0 pF -1.0 —

Medium 0 pF -1.0 —
SOUT data valid time (after SCK edge)
9 t

SUO

SOUT data valid time
from SCK

CPHA = 0

9

SOUT and SCK drive strength

Very strong 25 pF — 7.0 + t

Strong 50 pF — 8.0 + t

Medium 50 pF — 16.0 + t

SOUT data valid time
from SCK

CPHA = 1

9

SOUT and SCK drive strength

Very strong 25 pF — 7.0 ns

Strong 50 pF — 8.0

Medium 50 pF — 16.0
SOUT data hold time (after SCK edge)
10 t

HO

SOUT data hold time
after SCK

CPHA = 0

10

SOUT data hold time
after SCK

CPHA = 1

10

SOUT and SCK drive strength

Very strong 25 pF -7.7 + t

Strong 50 pF -11.0 + t

Medium 50 pF -15.0 + t

SYS

SYS

SYS

4

4

4

SOUT and SCK drive strength

Very strong 25 pF -7.7 — ns

Strong 50 pF -11.0 —

Medium 50 pF -15.0 —

1

) —
) —

— ns
—
—

SYS

SYS

SYS

4

ns

4

4

Unit

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.

3. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).

4. t

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t

SYS

SYS

= 10

ns).

5. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).

6. t

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

SDC

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

7. PCSx and PCSS using same pad configuration.

8. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL voltage thresholds.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 71

Data

Data

Last Data

First Data

First Data

Last Data

SIN

SOUT

SCK Output

SCK Output

(CPOL = 0)

PCSx

(CPOL = 1)

t

SCK

t

SDC

t

SDC

CSC

t

t

ASC

t

t

SUI

HI

t

SUO

t

HO

SIN

PCSx

SCK Output

SCK Output

SOUT

First Data

First Data

(CPOL=1)

(CPOL=0)

Last Data

Last Data

DataData

Data

t

SUI

t

HI

t

SUO

t

HO

t

HI

AC specifications

9. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set
to 1.

10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same

value.

Figure 33. DSPI CMOS master mode – modified timing, CPHA = 0

Figure 34. DSPI CMOS master mode – modified timing, CPHA = 1

72 NXP Semiconductors

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

PCSx

PCSS

t

PCSC

t

PASC

AC specifications

Figure 35. DSPI PCS strobe (PCSS) timing (master mode)1

18.2.1.3 DSPI LVDS master mode – modified timing

Table 42. DSPI LVDS master timing - full duplex - modified transfer format (MTFE = 1),

CPHA = 0 or 1

# Symbol Characteristic Condition Value

Pad drive Load Min Max

1 t

SCK

SCK cycle time LVDS 15 pF

30.0 — ns
to 25 pF
differential

2 t

3 t

CSC

ASC

PCS to SCK delay
(LVDS SCK)

After SCK delay
(LVDS SCK)

PCS drive strength
Very strong 25 pF (N2 x t
Strong 50 pF (N2 x t
Medium 50 pF (N2 x t
Very strong PCS = 0 pF

(M4 x t

SCK = 25 pF

Strong PCS = 0 pF

(M4 x t

, 3

) - 10 — ns

SYS

, 3

) - 10 — ns

SYS

, 3

) - 32 — ns

SYS

3

) - 8 — ns

SYS

, 3

) - 8 — ns

SYS

SCK = 25 pF

Medium PCS = 0 pF

(M4 x t

, 3

) - 8 — ns

SYS

SCK = 25 pF

4 t

SDC

SCK duty cycle

5

LVDS 15 pF

1

/2t

- 2

SCK

to 25 pF
differential

7 t

SUI

SIN setup time
SIN setup time to

SCK
CPHA = 0

6

SCK drive strength
LVDS 15 pF

to 25 pF

23 - (P7 x t

SYS

differential

SIN setup time to
SCK

CPHA = 1

6

SCK drive strength
LVDS 15 pF

to 25 pF

23 — ns

differential

8 t

HI

SIN Hold Time

Table continues on the next page...

1

1

/2t

+ 2 ns

SCK

3

) — ns

Unit

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 73

AC specifications

Table 42. DSPI LVDS master timing - full duplex - modified transfer format (MTFE = 1),

CPHA = 0 or 1 (continued)

# Symbol Characteristic Condition Value

Pad drive Load Min Max

9 t

SUO

SIN hold time from
SCK

CPHA = 0

6

SIN hold time from
SCK

CPHA = 1

6

SOUT data valid time (after SCK edge)
SOUT data valid time

from SCK
CPHA = 0

8

SCK drive strength
LVDS 0 pF differential -1 + (P7 x t

SYS

, 3

SCK drive strength
LVDS 0 pF differential -1 — ns

SOUT and SCK drive strength
LVDS 15 pF

— 7.0 + t
to 25 pF
differential

SOUT data valid time
from SCK

CPHA = 1

8

SOUT and SCK drive strength
LVDS 15 pF

to 25 pF

— 7.0 ns

differential

10 t

HO

SOUT data hold time (after SCK edge)
SOUT data hold time

after SCK
CPHA = 0

8

SOUT and SCK drive strength
LVDS 15 pF

to 25 pF

-7.5 + t

SYS

3

differential

SOUT data hold time
after SCK

CPHA = 1

8

SOUT and SCK drive strength
LVDS 15 pF

to 25 pF

-7.5 — ns

differential

1

) — ns

3

SYS

ns

— ns

Unit

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).

3. t

is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 100 MHz (min t

SYS

SYS

= 10

ns).

4. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).

5. t

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

SDC

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

6. Input timing assumes an input slew rate of 1 ns (10% - 90%) and LVDS differential voltage = ±100 mV.

7. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set
to 1.

8. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

74 NXP Semiconductors

Data

Data

Last Data

First Data

First Data

Last Data

SIN

SOUT

SCK Output

SCK OutputSCK Output

(CPOL = 0)

PCSx

(CPOL = 1)

t

SCK

t

SDC

t

SDC

CSC

t

t

ASC

t

t

SUI

HI

t

SUO

t

HO

Figure 36. DSPI LVDS master mode – modified timing, CPHA = 0

Data

First Data

First Data

Last Data

Data

Last Data

SIN

PCSx

SCK Output

SCK Output

(CPOL = 0)

(CPOL = 1)

SOUT

t

SUI

t

t

HI

HI

t

SUO

t

HO

AC specifications

18.2.1.4

For Table 43 :

Figure 37. DSPI LVDS master mode – modified timing, CPHA = 1

DSPI master mode – output only

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 75

AC specifications

• All DSPI timing specifications apply to pins when using LVDS pads for SCK and
SOUT and CMOS pad for PCS with pad driver strength as defined. Timing may
degrade for weaker output drivers.

• TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

Table 43. DSPI LVDS master timing - output only - timed serial bus mode TSB = 1 or ITSB =

1, CPOL = 0 or 1, continuous SCK clock

# Symbol Characteristic Condition Value Unit

Pad drive Load Min Max

1 t

SCK

2 t

CSV

3 t

CSH

4 t

SDC

SOUT data valid time (after SCK edge)
5 t

SUO

SOUT data hold time (after SCK edge)
6 t

HO

SCK cycle time LVDS 15 pF

to 50 pF

differential
PCS valid after SCK
(SCK with 50 pF

differential load cap.)
PCS hold after SCK
(SCK with 50 pF

differential load cap.)
SCK duty cycle
(SCK with 50 pF

differential load cap.)

SOUT data valid time
from SCK

SOUT data hold time
after SCK

2

2

1

Very strong 25 pF — 6.0 ns
Strong 50 pF — 6.0 ns

1

Very strong 0 pF -4.0 — ns
Strong 0 pF -4.0 — ns

LVDS 15 pF

to 50 pF

differential

SOUT and SCK drive strength
LVDS 15 pF

to 50 pF

differential

SOUT and SCK drive strength
LVDS 15 pF

to 50 pF

differential

25.0 — ns

1

/2t

- 2

SCK

— 3.5 ns

-3.5 — ns

1

/2t

SCK

+ 2 ns

1. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.

2. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

For Table 44 :

• TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.

• All output timing is worst case and includes the mismatching of rise and fall times of
the output pads.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

76 NXP Semiconductors

AC specifications

Table 44. DSPI CMOS master timing - output only - timed serial bus mode TSB = 1 or ITSB =

1, CPOL = 0 or 1, continuous SCK clock

# Symbol Characteristic Condition Value

2

Load (CL) Min Max

1 t

SCK

Pad drive

SCK cycle time SCK drive strength

Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 — ns
Medium 50 pF 200.0 — ns

2 t

CSV

PCS valid after SCK3SCK and PCS drive strength

Very strong 25 pF 7 — ns
Strong 50 pF 8 — ns
Medium 50 pF 16 — ns

3 t

CSH

PCS medium and
SCK strong

PCS hold after SCK3SCK and PCS drive strength

Very strong PCS = 0 pF

PCS = 50 pF
SCK = 50 pF

29 — ns

-14 — ns

SCK = 50 pF

Strong PCS = 0 pF

-14 — ns

SCK = 50 pF

Medium PCS = 0 pF

-33 — ns

SCK = 50 pF

4 t

SDC

SCK duty cycle

PCS medium and
SCK strong

4

SCK drive strength
Very strong 0 to 50 pF
Strong 0 to 50 pF
Medium 0 to 50 pF

PCS = 0 pF
SCK = 50 pF

-35 — ns

1

/2t

- 2

SCK

1

/2t

- 2

SCK

1

/2t

- 5

SCK

SOUT data valid time (after SCK edge)
9 t

SUO

SOUT data valid time
from SCK

CPHA = 1

, 5

SOUT and SCK drive strength
Very strong 25 pF — 7.0 ns
Strong 50 pF — 8.0 ns

Medium 50 pF — 16.0 ns
SOUT data hold time (after SCK edge)
10 t

HO

SOUT data hold time
after SCK CPHA = 1

SOUT and SCK drive strength

5

Very strong 25 pF -7.7 — ns

Strong 50 pF -11.0 — ns

Medium 50 pF -15.0 — ns

1

1

/2t

+ 2 ns

SCK

1

/2t

+ 2 ns

SCK

1

/2t

+ 5 ns

SCK

Unit

1. All timing values for output signals in this table are measured to 50% of the output voltage.

2. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.

3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 77

PCSx

SCK Output

(CPOL = 0)

SOUT

First Data

Last Data

Data

t

SUO t

HO

t

CSV

t

SDC

t

SCK

t

CSH

AC specifications

4. t

is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide

SDC

ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.

5. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.

Figure 38. DSPI LVDS and CMOS master timing – output only – modified transfer format

MTFE = 1, CHPA = 1

18.2.2 DSPI CMOS slave mode

DSPI slave operation is only supported for a single master and
single slave on the device. Timing is valid for that case only.

Table 45. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1)

# Symbol Characteristic

1 t
2 t
3 t
4 t
5 t

SCK

CSC

ASC

SDC

A

SCK Cycle Time — — 62 — ns
SS to SCK Delay — — 16 — ns
SCK to SS Delay — — 16 — ns
SCK Duty Cycle — — 30 — ns
Slave Access Time
(SS active to SOUT

driven)

6 t

DIS

9 t

SUI

Slave SOUT Disable

2

Time
(SS inactive to SOUT

High-Z or invalid)
Data Setup Time for

Inputs

1

Condition Value Unit

Pad drive Load Min Max

2

Very strong 25 pF — 50 ns
Strong 50 pF — 50 ns
Medium 50 pF — 60 ns
Very strong 25 pF — 5 ns
Strong 50 pF — 5 ns
Medium 50 pF — 10 ns

— — 10 — ns

Table continues on the next page...

NOTE

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

78 NXP Semiconductors

L a st D a ta

F irs t D a ta

D ata

D a ta

S IN

S O U T

S S

S C K I n p u t

F irs t D a ta

L a st D a ta

S C K In p u t

(C P O L =0 )

(C P O L =1 )

t

SCK

t

A

t

DIS

t

SDC

t

SDC

t

CSC

t

ASC

t

SUI

t

HI

t

SUO

t

HO

AC specifications

Table 45. DSPI CMOS slave timing - Modified Transfer Format (MTFE = 0/1) (continued)

# Symbol Characteristic

10 t

HI

11 t

SUO

12 t

HO

1. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.

2. All timing values for output signals in this table, are measured to 50% of the output voltage. All output timing is worst case
and includes the mismatching of rise and fall times of the output pads.

Data Hold Time for
Inputs

SOUT Valid Time
(after SCK edge)

SOUT Hold Time
(after SCK edge)

1

Pad drive Load Min Max

— — 10 — ns

2

Very strong 25 pF — 30 ns
Strong 50 pF — 30 ns
Medium 50 pF — 50 ns

2

Very strong 25 pF 2.5 — ns
Strong 50 pF 2.5 — ns
Medium 50 pF 2.5 — ns

Condition Value Unit

Figure 39. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 0

NXP Semiconductors 79

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

L a st D a ta

L a st D a ta

S IN

S O U T

S S

F irs t D a ta

F irs t D a ta

D ata

D a ta

S C K In p u t

S C K I n p u t

(C P O L =0 )

(C P O L =1 )

t

A

t

DIS

t

SUI

t

HI

t

SUO

t

HO

AC specifications

Figure 40. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 1

18.3

FEC timing

The FEC supports the 10/100 Mbps MII, 10/100 Mbps MII-lite, and the 10 Mbps-only 7­wire interface.

18.3.1

MII-lite receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)

The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at
least equal to or greater than the RX_CLK frequency.

All timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels.

Table 46. MII-lite receive signal timing

Spec Characteristic

M1 RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 — ns
M2 RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 — ns
M3 RX_CLK pulse width high 35% 65% RX_CLK period
M4 RX_CLK pulse width low 35% 65% RX_CLK period

Value Unit

Min Max

80 NXP Semiconductors

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

M3

M4

M1

RX_CLK (input)

RX_DV
RX_ER

M2

AC specifications

Figure 41. MII-lite receive signal timing diagram

18.3.2 MII-lite transmit signal timing (TXD[3:0], TX_EN, TX_ER,

TX_CLK)

The transmitter functions correctly up to a TX_CLK maximum frequency of 25 MHz
+1%. There is no minimum frequency requirement. The system clock frequency must be
at least equal to or greater than the TX_CLK frequency.

The transmit outputs (TXD[3:0], TX_EN, TX_ER) can be programmed to transition from
either the rising or falling edge of TX_CLK, and the timing is the same in either case.
This options allows the use of non-compliant MII PHYs.

All timing specifications are referenced from TX_CLK = 1.4 V to the valid output levels.

Table 47. MII-lite transmit signal timing

1

Spec Characteristic

Value

Min Max

M5 TX_CLK to TXD[3:0], TX_EN, TX_ER invalid 5 — ns
M6 TX_CLK to TXD[3:0], TX_EN, TX_ER valid — 25 ns
M7 TX_CLK pulse width high 35% 65% TX_CLK period
M8 TX_CLK pulse width low 35% 65% TX_CLK period

1. Output parameters are valid for CL = 25 pF, where CL is the external load to the device. The internal package capacitance
is accounted for, and does not need to be subtracted from the 25 pF value.

Unit

NXP Semiconductors 81

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

M5

M8

M7

M6

TX_CLK (input)

TX_

EN

TX_

ER

M9

AC specifications

Figure 42. MII-lite transmit signal timing diagram

18.3.3 MII-lite async inputs signal timing (CRS and COL)

Table 48. MII-lite async inputs signal timing

Spec Characteristic

M9 CRS, COL minimum pulse width 1.5 — TX_CLK period

Value Unit

Min Max

Figure 43. MII-lite async inputs timing diagram

18.3.4

MII-lite serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

NOTE

All timing specifications are referenced from MDC = 1.4 V
(TTL levels) to the valid input and output levels, 0.8 V and 2.0
V (TTL levels). For 5 V operation, timing is referenced from
MDC = 50% to 2.2 V/3.5 V input and output levels.

82 NXP Semiconductors

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

Table 49. MII-lite serial management channel timing

M11

M10

M12

M13

MDIO (input)

M14

M15

AC specifications

Spec Characteristic

M10 MDC falling edge to MDIO output invalid (minimum

propagation delay)
M11 MDC falling edge to MDIO output valid (max prop delay) — 25 ns
M12 MDIO (input) to MDC rising edge setup 10 — ns
M13 MDIO (input) to MDC rising edge hold 0 — ns
M14 MDC pulse width high 40% 60% MDC period
M15 MDC pulse width low 40% 60% MDC period

Value Unit

Min Max

0 — ns

Figure 44. MII-lite serial management channel timing diagram

18.3.5

RMII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.

Table 50. RMII serial management channel timing

Spec Characteristic

M10 MDC falling edge to

MDIO output invalid

(minimum propagation

delay)

Table continues on the next page...

Min Max

0 — ns

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 83

Value Unit

MDIO (input)

M12

M13

M10

M15

M14

M11

AC specifications

Table 50. RMII serial management channel timing (continued)

Spec Characteristic

M11 MDC falling edge to

MDIO output valid (max

prop delay)

M12 MDIO (input) to MDC

rising edge setup

M13 MDIO (input) to MDC

rising edge hold
M14 MDC pulse width high 40% 60% MDC period
M15 MDC pulse width low 40% 60% MDC period

Min Max

— 25 ns

10 — ns

0 — ns

Value Unit

Figure 45. RMII-lite serial management channel timing diagram

18.3.6

RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at
least equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK
frequency.

All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels.

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

84 NXP Semiconductors

Table 51. RMII receive signal timing

R2R1

REF_CLK (input)

CRS_DV

R3

R4

AC specifications

Spec Characteristic

R1 RXD[1:0], CRS_DV to REF_CLK setup 4 — ns
R2 REF_CLK to RXD[1:0], CRS_DV hold 2 — ns
R3 REF_CLK pulse width high 35% 65% REF_CLK period
R4 REF_CLK pulse width low 35% 65% REF_CLK period

Value Unit

Min Max

Figure 46. RMII receive signal timing diagram

18.3.7

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz +
1%. There is no minimum frequency requirement. The system clock frequency must be at
least equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK
frequency.

The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either
the rising or falling edge of REF_CLK, and the timing is the same in either case. This
options allows the use of non-compliant RMII PHYs.

All timing specifications are referenced from REF_CLK = 1.4 V to the valid output
levels.

RMII transmit signal timing (TXD[1:0], TX_EN)

Table 52. RMII transmit signal timing

Spec Characteristic

R5 REF_CLK to TXD[1:0], TX_EN invalid 2 — ns
R6 REF_CLK to TXD[1:0], TX_EN valid — 16 ns
R7 REF_CLK pulse width high 35% 65% REF_CLK period
R8 REF_CLK pulse width low 35% 65% REF_CLK period

Value Unit

Min Max

NXP Semiconductors 85

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

R6

REF_CLK (input)

TX_EN

R7

R5

R8

Obtaining package dimensions

Figure 47. RMII transmit signal timing diagram

18.4

UART timings

UART channel frequency support is shown in the following table.

Table 53. UART frequency support

LINFlexD clock frequency

LIN_CLK (MHz)

80 16 3:1 majority voting 5

Oversampling rate Voting scheme Max usable frequency

8 10
6 Limited voting on one sample
5 16
4 20

with configurable sampling

point

18.5 eMIOS timing

Table 54. eMIOS timing

Symbol Characteristic Condition Min.

Value

t

MIPW

eMIOS Input Pulse Width eMIOS_CLK = 100 MHz 2 — cycles

(Mbaud)

13.33

Max.

Value

Unit

19 Obtaining package dimensions

Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.nxp.com and perform a keyword search for

the drawing's document number.

86 NXP Semiconductors

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

Thermal characteristics

If you want the drawing for this package Then use this document number

LQFP 144 PD 98ASS23177W
LQFP 176 PD 98ASS23479W
MAPBGA 252 PD 98ASA00468D
MAPBGA 292 ED 98ASA00261D

20 Thermal characteristics

The following tables describe the thermal characteristics of the device.
Junction temperature is a function of die size, on-chip power dissipation, package thermal

resistance, mounting side (board) temperature, ambient temperature, air flow, power
dissipation or other components on the board, and board thermal resistance.

Table 56. Thermal characteristics for the 144-pin LQFP package

Rating Conditions Symbol Value Unit

Junction to Ambient Natural Convection

Junction to Ambient Natural Convection

Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)

Junction to Board
Junction to Case

4

5

Junction to Package Top

Junction to Package Lead

1, 2

1, 2, 3

1, 3

1, 3

6

7

Single layer board (1s) R

Four layer board (2s2p) R

Single layer board (1s) R

Four layer board (2s2p) R

— R

— R
Natural Convection ψ
Natural Convection ψ

θJA

θJA

θJMA

θJMA

θJB

θJC

JT

JB

41.3 °C/W

33.0 °C/W

32.4 °C/W

26.7 °C/W

21.5 °C/W

7.0 °C/W

0.25 °C/W

16.5 °C/W

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12.

Table 57. Thermal characteristics for the 176-pin LQFP package

Rating Conditions Symbol Value Unit

Junction to Ambient Natural Convection

Junction to Ambient Natural Convection

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 87

1, 2

1, 2, 3

Single layer board (1s) R

Four layer board (2s2p) R

Table continues on the next page...

θJA

θJA

49.9 °C/W

33.8 °C/W

Thermal characteristics

Table 57. Thermal characteristics for the 176-pin LQFP package (continued)

Rating Conditions Symbol Value Unit

Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)

Junction to Board

Junction to Case

4

5

Junction to Package Top

Junction to Package Lead

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12.

1, 3

1, 3

6

7

Single layer board (1s) R

Four layer board (2s2p) R

— R

— R
Natural Convection ψ
Natural Convection ψ

θJMA

θJMA

θJB

θJC

JT

JB

37.8 °C/W

28.2 °C/W

21.0 °C/W

7.8 °C/W

0.3 °C/W

13.0 °C/W

Table 58. Thermal characteristics for the 252-pin MAPBGA package with full solder balls

Rating Conditions Symbol Value Unit

Junction to Ambient Natural Convection

Junction to Ambient Natural Convection

Junction to Ambient (@200 ft/min)
Junction to Ambient (@200 ft/min)

Junction to Board

Junction to Case

4

5

Junction to Package Top

Junction to Package Lead

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.

1, 2

1, 2, 3

1, 3

1, 3

6

7

Single layer board (1s) R

Four layer board (2s2p) R

Single layer board (1s) R

Four layer board (2s2p) R

— R

— R
Natural Convection ψ
Natural Convection ψ

θJA

θJA

θJMA

θJMA

θJB

θJC

JT

JB

43.0 °C/W

26.5 °C/W

33.2 °C/W

22.2 °C/W

12.5 °C/W

6.3 °C/W

0.3 °C/W

8.7 °C/W

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

88 NXP Semiconductors

Thermal characteristics

7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12.

Table 59. Thermal characteristics for the 252-pin MAPBGA package 16 removed balls: 12

central, 4 corner peripheral

Rating Conditions Symbol Value Unit

Junction to Ambient Natural Convection

Junction to Board

Junction to Package Lead

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.

5. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction
temperature per JEDEC JESD51-12.

4

1, 2, 3

5

Four layer board (2s2p) R
Four layer board (2s2p) R

Natural Convection ψ

θJA

θJB

JB

23.8 °C/W

15.9 °C/W

4.8 °C/W

20.1 General notes for specifications at maximum junction

temperature

An estimation of the chip junction temperature, TJ, can be obtained from this equation:
TJ = TA + (R
where:

• TA = ambient temperature for the package (°C)

• R

= junction to ambient thermal resistance (°C/W)

θJA

• PD = power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides a
quick and easy estimation of thermal performance. Unfortunately, there are two values in
common usage: the value determined on a single layer board and the value obtained on a
board with two planes. For packages such as the PBGA, these values can be different by
a factor of two. Which value is closer to the application depends on the power dissipated
by other components on the board. The value obtained on a single layer board is
appropriate for the tightly packed printed circuit board. The value obtained on the board
with the internal planes is usually appropriate if the board has low power dissipation and
the components are well separated.

θJA

× PD)

When a heat sink is used, the thermal resistance is expressed in the following equation as
the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance:

R

= R

θJA

NXP Semiconductors 89

θJC

+ R

θCA

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

Ordering information

where:

• R

• R

• R

R

θJC

environment to change the case to ambient thermal resistance, R

= junction to ambient thermal resistance (°C/W)

θJA

= junction to case thermal resistance (°C/W)

θJC

= case to ambient thermal resistance (°C/W)

θCA

is device related and cannot be influenced by the user. The user controls the thermal

. For instance, the

θCA

user can change the size of the heat sink, the air flow around the device, the interface
material, the mounting arrangement on printed circuit board, or change the thermal
dissipation on the printed circuit board surrounding the device.

To determine the junction temperature of the device in the application when heat sinks
are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine the
junction temperature with a measurement of the temperature at the top center of the
package case using this equation:

TJ = TT + (ΨJT × PD)
where:

• TT = thermocouple temperature on top of the package (°C)

• ΨJT = thermal characterization parameter (°C/W)

• PD = power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a
40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.

21

Ordering information

Table 60. Ordering information

Part Number Device Type Flash/SRAM Emulation RAM Package Frequency

SPC5746RK1MMT5 Sample PD

SPC5746RK1MLU3 Sample PD 4M/256KB - 176 LQFP 150 MHz

SPC5745RK1MMT5 Sample PD 3M/192KB - 252 MAPBGA 200 MHz

SPC5745RK1MLU3 Sample PD 3M / 192 KB - 176 LQFP 150 MHz
SPC5743RK1MLU5 Sample PD 2M / 128KB - 176 LQFP 200 MHz
SPC5743RK1MLQ5 Sample PD 2M / 128 KB - 144 LQFP 200 MHz

PPC5746R2K1MMZ5A Sample ED

1

2

4M / 256 KB - 252 MAPBGA 200 MHz

4M / 256 KB 1 MB 292 MAPBGA 200 MHz

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

90 NXP Semiconductors

Revision history

1. "PD" refers to a production device, orderable in quantity.

2. “ED" refers to an emulation device, orderable in limited quantities. An emulation device (ED) is for use during system
development only and is not to be used in production. An ED is a Production PD chip combined with a companion chip to
form an Emulation and Debug Device (ED) and includes additional RAM memory and debug features. EDs are provided
“as is" without warranty of any kind. In the event of a suspected ED failure, NXP agrees to exchange the suspected failing
ED from the customer at no additional charge, however NXP will not analyze ED returns.

22 Revision history

Table 61. Revision history

Revision Date Description of changes

1 05/2013 Initial release.
2 12/2014 Overall:

• Editorial changes.

• Removed the Classification columns in spec tables and removed statements that values need
to be characterized.

• In footnotes changed cross references to figures to static text.

In section Block diagram :

• In Figure 1, changed "AIPS Bridge 0/1" to "AIPS PBridge_0/1".

• In Figure 2 :

• Changed figure title (was “Peripherals block diagram”).

• Changed "BAF" to "BAR".

• Added PBRIDGE_1, EIM, XBAR, and PBRIDGE_0.

In section Introduction, removed section "Parameter classification".
In section Absolute maximum ratings, Table 1 :

• VDD_HV_IO_FEC spec: removed row for "Using Ethernet Reference to VSS" condition.

• Corrected "VIDD_HV_IO_MSC" to "VDD_HV_IO_MSC".

• Add parameter IIOMAX.

• Deleted IMAXSEG parameter.

In section Operating conditions :

• Deleted sentence "The ranges in this table are design targets...".

• Added a NOTE that all power supplies need to be powered up.

• In Table 3 :

• Removed VDD_HV_FLA.

• Changed minimum voltage of VDD_HV_ADV_SD.

• Modified footnote for S/D ADC supply voltage.

• Modified footnote for SAR ADC supply voltage.

• Modified VRAMP spec to two separate specs for "VRAMP_VDD_LV" and
"VRAMP_VDD_HV_IO_MAIN, VRAMP_VDD_HV_PMC".

In section DC electrical specifications :

• Removed the statement that the ranges are design targets.

• In Table 5 :

• Modified I

• Removed the “PMC only” row of the IDD_HV_PMC “internal core reg bypassed” spec.

• Removed IDD_MAIN_CORE_AC.

• Removed IDD_LKSTP_AC.

• Changed I

• Changed I
"Standby Leakage Current"); changed condition to "V
150C" (was "V

Table continues on the next page...

to show specs depending on device model. Modified footnote.

DD_LV

DDSTBY_ON
DDSTBY_REG

value at 40 °C.

parameter to "32 KB RAM Standby Regulator Current" (was

@1.2 V to 5.9 V, Tj =

DDSTBY

DDSTBY

@1.3 V...")

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 91

Revision history

Table 61. Revision history

Revision Date Description of changes

• Removed IDDOFF.

• Added IDD_BD_STBY.

• Added IVDDA.

In section Input pad specifications :

• In Table 7 :

• Added footnote that supported input levels vary according to pad types.

• Corrected VILTTL Min and Max values.

• Corrected VIHAUTO, VILCMOS_H and VILCMOS Min value.

• In Table 8 :

• Modified |IWPU| Min values for condition Vin = VIH = 0.65 * VDD_HV_IO.

• Modified |IWPD| Min values for condition Vin = VIL = 0.35 * VDD_HV_IO.

• Removed the "Analog Input Leakeage and Pull-Up/Down DC electrical characteristics" table
and the preceding introductory paragraph to be moved to the ADC input description section.

In section Output pad specifications, Table 9, changed VOH and VOL specs to two separate specs
for 3V pads and 5V pads respectively. Corrected VOH Min and VOL Max values.

In section I/O pad current specifications :

• Added I/O Current Consumption tables.

• Modified NOTE on Excel file attached to the Reference Manual.

Added section Reset pad (PORST, RESET) electrical characteristics.
In section Oscillator and FMPLL :

• In Table 13, removed PLL0_PHI0 single period jitter row.

• In Table 15 :

• Modified footnote for CS_EXTAL and CS_XTAL.

• Modified gm (Oscillator Transconductance) spec.

• Removed VHYS.

In section ADC modules, revised the subsection structure and titles:

• Added section ADC input description with content moved from the "Input pad specifications"
section.

• Section "Input impedance and ADC accuracy" renamed to Input equivalent circuit and ADC

conversion characteristics with all content except Figure 11 and Table 19 removed.

• Removed erroneous section "SAR ADC electrical specification".

In section SAR ADC, Table 19 :

• Added footnote ("SAR ADC performance is not guaranteed...") to fCK symbol.

• Changed t

specification min value to 250 ns (was 275).

sample

• Added footnote to OFS and GNE. Changed OFS and GNE min and max values.

• Removed "Input (singe ADC channel)".

• Removed injection row for "Input (double ADC channel)".

• SNR, THD, SINAD, and ENOB specifications: changed frequency condition to 50 kHz (was
125 kHz).

• Changed SNR Min values.

• Added footnote to ENOB.

• Added I

DD_VDDA

, I

DD_VDDR

, and V

BG_REF

parameters.

In section S/D ADC, Table 20 :

• For V

• For f

IN_PK2PK

ADCD_M

parameter second and third rows, changed VSS in Conditions to VDD.

specification, removed sampling frequency footnote from parameter.

• Added footnote to RESOLUTION value.

• For |δ

| specification added footnote to parameter and added new row with more detailed

GAIN

"After calibration" conditions.

• Moved footnote "S/D ADC is functional in the range..." from the ZIN to the SNR parameters.

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

92 NXP Semiconductors

Table 61. Revision history

Revision Date Description of changes

• Changed all instances of “4.0 < VDD_HV_ADV_SD < 5.5” in the Conditions column to “4.5 <
VDD_HV_ADV_SD < 5.5”. Modified voltage range in its footnote.

• Changed SNR

• Changed SINAD

• Unit for SINADDIFF150, SINADDIFF333 and SINADSE150 changed from dBFs to dB.

• For ZIN specification, revised parameter footnote.

• Added CMRR to symbol column for Common mode rejection ratio specification. Changed min
value to 55 dB.

• For δ

specification, revised maximum values for OSR = 24 to OSR = 256 conditions.

GROUP

• Revised entire row for t
t

LATENCY

• Added I

parameter.

specification.

BIAS

• Changed IADV_D and ΣIADR_D values.

In section Temperature sensor, Table 21 :

• Changed TACC values.

• Removed ITEMP_SENS spec item.

In section LFAST interface timing diagrams, Figure 12, "|ΔVOD|" changed to "|VOD|".
In section LFAST and MSC /DSPI LVDS interface electrical characteristics, Table 24, the max.

value for Rise/ Fall time specs changed from 4.0 to 5.7 ns.
In section LFAST PLL electrical characteristics, Table 25, ΔPER

value to 550 (was blank) and Max value to blank (was 400).
In section Recommended power transistors, Table 27, added the specification for VC.
In section Power management integration :

• In Figure 17 :

• Changed "n x CLV" to "CLV".

• Changed C

• In Table 28 :

• Changed the first footnote for CHV_PMC to have the same footnote number as the first
footnote for CLV as they were identical.

• Modified Minimum V

, GAIN = 16 condition min value to 55 dB (was 60).

SE150

, GAIN = 16 condition min value to 54 dB (was 59).

SE150

LATENCY

HV_ADC_S

, t

SETTLING

to C

HV_ADC_SAR

DD_HV_ADV_SAR

, and t

ODRECOVERY

.

external capacitance and associated footnote.

Revision history

specifications. Footnote added to

specification, changed Nominal

EYE

Added section Regulator example for the NJD2873 transistor.
Added section Regulator example for the 2SCR574d transistor.
In section Device voltage monitoring, Table 29 :

• Updated following specs:

• LVD_core_hot

• LVD_core_cold

• HVD_core

• LVD_HV

• HVD_HV

• LVD_IO

• LVD_SAR

• Removed following specs:

• LVD_FLASH

• HVD_FLASH

• LVD_MSC_3V3

• LVD_MSC_5V0

• LVD_FEC_5V0

• LVD_JTAG

• HVD_SAR

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 93

Revision history

Table 61. Revision history

Revision Date Description of changes

• LVD_SD

• HVD_SD

• Corrected Voltage detector threshold crossing assertion Unit.

In section Flash memory program and erase specifications, Table 30 :

• Removed parenthetical phrase from table title.

• Made overall updates to spec values.

• Removed footnote 7.

In section Flash memory Array Integrity and Margin Read specifications, Table 31 :

• Removed parenthetical phrase from table title.

• Made overall updates to spec values.

In section Flash memory module life specifications, Table 32, removed parenthetical phrase from
table title.

In section Flash memory AC timing specifications, Table 33, removed parenthetical phrase from
table title.

Added section Flash read wait state and address pipeline control settings.
In section Power management integration, Table 28, changed the footnotes for t

have the same footnote number as they were identical.
In section DSPI timing with CMOS and LVDS, Table 39, LVDS (Master mode) specification:

changed Max usuable frequency to 40 MHz (was 33 MHz).
In section DSPI CMOS master mode – classic timing :

• Added NOTE.

• In Table 40, changed PCS strobe timing values.

Min values to

TCYC

In section DSPI CMOS master mode – modified timing :

• Added NOTE.

• In Table 41, changed PCS strobe timing values.

In section DSPI LVDS master mode – modified timing, Table 42, changed significant digits for some
values.

In section DSPI master mode – output only :

• Modified format paragraphs leading the tables. Removed NOTE.

• In Table 43, changed the t

strong drive value and tHO LVDS value.

CSV

• In Table 44, changed significant digits for some values.

In section FEC timing, corrected the title of MII-lite and RMII serial management channel timing
subsections.

In section MII-lite transmit signal timing (TXD[3:0], TX_EN, TX_ER, TX_CLK), Table 47, modified
footnote for output parameters.

In section RMII serial management channel timing (MDIO and MDC), added Note on reference for
timing specifications.

In section RMII transmit signal timing (TXD[1:0], TX_EN), Table 52, modified R6 max value.
In section UART timings, Table 53, removed 100 MHz specification.
"Package drawings" section renamed to Obtaining package dimensions, with package drawing

document numbers to search at the Freescale website. Drawings removed from this document.
In section Thermal characteristics :

• Added table for 144 LQFP.

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

94 NXP Semiconductors

Table 61. Revision history (continued)

Revision Date Description of changes

• Moved table for 176 LQFP before 252 MAPBGA and updated table.

• Replaced table for 252 MAPBGA with two separate tables for package with full solder balls
and package with 16 removed balls.

In section Ordering information, replaced the table.

3 09/2015 On the cover page:

• Changed doctype from "Data Sheet: Product Preview" to "Data Sheet: Technical Data" at the
upper left corner.

• Changed statement on status of doc at the bottom of the page.

Removed "Preliminary" and "Non-Disclosure Agreement required" from footers on each page.
In section Electromagnetic Compatibility (EMC) removed content of entire section and replaced it

with statement: "EMC measurements to IC-level IEC standards are available from Freescale on
request."

In section Operating conditions :

• In Table 3

• For VDD_HV_PMC, removed the two footnotes.

• For VDDSTBY, added statement on ramp rate to footnote.

• For VSTBY_BO, removed Min value and added Max value.

In section DC electrical specifications :

• In Table 5 :

• IDD_LV spec:

• MPC5746R/MPC5745R Max value changed to 700 mA.

• MPC5743R/MPC5742R Max value changed to 610 mA.

• IDDSTBY_ON TA=40°C and TA=85°C values updated.

• IVDDA values updated.

Revision history

In section I/O pad specification, Table 6 Description for Input only pads, removed reference to
"Automotive" input.

In section Input pad specifications, Table 7 removed VIHAUTO, VILAUTO, VHYSAUTO, and
VDRFTAUTO specs and references to "Automotive" input in footnotes.

In section Output pad specifications :

• In Table 9, removed footnote for tR_F spec Parameter about transition time maximum value
approximation formula.

In section Reset pad (PORST, RESET) electrical characteristics :

• In Table 12 :

• Changed specs for VIH, VIL, and VHYS to VIH Reset, VIL Reset, and VHYS Reset
respectively.

• Added specs for VIH PORST, VIL PORST, VHYS PORST.

• Generally added Conditions and updated spec values. In the Conditions column,
changed all instances of "3.0 V" to "3.5 V".

In section Oscillator and FMPLL :

• In Table 13, for ΔPLL0LTJ spec, modified long term jitter Min and Max values.

• In Table 16, values updated.

• In Table 17, added spec for dfTRIM (IRC software trimming step).

In section ADC input description :

• In Table 18 :

• RPUPD 5KΩ spec Max value changed to 8.8KΩ.

In section Input equivalent circuit and ADC conversion characteristics :

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 95

Revision history

Table 61. Revision history (continued)

Revision Date Description of changes

• In Table 19 :

• In the SNR, THD, SINAD, and ENOB rows Conditions, changed "50 kHz" to "125 kHz".
Modified footnote to ENOB

• In IDD_VDDA and IDD_VDDR rows, modified values.

• In VBG_REF row's Conditions, added "INPSAMP=0xFF"

• Added NOTE "For spec complaint operation, do not expose clock sources, including crystal
oscillator, IRC, PLL0, and PLL1 on the CLKOUT pads while the SAR ADC is converting."

• Added NOTE: "The ADC performance specifications are not guaranteed if two or more ADCs
simultaneously sample the same shared channel".

In section S/D ADC :

• In Table 20 :

• For THD

• For I

ADV_D

In section LFAST and MSC /DSPI LVDS interface electrical characteristics :

• After table Table 24 added NOTE "For optimum LVDS performance, it is recommended to set
the neighbouring GPIO pads to use Weak Drive".

In section Device voltage monitoring :

• In Table 29 :

• For LVD_core_hot, LVD_HV, and LVD_IO specs, removed the untrimmed Rising
voltage and Falling voltage rows.

• For LVD_core_hot, changed Mask Opt. value to "No".

GAIN = 16, updated Min value.

DIFF333

, updated Max value.

In section Regulator example for the 2SCR574d transistor, figure "Regulator example", changed “5V
or Vcollector” to “3.3V or Vcollector”.

In section DSPI CMOS master mode – classic timing, Table 40 :

• Changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF".

• In tSUI and tHI specs' footnote, removed reference to "Automotive" thresholds.

In section DSPI CMOS master mode – modified timing, Table 41 :

• Changed tSDC spec's Condition SCK drive strength from "0 pF" to "0 to 50 pF".

• In tSUI and tHI specs' footnote, removed reference to "Automotive" thresholds.

In section DSPI master mode – output only, Table 44, changed tSDC spec's Condition SCK drive
strength from "0 pF" to "0 to 50 pF".

Added section eMIOS timing.
In section Ordering information, Table 60 :

• Updated Part Numbers.

• Updated Emulation device footnote.

4

03/2016 In section Block diagram, Figure 2 :

• "DECIM" changed to "DECFILTER".

• "SIPI" changed to "Zipwire".

• I/O lines added to Zipwire, SIUL2, REACM, eTPU, eMIOS, IGF, and XOSC.

In section Absolute maximum ratings table "Absolute maximum ratings", removed I
added I

MAXSEG

spec.

IOMAX

spec and

In section Operating conditions table "Device operating conditions":

• For the FEC I/O supply voltage, MSC I/O supply voltage, and JTAG I/O supply voltage specs,
removed the LVD enabled/disabled distinction.

• Added footnote to I

MAXSEG

.

In section I/O pad current specifications :

Table continues on the next page...

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

96 NXP Semiconductors

Table 61. Revision history (continued)

Revision Date Description of changes

• Modified the descriptions in the two paragraphs after the tables.

• Removed the third paragraph after the tables and the first Note.

Added section DSPI CMOS slave mode.
In section Ordering information table "Ordering Information", changed Part Numbers for the 176

LQFP PD and the ED.

5 10/2016 Editorial updates.

In section Operating conditions table "Device operating conditions" added foootnote to
V

DD_HV_IO_JTAG

In section Input pad specifications table "I/O input DC electrical characteristics" for I
condition "VSS < VIN < V

In section ADC input description table "Analog Input Leakage and Pull-Up/Down DC electrical
characteristics" for ILK_AD added conditions "V
"V

SS_HV_ADV_SD

In section Recommended power transistors table "Recommended operating characteristics" for
I

changed the parameter from "Minimum peak collector current" to "Maximum DC collector

CMaxDC

current".
In section SAR ADC table "ADC conversion characteristics":

• Removed the condition for t

• Removed the Min and added the formula (6.02*ENOB) + 1.76 for SINAD.

• Changed the Min value from 650 to 700 for t

.

< VIN < V

DD_HV_IO*

DD_HV_ADV_SD

"

sample

".

SS_HV_ADV_SAR

.

.

conv

< VIN < V

Revision history

LKG

DD_HV_ADV_SAR

added

" and

In section S/D ADC table "SDn ADC electrical specification":

• Removed ZIN specification

• Added Z

• For R

BIAS

DIFF

:

, ZCM, and ΔV

specifications

INTCM

• Changed Parameter description from "Bias resistance" to "Bare bias resistance"

• Changed Min from 100 kΩ to 110 kΩ

• Changed Typ from 125 kΩ to 144 kΩ

• Changed Max from 160 kΩ to 180 kΩ

In section Flash memory AC timing specifications table "Flash memory AC timing specifications" for
t

:

psus

• Changed Typical from 7 μs plus four system clock periods to 9.4 μs plus four system clock
periods

• Changed Max from 9.1 μs plus four system clock periods to 11.5 μs plus four system clock
periods

6

05/2017 Changed Freescale to NXP throughout the datasheet.

In Ordering information added rows for SPC5746RK1MLU3, SPC5745RK1MMT5 and
SPC5743RK1MLU5.

In Table 3 added footnote in V
In Table 28 for the rowset C

DD_HV_PMC

changed the Minimum and Typical values.

HV_FLA

SPC5746R Microcontroller Data Sheet, Rev. 6, 06/2017

NXP Semiconductors 97

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Document Number MPC5746R

Revision 6, 06/2017