Datasheet MPC2106SG66, MPC2107, MPC2107SG66, MPC2105SG66, MPC2106 Datasheet (Motorola)

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Page 1

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

Advance Information

256KB and 512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

The MPC2104/5/6/7 are des igned to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications. These products utilize synchronous or asynchronous data RAMs.

The MPC2104, MPC2105, and MPC2106 utilize synchronous BurstRAMs. The modules are configured as 32K x 72, 64K x 72, and 128K x 72 bits in a 182 (91 x 2) pin DIMM format. The MPC2104 uses four of Motorola’s 5 V 32K x 18; the MPC2105 uses four of the 5 V 64K x 18; the MPC2106 uses eight of the 5 V 64K x 18. For tag bits, a 5 V cache ta g RA M configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits is used.

Bursts can be initiated with the ADS

signal. Subsequent burst addresses are

generated internal to the BurstRAM by the CNTEN

signal.

Write cycles are internally self timed and are initiated by the rising edge of the clock (CLKx) inputs. Eight write enables are provided for byte write control.

The MPC2107 utilizes asynchronous data RAMs. The module is configured as 32K x 64 in the same 182 pin DIMM format. Again, 5 V cache tag RAMs configured as 16K x 12 for tag field plus 16K x 2 for valid and dirty status bits are used. Burst capability is provided in that two burst addresses bypass the address latch.

Presence detect pins are available for auto configuration of the cache control. A serial EEPROM is optional to provide more in–depth description of the cache module. This EEPROM will be available on future revisions of the module family.

The module family pinout will support 5 V and 3.3 V components for a clear path to lower voltage and power savings. Both power supplies must be connected.

All of these cache modules are plug and pin compatible with each other.

• PowerPC–style Burst Counter on Chip (MPC2104/5/6)

• Flow–Through Data I/O (MPC2104/5/6)

• Plug and Pin Compatibility of entire Module Family

• Multiple Clock Pins for Reduced Loading

• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible (MPC2104/5/6)

• Three State Outputs

• Byte Write Capability

• Fast Module Clock Rates: Up to 66 MHz

• Fast SRAM Access Times: 10 ns for Tag RAM Match

9 ns for Data RAM (MPC2104/5/6)

15 ns for Data RAM (MPC2107)

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

• 182 Pin Card Edge Module

• Burndy Connector, Part Number: ELF182JSC–3Z50

BurstRAM is a trademark of Motorola. PowerPC is a trademark of International Business Machines Corp.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Order this document

by MPC2104/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MPC2104 MPC2105 MPC2106 MPC2107

11/8/95

 Motorola, Inc. 1995

Page 2

PIN ASSIGNMENT

182–LEAD DIMM

TOP VIEW – CASE TBD

PD1/IDSDATA

PD3 DH31 DH29 DH27 DH25 VCC3

CWE3

DH23 DH21 DH18

DH16

CWE2

DH14 DH13 VCC5 DH10

DH8

CWE1

DH6 VCC3

DH4

CLK0

DH1

CWE0

DL31 DL30

DL29 DL27 DL25

VCC5

CWE7

DL23 DL21 DL19

DL17

92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

PD0/IDSCLK PD2 DH30 DH28 DH26 DH24 VCC3 DP3 DH22 DH20 DH19 V

DH17 DP2 DH15 DH12 VCC5 DH11 DH9 DP1 DH7 VCC3 DH5 DH3 DH2 DH0 DP0 V

CLK1 VSS DL28 DL26 DL24 DP7 VCC5 DL22 DL20 DL18 DL16 V

DP6

134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182

43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

CWE6

DL15 DL13

DL10

DL8

CWE5

DL6

VCC3

DL5 DL2

CLK3

CLK4

CWE4

ALE

VCC3

ADDR1

RESERVED

CNTEN0 CNTEN1

VCC5 VCC5

A27 A24 A22 A20

A18 A16 A15 A14

VCC3

A10

A8 A6

SS A4

A2 A1

BURSTMODE

VCC5

VALIDIN

TWE

STANDBY

DIRTYOUT

DL14 DL12 DL11 V

DL9 DP5 DL7 DL4 VCC3 DL3 DL1 DL0 V

CLK2 V

DP4 COE0 COE1 VCC3 ADDR0 RESERVED ADS0 ADS1 VCC5 VCC5 A28 A26 A25 A23 V

A21 A19 A17 A13 VCC3 A12 A11 A9 V

A7 A5 A3 A0 VCC5 TCLR MATCH TOE DIRTYIN V

NOTES:

1. VCC5 and VCC3 must be connected on all modules.

MPC2104•MPC2105•MPC2106•MPC2107 2

MOTOROLA FAST SRAM

Page 3

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

MPC2104/MPC2105 BLOCK DIAGRAM

MCM67Mx18

A15

G E

DQ0 – DQ8

A13

STANDBY

TSC

COE0

TSP

A14 – A26

VCC5 via 100

Ω

A2 – A14

A14 – A26

BAA

ADS0

CWE0

A2 – A12

TCLR

TWE

CLK2

MATCH

DIRTYOUT

VALIDIN

DIRTYIN

TOE

TAG: 16K x 12 + V + D

A13

RESET

A0 – A12

TAG

, TAD, E2

SFUNC, SG TDQ0 – TDQ10 TDQ11

SW TW K

MATCH

DIRTYQ

VALIDD DIRTYD TG

CLK3 = NC CLK4 = NC ALE = NC ADS1

= NC

CNTEN1

= NC

COE1

= NC ADDR0 = NC ADDR1 = NC PD2 = NC PD3

X24C00

(OPTIONAL)

SCL SDA

PD0/IDSCLK PD1/IDSDATA

DQ9 – DQ17

CLK0 DH0 – DH7 + DP0 DH8 – DH15 + DP1

CWE1

CNTEN0

A27

A28

MCM67Mx18

A15

G E

DQ0 – DQ8

TSC

TSP

A2 – A14

BAA

CWE2

DQ9 – DQ17

CLK0 DH16 – DH23 + DP2 DH24 – DH31 + DP3

CWE3

MCM67Mx18

A15

G E

DQ0 – DQ8

TSC

TSP

A2 – A14

BAA

CWE4

DQ9 – DQ17

CLK1 DL0 – DL7 + DP4 DL8 – DL15 + DP5

CWE5

MCM67Mx18

A15

G E

DQ0 – DQ8

TSC

TSP

A2 – A14

BAA

CWE6

DQ9 – DQ17

CLK1 DL16 – DL23 + DP6 DL24 – DL31 + DP7

CWE7

’244

TT1, WTD, E1

TAH, PWRDN

VCC5 via 100

Ω

WTQ

VALIDQ

CCQ

VCC3 NC

256KB 512KB EEPROM EEPROM

256KB 512KB

J5 no stuff 0

Ω

no stuff 0

Ω

J4 0

Ω

no stuff no stuff

J3 0

Ω

no stuff no stuff

J2 0

Ω

no stuff no stuff no stuff

J1 0

Ω

no stuff 0

Ω

no stuff

J0 no stuff 0

Ω

no stuff 0

Ω

Note: MPC2104 utilizes 32K x 18 BurstRAMs. MPC2105 utilizes 64K x 18 BurstRAMs.

Page 4

MPC2104•MPC2105•MPC2106•MPC2107 4

MOTOROLA FAST SRAM

MPC2106 BLOCK DIAGRAM

64K X 18 BURST

G E

DQ0 – DQ8

STANDBY

TSC

COE0

A13 – A26

A0 – A15

A13 – A28

BAA

ADS0

CWE0

A0 – A11

TCLR

TWE

CLK2

MATCH

DIRTYOUT

VALIDIN

DIRTYIN

TOE

TAG: 16K x 12 + V + D

A0 – A13

RESET

TAH, TAG, TAD

SFUNC, SGTDQ0 – TDQ11

SW TW K

MATCH

DIRTYQ

VALIDD DIRTYD TG

ALE = NC ADDR0 = NC ADDR1 = NC PD2 = NC PD3

X24C00

(OPTIONAL)

SCL SDA

PD0/IDSCLK PD1/IDSDATA

DQ9 – DQ17

CLK0 DH0 – DH7 + DP0 DH8 – DH15 + DP1

CWE1

CNTEN0

64K X 18 BURST

G E

DQ0 – DQ8TSC

A0 – A15

BAA

CWE2

DQ9 – DQ17

CLK1 DH16 – DH23 + DP2 DH24 – DH31 + DP3

CWE3

64K X 18 BURST

G E

DQ0 – DQ8

TSC

A0 – A15

BAA

CWE4

DQ9 – DQ17

CLK3 DL0 – DL7 + DP4 DL8 – DL15 + DP5

CWE5

64K X 18 BURST

G E

DQ0 – DQ8

TSC

A0 – A15

BAA

CWE6

DQ9 – DQ17

CLK4 DL16 – DL23 + DP6 DL24 – DL31 + DP7

CWE7

’244

TT1, WTD

PWRDN

VCC5 via 100

Ω

WTQ

, VALIDQ

CCQ

VCC3 NC

1M EEPROM 1M

J1 0

Ω

no stuff

J0 0

Ω

no stuff

A12

64K X 18 BURST

G E

DQ0 – DQ8

TSC

A0 – A15

BAA

CWE0

DQ9 – DQ17

CLK0 DH0 – DH7 + DP0 DH8 – DH15 + DP1

CWE1

64K X 18 BURST

G E

DQ0 – DQ8

TSC

A0 – A15

BAA

CWE2

DQ9 – DQ17

CLK1 DH16 – DH23 + DP2 DH24 – DH31 + DP3

CWE3

64K X 18 BURST

G E

DQ0 – DQ8

TSC

A0 – A15

BAA

CWE4

DQ9 – DQ17

CLK3 DL0 – DL7 + DP4 DL8 – DL15 + DP5

CWE5

64K X 18 BURST

G E

DQ0 – DQ8

TSC

A0 – A15

BAA

CWE6

DQ9 – DQ17

CLK4 DL16 – DL23 + DP6 DL24 – DL31 + DP7

CWE7

COE1

ADS1

CNTEN1

A12

A13 – A26

A0 – A11

TCLR

TWE

CLK2

MATCH DIRTYOUT

VALIDIN

DIRTYIN

TOE

TAG: 16K x 12 + V + D

A0 – A13

RESET

TAH, TAG, TAD

SFUNC, SGTDQ0 – TDQ11

SW TW K

MATCH

DIRTYQ

VALIDD DIRTYD TG

TT1, WTD

PWRDN

VCC5 via 100

Ω

WTQ

, VALIDQ

CCQ

VCC3 NC

A12

Note: All 64K X 18 TSP signals are tied to VCC via a 100 Ω resistor. Edge connector A28 connects to the 64K x 18 A0; edge

connector A27 connects to the 64K x 18 A1.

PAL

PA12

PA12L

Page 5

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

MPC2107 BLOCK DIAGRAM

MCM6206

G E

STANDBY

COE0

A14 – A26

A2 – A14

A14 – A26

ADDR0

CWE0

A2 – A13

TCLR

TWE

CLK2

MATCH

DIRTYOUT

VALIDIN

DIRTYIN

TOE

TAG: 16K x 12 + V + D

A0 – A12

RESET

TAH, TAG, TAD

SFUNC, SGTDQ0 – TDQ11

SW TW K

MATCH

DIRTYQ

VALIDD DIRTYD TG

CLK0, 1, 3, 4 = NC ADS0

, ADS1 = NC

CNTEN0

, CNTEN1 = NC A27, A28 = NC DP0 – DP7 = NC BURSTMODE = NC PD2 PD3 = NC

X24C00

(OPTIONAL)

SCL SDA

PD0/IDSCLK PD1/IDSDATA

DQ0 – DQ7

DH0 – DH7

ADDR1

MCM6206

’373

TT1, WTD, E1

E2, PWRDN

VCC5 via 100

Ω

WTQ

, VALIDQ

CCQ

VCC3 NC

256KB EEPROM 256KB

J3 0

Ω

no stuff

J2 0

Ω

no stuff

J1 0

Ω

no stuff

MCM6206

ALE

G E

A2 – A14

CWE1

DQ0 – DQ7

DH8 – DH15

G E

A2 – A14

CWE2

DQ0 – DQ7

DH16 – DH23

G E

A2 – A14

CWE3

DQ0 – DQ7

DH24 – DH31

G E

A2 – A14

CWE4

DQ0 – DQ7

DL0 – DL7

COE1

G E

A2 – A14

CWE5

DQ0 – DQ7

DL8 – DL15

G E

A2 – A14

CWE6

DQ0 – DQ7

DL16 – DL23

G E

A2 – A14

CWE7

DQ0 – DQ7

DL24 – DL31

A13

Page 6

MPC2104•MPC2105•MPC2106•MPC2107 6

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

Pin Locations Symbol

Type Description

68, 69, 70, 71, 73, 74, 75, 76,

78, 79, 80, 82, 83, 84, 85, 159, 160, 161, 162, 164, 165, 166, 167, 169, 170, 171, 173,

174, 175

A0 – A28 Input Address Inputs – (MSB:0, LSB:28)

62 ADDR0 Input Least significant address bit when asynchronous Data RAMs are used.

153 ADDR1 Input Next to least significant address bit when asynchronous Data RAMs are used.

30, 56, 117, 146, 148 CLK0 – CLK4 Input Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for Data RAMs only .

For MPC2106 use all the clocks. For MPC2104 or MPC2105 use CLK0–CLK2 only. For MPC2107 use CLK2 only.

4, 5, 6, 7, 10, 11, 12, 14, 16, 17, 19, 20, 22, 24, 25, 26, 27, 95, 96, 97, 98, 101, 102, 103,

105, 107, 108, 110, 111, 113,

115, 119

DH0 – DH31 I/O High Data Bus – (MSB:0, LSB:31)

32, 33, 34, 37, 38, 39, 40, 43, 44, 45, 47, 49, 50, 52, 53, 54, 121, 122, 124, 125, 126, 129, 130, 131, 133, 135, 136, 138,

139, 141, 143, 144

DL0 – DL31 I/O Low Data Bus – (MSB:0, LSB:31)

9, 15, 21, 28, 35, 42, 48, 58 DP0 – DP7 I/O Data Parity Bits – (MSB:0, LSB:7)

3, 94 PD2, PD3 Output Presence detect bits.

2 PD0/IDSCLK Input Presence detect bit 0/EEPROM serial clock. (EEPROM option only.)

93 PD1/IDSDATA I/O Presence detect bit 1/EEPROM serial data. (EEPROM option only.)

64, 65 ADS0, ADS1 Input Data RAM Address Strobe – For MPC2104 or MPC2105 use ADS0 only. For

MPC2106 use ADS0

, ADS1.

151 ALE Input Data RAM Address Latch Enable – Use for asynchronous Data RAM only.

155, 156 CNTEN0,

CNTEN1

Input Data RAM Count Enables – For MPC2104 or MPC2105 use CNTEN0 only. For

MPC2106 use CNTEN0

, CNTEN1.

59, 60 COE0,

COE1

Input Data RAM Output Enables – For MPC2104 or MPC2105 use COE0 only. For

all others use COE0

, COE1.

100, 106, 112, 120,

128, 134, 140, 150

CWE0 – CWE7 Input Data RAM Write Enables – (MSB:0, LSB:7)

87 TCLR Input Tag RAM clear.

88 MATCH Output Tag RAM active high match indication. 178 VALIDIN Input Tag RAM valid bit. 179 TWE Input T ag RAM write enable.

89 TOE Input Tag RAM output enable.

90 DIRTYIN Input Dirty input bit. 181 DIRTYOUT Output Dirty output bit. 180 STANDBY Input Standby pin. Reduces standby power consumption.

176, 63, 154 RESERVED Reserved pin.

8, 23, 51, 61, 77, 99, 114,

142, 152, 168

VCC3 Input + 3.3 V power supply. Must be connected.

18, 36, 66, 67, 86, 109, 127,

157, 158, 177

VCC5 Input + 5 V power supply. Must be connected.

1, 13, 29, 31, 41, 46, 55, 57,

72, 81, 91, 92, 104, 116, 118, 123, 132, 137, 145,

147, 149, 163, 172, 182

Input Ground

176 BURSTMODE Input Burstmode. 0 = Linear, 1 = Interleaved.

Page 7

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

DATA RAM MCM67M518, MCM67M618 SYNCHRONOUS TRUTH TABLE (See Notes 1, 2, and 3)

STANDBY

ADS0 CNTEN0 CWEx CLKx Address Used Operation

H L X X L–H N/A Deselected

L L X L L–H External Address Write Cycle, Begin Burst L L X H L–H External Address Read Cycle, Begin Burst X H L L L–H Next Address Write Cycle, Continue Burst X H L H L–H Next Address Read Cycle, Continue Burst X H H L L–H Current Address Write Cycle, Suspend Burst X H H H L–H Current Address Read Cycle, Suspend Burst

NOTES:

1. X means Don’t Care.

2. All inputs except COE

must meet set–up and hold times for the low–to–high transition of clock (CLK0 – CLK4).

3. Wait states are inserted by suspending burst.

ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

Operation

COE I/O Status

Read L Data Out (DQ0 – DQ8) Read H High–Z Write X High–Z — Data In

Deselected X High–Z

NOTES:

1. X means Don’t Care.

2. For a write operation following a read operation, COE

must be high before the input

data required set–up time and held high through the input data hold time.

DATA RAM MCM6206 ASYNCHRONOUS TRUTH TABLE (See Notes 1 and 2)

STANDBY

COE0, COE1 CWE0 – CWE7 Operation I/O Status

H X X Deselected High–Z

L H H Output Disabled High–Z L L H Read Data Out L X L Write High–Z

NOTES:

1. X means Don’t Care.

2. For a write operation following a read operation, COE0

, and COE1 must be high before the input data required set–up time, and held high

through the input data hold time.

ABSOLUTE MAXIMUM RATINGS (Voltages Referenced to V

= 0 V)

Rating

Symbol Value Unit

Power Supply Voltage V

– 0.5 to + 7.0 V

Voltage Relative to V

Vin, V

out

– 0.5 to VCC + 0.5 V

Output Current (per I/O) Data RAM

Tag

out

± 30 ± 20

Power Dissipation P

8.1 W

Temperature Under Bias T

bias

– 10 to + 85 °C

Operating Temperature T

0 to +70 °C

Storage Temperature T

stg

– 55 to + 125 °C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high–impedance circuit.

This BiCMOS memory circuit has been designed to meet the dc and ac specifications shown in the tables, after thermal equilibrium has been established.

This device contains circuitry that will ensure the output devices are in High–Z at power up.

Page 8

MPC2104•MPC2105•MPC2106•MPC2107 8

MOTOROLA FAST SRAM

DC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

RECOMMENDED OPERATING CONDITIONS

(Voltages referenced to VSS = 0 V)

Parameter

Symbol Min Max Unit

Supply Voltage (Operating Voltage Range) V

4.75 5.25 V

Input High Voltage V

2.2 VCC + 0.3** V

Input Low Voltage V

– 0.5* 0.8 V

*VIL (min) = – 0.5 V dc; VIL (min) = – 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

**VIH (max) = VCC + 0.3 V dc; VIH (max) = VCC + 2.0 V ac (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

DC CHARACTERISTICS

Parameter Symbol Min Max Unit

Input Leakage Current (All Inputs, Vin = 0 to VCC) Data RAM

Tag

lkg(I)

— ± 1.0

± 5.0

µA

Output Leakage Current (COE = VIH, V

out

= 0 to VCC) Data RAM

Tag

lkg(O)

— ± 1.0

± 5.0

µA

TTL Output Low Voltage (IOL = + 8.0 mA) V

— 0.4 V

TTL Output High Voltage (IOH = – 4.0 mA) V

2.4 — V

POWER SUPPLY CURRENTS

Parameter Symbol Max Unit

AC Supply Current (COE = VIH, E = VIL, I

out

= 0 mA, All Inputs = VIL and VIH,

VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns) MPC2104

MPC2105 MPC2106 MPC2107

CCA

1480 1420 2840 1400

AC Standby Current (E = VIH, I

out

= 0 mA, All Inputs = VIL or VIH,

VIL = 0.0 V and VIH ≥ 3.0 V, Cycle Time ≥ 20 ns) MPC2104

MPC2105 MPC2106 MPC2107

SB1

620 700

1400

960

CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, T

= 25°C, Periodically Sampled Rather Than 100% Tested)

Parameter

Symbol Typ Max Unit

Input Capacitance (A13 – A28)

(Data RAM Control Pins)

(CLK0 – CLK4)

(Tag Control Pins)

—

15 20 10

Tag Output Capacitance (MATCH, DIRTYOUT) C

out

— 7 pF

Data RAM Input/Output Capacitance (DH0 – DH31, DL0 – DL31) C

I/O

6 8 pF

Tag Input/Output Capacitance (A0 – A11) C

I/O

— 7 pF

Page 9

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

DATA RAMs AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 1A Unless Otherwise Noted. . . . . . . . . . . .

SYNCHRONOUS DATA RAMs READ/WRITE CYCLE TIMING (See Notes 1, 2, 3, and 7)

MPC2104 MPC2105 MPC2106

Parameter Symbol Min Max Unit Notes

Cycle Time t

KHKH

15 — ns

Clock Access Time t

KHQV

— 9 ns 4

Output Enable to Output Valid t

GLQV

— 5 ns

Clock High to Output Active t

KHQX1

6 — ns

Clock High to Output Change t

KHQX2

3 — ns

Output Enable to Output Active t

GLQX

0 — ns

Output Disable to Q High–Z t

GHQZ

2 6 ns

Clock High to Q High–Z t

KHQZ

— 6 ns

Clock High Pulse Width t

KHKL

5 — ns

Clock Low Pulse Width t

KLKH

5 — ns

Setup Time Address t

AVKH

7.5 — ns 5, 6

Setup Times: Address Status

Data In

Write

Address Advance

Chip Enable

SVKH

DVKH

WVKH

BAVVKH

EVKH

2.5 — ns 5

Hold Times: Address

Address Status

Data In

Write

Address Advance

Chip Enable

KHAX

KHTSX t

KHDX

KHWX

KHBAX

KHEX

0.5 — ns 5

NOTES:

1. In setup and hold times, W (write) refers to either one or both byte write enables LW

and UW.

2. All read and write cycle timings are referenced from CLK or COE

3. COE

is a don’t care when UW or LW is sampled low.

4. Maximum access times are guaranteed for all possible PowerPC external bus cycles.

5. This is a synchronous device. All addresses must meet the specified setup and hold times for

ALL

rising edges of CLK whenever TSP or

TSC

is low, and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for

ALL

rising edges of

CLK when the chip is enabled. Chip enable must be valid at each rising edge of clock for the device (when TSP

or TSC is low) to remain

enabled.

6. 5 ns of set–up delay is incurred in address buffers.

7. Applies to MPC2104, MPC2105, and MPC2106.

Page 10

MPC2104•MPC2105•MPC2106•MPC2107 10

MOTOROLA FAST SRAM

SYNCHRONOUS DATA RAM READ CYCLE

CLK1,

CLK0

ADS0

A(12, 13,

14 – 26)

(See Note 1)

CWE0

–

CWE7

STANDBY

CNTEN0

COE

DATA OUT

READ BURST READ

KHKH

KHKL

KLKH

A1 A2

AVKH

KHAX

KHQX1

GHQZ

KHQV

KHQZ

Q (A1)

Q (A2) Q (A2 + 1) Q (A2 + 2)

TSVKH

KHTSX

WVKH

KHWX

EVKH

KHEX

BAVKH

KHBAX

KHQV

GLQV

GLQX

KHQX2

NOTES:

1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106.

2. Q1 (A2) represents the first ouput from the external address A2; Q2 (A2) represents the next output data in the burst sequence with A2 as the base address.

Q (A2 + 3)

Page 11

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

SYNCHRONOUS DATA RAM WRITE CYCLE

CLK1,

CLK0

ADS0

A(12, 13,

14 – 26)

CWE0

–

CWE7

STANDBY

CNTEN0

DATA IN

SINGLE WRITE BURST WRITE

KHKH

KHKL

KLKH

A1 A2

AVKH

KHAX

D (A1)

D (A2) D (A2 + 1) D (A2 + 2)

WVKH

KHWX

EVKH

KHEX

BAVKH

KHBAX

NOTES:

1. Cache addresses used are: 14 – 26 for MPC2104 and MPC2107; 13 – 26 for MPC2105; and 12 – 26 for MPC2106.

2. COE0

= V

SVKH

KHTSX

AVKH

KHAX

D (A2 + 3)

DVKH

KHDX

Page 12

MPC2104•MPC2105•MPC2106•MPC2107 12

MOTOROLA FAST SRAM

AC OPERA TING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5% TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Reference Level 1.5 V. . . . . . . . . . . . . . . . . . . . . . . . . .

Output Load See Figure 1A Unless Otherwise Noted. . . . . . . . . . . .

ASYNCHRONOUS DATA RAMs READ CYCLE TIMING (See Notes 1 and 8)

MPC2107–15

Parameter Symbol Min Max Unit Notes

Cycle Time t

AVAV

15 — ns 2

Address Access Time t

AVQV

— 15 ns

Enable Access Time t

ELQV

— 15 ns 3

Output Enable Access Time t

GLQV

— 8 ns

Output Hold from Address Change t

AXQX

4 — ns 4, 5, 6

Enable Low to Output Active t

ELQX

4 — ns 4, 5, 6

Enable High to Output High–Z t

EHQZ

0 8 ns 4, 5, 6

Output Enable Low to Output Active t

GLQX

0 — ns 4, 5, 6

Output Enable High to Output High–Z t

GHQZ

0 7 ns 4, 5, 6

Power Up Time t

ELICCH

0 — ns

Power Down Time t

EHICCL

— 15 ns

NOTES:

1. W

is high for read cycle.

2. All timings are referenced from the last valid address to the first transitioning address.

3. Addresses valid prior to or coincident with E

going low.

4. At any given voltage and temperature, t

EHQZ

(max) is less than t

ELQX

(min), and t

GHQZ

(max) is less than t

GLQX

(min), both for a given device

and from device to device.

5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1B.

6. This parameter is sampled and not 100% tested.

7. Device is continuously selected (E

= VIL, COE0 = VIL).

8. Applies to MPC2107.

Page 13

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

ASYNCHRONOUS READ CYCLE 1 (See Note 7)

Q (DATA OUT)

A (ADDRESS)

DATA VALIDPREVIOUS DATA VALID

AVAV

AXQX

AVQV

ASYNCHRONOUS READ CYCLE 2 (See Note 3)

EHQZ

DATA VALID

GHQZ

AVAV

ELQX

ELQV

E (CHIP ENABLE)

Q (DATA OUT)

A (ADDRESS)

AVQV

GLQX

GLQV

G (OUTPUT ENABLE)

VCC SUPPLY

CURRENT

EHICCL

ELICCH

HIGH–Z HIGH–Z

Page 14

MPC2104•MPC2105•MPC2106•MPC2107 14

MOTOROLA FAST SRAM

ASYNCHRONOUS DATA RAMs WRITE CYCLE 1 (See Notes 1 and 2)

MPC2107–15

Parameter Symbol Min Max Unit Notes

Write Cycle Time t

AVAV

15 — ns 3

Address Set–up Time t

AVWL

0 — ns

Address Valid to End of W rite t

AVWH

12 — ns

Write Pulse Width t

WLWH

WLEH

12 — ns

Write Pulse Width, G High t

WLWH

WLEH

10 — ns 4

Data Valid to End of W rite t

DVWH

7 — ns

Data Hold Time t

WHDX

0 — ns

Write Low to Output High–Z t

WLQZ

0 7 ns 5,6,7

Write High to Output Active t

WHQX

5 — ns 5,6,7

Write Recovery Time t

WHAX

0 — ns

NOTES:

1. A write occurs during the overlap of E

low and W low.

2. If E

goes low coincident with or after W goes low, the output will remain in a high impedance state.

3. All timings are referenced from the last valid address to the first transitioning address.

4. If E

≥ VIH, the output will remain in a high impedance state.

5. At any given voltage and temperature, t

WLQZ

(max) is less than t

WHQX

(min), both for a given device and from device to device.

6. Transition is measured ±500 mV from steady–state voltage with load of Figure 1B.

7. This parameter is sampled and not 100% tested.

ASYNCHRONOUS WRITE CYCLE 1 (W Controlled, See Notes 1 and 2)

DATA VALID

DVWH

AVWL

AVWH

AVAV

WHAX

WLWH

WHDX

WLQZ

WHQX

HIGH–Z

A (ADDRESS)

(WRITE ENABLE)

(CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

WLEH

Page 15

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

ASYNCHRONOUS DATA RAMs WRITE CYCLE 2 (E Controlled, See Notes 1 and 2)

MPC2107–15

Parameter Symbol Min Max Unit Notes

Write Cycle Time t

AVAV

15 — ns 0

Address Setup Time t

AVEL

0 — ns

Address Valid to End of W rite t

AVEH

12 — ns

Enable to End of Write t

ELEH

ELWH

10 — ns 3, 4

Data Valid to End of W rite t

DVEH

7 — ns

Data Hold Time t

EHDX

0 — ns

Write Recovery Time t

EHAX

0 — ns

NOTES:

1. A write occurs during the overlap of E

low and W low.

2. All timings are referenced from the last valid address to the first transitioning address.

3. If E

goes low coincident with or after W goes low, the output will remain in a high impedance state.

4. If E

goes high coincident with or before W goes high, the output will remain in a high impedance state.

ASYNCHRONOUS WRITE CYCLE 2 (E Controlled, See Note 1)

EHDX

DVEH

EHAX

ELWH

ELEH

AVEL

AVEH

DATA VALID

AVAV

HIGH–Z

A (ADDRESS)

(WRITE ENABLE)

(CHIP ENABLE)

Q (DATA OUT)

D (DATA IN)

WLEH

Page 16

MPC2104•MPC2105•MPC2106•MPC2107 16

MOTOROLA FAST SRAM

T AG RAM

RESET FUNCTION TRUTH TABLE (See Notes 1 and 2)

TCLR

CLK TWE TAG VLD

out

DTY

out

MATCH TA Operation POWER

L L – H H High–Z L

(3)

High–Z Reset Status Active

L L – H L — — — — — — Not Allowed —

NOTES:

1. H = VIH, L = VIL, X = don‘t care, — = unrelated.

2. TOE

is X for this table.

READ FUNCTION TRUTH TABLE (See Notes 1, 2, and 3)

TOE

TWE CLK TAG VLDinDTYinWT

VLD

out

DTY

out

MATCH Operation

L H X D

OUT

— — — — — — D

OUT

Read Tag I/O

H X X High–Z — — — — — — — Tag I/O Disable

WRITE FUNCTION TRUTH TABLE (See Notes 1 and 2)

TOE

TWE CLK TAG VLDinDTYinWT

VLD

out

DTY

out

MATCH Operation

H L L – H D

— — — D

OUT

L Write Tag I/O

L L L – H — — — — — — — — Not Allowed

NOTES:

1. H = VIH, L = VIL, X = don‘t care, — = unrelated.

2. This table applies when RESET

and PWRDN are high.

3. D

OUT

in this case is the same as DIN. The input data is written through to the outputs during the write operation.

MATCH FUNCTION TRUTH TABLE (See Notes 1 through 4)

TOE

TWE TAG VLD

(4)

DTY

(4)

MATCH Operation

X X — — — — D

OUT

Selected

L H D

OUT

— — — L Read Tag I/O

H L D

L Write Tag I/O, Status Bits

H H TAG

L — — L Invalid Data – Dedicated Status Bits

H H TAG

H — — M Match – Dedicated Status Bits

NOTES:

1. H = VIH, L = VIL, X = don‘t care, — = unrelated.

2. M = high if TAGIN equals the memory contents at the address; M = low if TAGIN does not equal the ocntents at that address.

3. PWRDN

and RESET are high for this table. OES and CLK are X.

4. This column represents the stored memory cell data for the given status bit at the selected address.

Page 17

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

T AG RAM AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 V ± 5%, TA = 0 to + 70°C, Unless Otherwise Noted)

Input Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . . . .

Input Pulse Levels 0 to 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input Rise/Fall Time 3 ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output Timing Measurement Reference Level 1.5 V. . . . . . . . . . . . .

Output Load Figure 1A Unless Otherwise Noted. . . . . . . . . . . . . . . .

TAG RAM READ CYCLE (See Notes 1 through 4)

Tag RAM

Parameter Symbol Min Max Unit Notes

Clock Access Time t

KHQV

— 10 ns

Output Enable to Output Valid t

GLQV

— 8 ns

Output Enable to Output Active t

GLQX

0 — ns

Output Disable to Q High–Z t

GHQZ

1 6 ns

Status Bit Hold from Address Change t

AXSX

3 — ns

Address Access Time Status Bits t

AVSV

— 10 ns

Tag Bit Hold from Address Change t

AVQX

3 — ns

Address Access Time Tag Bits t

AVQV

— 12 ns

NOTES:

1. Set–up and hold times, W (write) referes to TWE

2. A read cycle is defined by TWE

high. A write cycle is defined by TWE low.

3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.

4. Tag reads are asynchronous.

TAG RAM WRITE CYCLE (See Notes 1 through 4)

Tag RAM

Parameter Symbol Min Max Unit Notes

Cycle Time t

KHKH

15 — ns

Clock High Pulse Width t

KHKL

4.5 — ns

Clock Low Pulse Width t

KLKH

4.5 — ns

Clock High to Output Active t

KHQX

1.5 — ns

Set–up Times Address

Write

AVKH

WVKH

3 — ns

Hold Times Address

Write

KHAX

KHWX

1.5 — ns

Status Output Hold t

KHSX

0 — ns

Clock High to Status Bits Valid t

KHSV

— 9 ns

NOTES:

1. Set–up and hold times, W (write) referes to TWE

2. A read cycle is defined by TWE

high. A write cycle is defined by TWE low.

3. Maximum access times are guaranteed for all possible MC68040 and PowerPC external bus cycles.

4. Tag writes are synchronous.

Page 18

MPC2104•MPC2105•MPC2106•MPC2107 18

MOTOROLA FAST SRAM

TAG RAM WRITE AND READ CYCLES

CLK

A(12, 13,

TWE

A0 – A11

TOE

VALID VALID VALID

VALID INPUT VALID OUTPUT

VALID

OUTPUT

VALID

OUTPUT

VALID

VALID VALID

VALID V ALID

AVKH

KHAX

STATUS WRITE TAG READ

TAG WRITE AFTER READ

WVKH

KHWX

WVKH

KHWX

KHSV

KHSX

WVKH

KHWX

KHQV

KHQX

AVSV

GHQZ

GLQX

AXSX

VALIDIN

DIRTYIN

DIRTYOUT

KHKL

KLKH

KHKH

GLQV

(See Note 2)

14–26)

(See Note 3)

AVQV

AXQX

AVKH

KHAX

(See Note 1)

AVSV

AXSX

NOTE:

1. Transition is measured plus or minus 200 mV from steady state.

2. TCLR = High.

TAG READ

AFTER WRITE

3. Cache addresses used are: 14–26 for MPC2004 and MPC2007; 13–26 for MPC2005; 12–26 for MPC2006 and MPC2009.

Page 19

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

TAG RAM MATCH CYCLE

Tag RAM

Parameter Symbol Min Max Unit Notes

Clock High Write to MA TCH Invalid t

KHML

— 7 ns

Clock High Read to MATCH Valid t

KHMV

— 10 ns

Address Valid to MATCH Valid t

AVMV

— 10 ns

MATCH Valid Hold from Address Change t

AXMX

2 — ns

TOE Low to MATCH Invalid t

GLML

— 7 ns

TOE High to MATCH Valid t

GHMX

— 8 ns

TAG RAM RESET (TCLR) CYCLE

Tag RAM

Parameter Symbol Min Max Unit Notes

TCLR Set–up Time t

STC

4 — ns

TCLR Hold Time t

HTC

1 — ns

Status Bit Reset Time t

SRST

— 60 ns

Status Bit Hold from TCLR Low t

SHRS

2 — ns

TCLR Low to MATCH Invalid t

RSML

— 10 ns

TCLR High to MATCH Valid t

RSMV

— 100 ns

TCLR Low to TAG High–Z t

RSQZ

— 10 ns

TCLR High to TAG Active t

RSQX

— 100 ns

STANDBY Set–up to TCLR Low t

PDSR

30 — ns

TCLR High to TWE Low t

RHWX

80 — ns

AC TEST LOADS

OUTPUT

Z0 = 50

Ω

VL = 1.5 V

Figure 1A Figure 1B

5 pF

+5 V

OUTPUT

255

Ω

480

Ω

TIMING LIMITS

The table of timing values shows either a minimum or a maximum limit for each parameter. Input requirements are specified from the external system point of view. Thus, address setup time is shown as a minimum since the system must supply at least that much time (even though most devices do not require it). On the other hand, responses from the memory are specified from the device point of view. Thus, the access time is shown as a maximum since the device never provides data later than that time.

Page 20

MPC2104•MPC2105•MPC2106•MPC2107 20

MOTOROLA FAST SRAM

MATCH

CLK

A(12, 13,

TAG RAM MATCH CYCLE

VALID

MATCH VALID

VALID

AVMV

AXMX

KHWX

WVKH

TWE

A0 – A11

TOE

VALID ADDRESS

VALID MATCH DATA FROM: PROCESSOR PROCESSORTAG RAM

VALID

(14–26)*

GLML

GLMX

KHML

KHMV

* Cache addresses used are: 14–26 for MPC2004 and MPC2007; 13–26 for MPC2005; 12–26 for MPC2006.

Page 21

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

MATCH

CLK

HTC

TAG RAM TCLR FUNCTION

* Transition is measured plus or minus 200 mV from steady state.

RSQX

SRST

STC

WVKH

RSQZ*

RHWX

A0 – A11

TWE

DIRTYOUT

TCLR

VALID

SHRS

RSMV

Page 22

MPC2104•MPC2105•MPC2106•MPC2107 22

MOTOROLA FAST SRAM

ORDERING INFORMATION

(Order by Full Part Number)

MPC 210x XX XX

Motorola Memory Prefix Part Number

Full Part Numbers — MPC2104SG66

MPC2105SG66 MPC2106SG66 MPC2107SG15

Speed (66 = 66 MHz, synchronous)

Package (SG = Gold Pad SIMM)

(15 = 15 ns asynchronous)

MPC2104 = 256KB, synchronous MPC2105 = 512KB, synchronous MPC2106 = 1MB, synchronous MPC2107 = 256KB, asynchronous

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Af firmative Action Employer.

Page 23

MPC2104•MPC2105•MPC2106•MPC2107

MOTOROLA FAST SRAM

Page 24

MPC2104•MPC2105•MPC2106•MPC2107 24

MOTOROLA FAST SRAM

How to reach us: USA/ EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; T atsumi–SPD–JLDC, Toshikatsu Otsuki,

P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315

MFAX: RMF AX0@email.sps.mot.com – T OUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting K ok Road, T ai Po, N.T., Hong Kong. 852–26629298

MPC2104/D

*MPC2104/D*

◊