Datasheet MPC2005, MPC2004 Datasheet (Motorola)

MPC2004•MPC2005

6–1

MOTOROLA FAST SRAM

Advance Information

256KB and 512KB BurstRAM
Secondary Cache Modules for
PowerPC PReP/CHRP Platforms

The MPC2004 and MPC2005 are designed to provide burstable, high perfor­mance 256KB/512KB L2 cache for the PowerPC 60x microprocessor family in
conformance with the PowerPC Reference Platform (PReP) and the PowerPC
Common Hardware Reference Platform (CHRP) specifications. The modules
are configured as 32K x 72 and 64K x 72 bits in a 182 (91 x 2) pin DIMM format.
Each module uses four of Motorola’s 5 V 32K x 18 or 64K x 18 BurstRAMs and
a 5 V cache tag RAM configured as 16K x 12 for tag field plus 16K x 2 for valid and
dirty status bits.

Bursts can be initiated with the SRAMADS

signal. Subsequent burst address-

es are generated internal to the BurstRAM by the SRAMCNTEN

signal.

Write cycles are internally self timed and are initiated by the rising edge of the
clock (CLKx) inputs. Eight write enables are provided for byte write control.

Presence detect pins are available for auto configuration of the cache control.
A serial EEPROM is optional to provide more in–depth description of the
cache module.

The module family pinout will support 5 V and 3.3 V components for a clear path
to lower voltage and power savings. Both power supplies must be connected.

These cache modules are plug and pin compatible with the MPC2006, a 1MB
synchronous module also designed for the PReP and CHRP specifications.
They are also compatible with the MPC2007 and MPC2009, 256KB and 1MB re­spectively, asynchronous cache modules.

• PowerPC–style Burst Counter on Chip

• Flow–Through Data I/O

• Module Requires Both 3.3 V and 5 V Power Supplies

• Multiple Clock Pins for Reduced Loading

• All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible

• Three State Outputs

• Byte Write Capability

• Fast Module Clock Rates: 66 MHz

• Fast SRAM Access Times: 10 ns for Tag RAM Match

9 ns for Data RAM

• Decoupling Capacitors for Each Fast Static RAM

• High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

• 182 Pin Card Edge Module

• Burndy Connector, Part Number: ELF182JSC–3Z50

BurstRAM is a trademark of Motorola.BurstRAM is a trademark of Motorola.
PowerPC is a trademark of International Business Machines Corp.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Order this document

by MPC2004/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MPC2004
MPC2005

5/95

 Motorola, Inc. 1995

PIN ASSIGNMENT

182–LEAD DIMM

TOP VIEW – CASE TBD

GND

PD1/IDSDATA

PD3
DH31
DH29
DH27
DH25
VCC3

SRAMWE3

DH23
DH21
DH18

GND

DH16

SRAMWE2

DH14
DH13
VCC5
DH10

DH8

SRAMWE1

DH6
VCC3

DH4

GND

CLK0

GND

DH1

SRAMWE0

DL31
DL30

GND
DL29
DL27
DL25

VCC5

SRAMWE7

DL23
DL21
DL19

GND
DL17

92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

GND
PD0/IDSCLK
PD2
DH30
DH28
DH26
DH24
VCC3
DP3
DH22
DH20
DH19
GND
DH17
DP2
DH15
DH12
VCC5
DH11
DH9
DP1
DH7
VCC3
DH5
DH3
DH2
DH0
DP0
GND
CLK1
GND
DL28
DL26
DL24
DP7
VCC5
DL22
DL20
DL18
DL16
GND
DP6

134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91

SRAMWE6

DL15
DL13

GND

DL10

DL8

SRAMWE5

DL6

VCC3

DL5
DL2

GND

(CLK3) NC

GND

(CLK4) NC

GND

SRAMWE4

(SRAMALE) NC

VCC3
(ADDR1A) NC
(ADDR1B) NC

SRAMCNTEN0

(SRAMCNTEN1) NC

VCC5

VCC5

A27
A24
A22
A20

GND

A18
A16
A15
A14

VCC3

A10

A8
A6

GND

A4
A2
A1

RESERVED

VCC5

TAG VALID

TAGWE

STANDBY

DIRTYOUT

GND

DL14
DL12
DL11
GND
DL9
DP5
DL7
DL4
VCC3
DL3
DL1
DL0
GND
CLK2
GND
DP4
SRAMOE0
NC (SRAMOE1)
VCC3
NC (ADDR0A)
NC (ADDR0B)
SRAMADS0
NC (SRAMADS1)
VCC5
VCC5
A28
A26
A25
A23
GND
A21
A19
A17
A13 (See Note 1)
VCC3
NC (A12)
A11
A9
GND
A7
A5
A3
A0
VCC5
TAGCLR
TAG MATCH
TAGOE
DIRTYIN
GND

NOTES:

1. This pin on the MPC2004 is a No Connect (NC).

2. Signal n ames in ( parentheses) a re NC o n MPC2004 and
MPC2005, but are actual signals on other modules i n the
MPC200x family.

3. All power pins (VCC5, VCC3) must be connected to appropriate
supplies.

MPC2004•MPC2005
6–2

MOTOROLA FAST SRAM

MPC2004•MPC2005

6–3

MOTOROLA FAST SRAM

MPC2004 (32K x 72) BurstRAM MEMORY BLOCK DIAGRAM

LW

MCM67M618

A14 – A0

BAA

K
G

E

DQ0 – DQ7

A14 – A28

STANDBY

15

DQ8

UW

TSC

DQ9 – DQ16

DQ17

SRAMCNTEN0

SRAMADS0

CLK0

SRAMOE0

DH0 – DH7
DP0

DH8 – DH15

DP1

SRAMWE1

8

8

TSP

VCC5

SRAMWE0

’FCT

244

LW

MCM67M618

A14 – A0

BAA

K
G

E

DQ0 – DQ7

DQ8

UW

TSC

DQ9 – DQ16

DQ17

DH16 – DH23
DP2

DH24 – DH31

DP3

SRAMWE3

8

8

TSP

VCC5

SRAMWE2

LW

MCM67M618

A14 – A0

BAA

K
G

E

DQ0 – DQ7

15

DQ8

UW

TSC

DQ9 – DQ16

DQ17

DL0 – DL7
DP4

DL8 – DL15

DP5

SRAMWE5

8

8

TSP

VCC5

SRAMWE4

LW

MCM67M618

A14 – A10

BAA

K
G

E

DQ0 – DQ7

DQ8

UW

TSC

DQ9 – DQ16

DQ17

DL16 – DL23
DP6

DL24 – DL31

DP7

SRAMWE7

8

8

TSP

VCC5

SRAMWE6

MATCH

16K x 12 TAG

A12 – A0

PWRDN

WESTAT, WETAG
RESET
DIRTYIN

VALIDIN

A14 – A26

DIRTYIN

13

CLK

TAG 0 – TAG 11A0 – A11

TAGWE

TAGCLR

TAG VALID
CLK2

TAG MATCH

CLK1

OESTAT, OETAGTAGOE

DIRTYOUT DIRTYOUT

’F04

A13 – NC

PD3
PD2 – NC
PD1
PD0

V

CCQ

VCC3

MPC2004•MPC2005
6–4

MOTOROLA FAST SRAM

MPC2005 (64K x 72) BurstRAM MODULE BLOCK DIAGRAM

LW

MCM67M618

A14 – A0

BAA

K
G

E

DQ0 – DQ7

A14 – A28

STANDBY

15

DQ8

UW

TSC

DQ9 – DQ16

DQ17

SRAMCNTEN0

SRAMADS0

CLK0

SRAMOE0

DH0 – DH7
DP0

DH8 – DH15

DP1

SRAMWE1

8

8

TSP

VCC5

SRAMWE0

’FCT

244

LW

MCM67M618

A14 – A0

BAA

K
G

E

DQ0 – DQ7

DQ8

UW

TSC

DQ9 – DQ16

DQ17

DH16 – DH23
DP2

DH24 – DH31

DP3

SRAMWE3

8

8

TSP

VCC5

SRAMWE2

LW

MCM67M618

A14 – A0

BAA

K
G

E

DQ0 – DQ7

15

DQ8

UW

TSC

DQ9 – DQ16

DQ17

DL0 – DL7
DP4

DL8 – DL15

DP5

SRAMWE5

8

8

TSP

VCC5

SRAMWE4

LW

MCM67M618

A14 – A0

BAA

K
G

E

DQ0 – DQ7

DQ8

UW

TSC

DQ9 – DQ16

DQ17

DL16 – DL23
DP6

DL24 – DL31

DP7

SRAMWE7

8

8

TSP

VCC5

SRAMWE6

MATCH

16K x 12 TAG

A13 – A0

PWRDN

WESTAT, WETAG
RESET
DIRTYIN

VALIDIN

A13 – A26

DIRTYIN

14

CLK

TAG 0 – TAG 11A0 – A11

TAGWE

TAGCLR

TAG VALID
CLK2

TAG MATCH

CLK1

OESTAT, OETAGTAGOE

DIRTYOUT DIRTYOUT

’F04

PD3
PD2 – NC
PD1
PD0 – NC

A15

A15

A15

A15

A13

V

CCQ

VCC3

MPC2004•MPC2005

6–5

MOTOROLA FAST SRAM

PIN DESCRIPTIONS

Pin Locations Symbol

Type Description

68, 69, 70, 71, 73, 74, 75,
76, 78, 79, 80, 82, 83, 84,

85, 159, 160, 161, 162,

164, 165, 166, 167, 169,

170, 171, 173, 174, 175

A0 – A28 Input Address Inputs – (MSB:0, LSB:28)

62, 63 ADDR0A,

ADDR0B

Input Least significant address bit when asynchronous SRAMs are used.

153, 154 ADDR1A,

ADDR1B

Input Next to least significant address bit when asynchronous SRAMs are used.

30, 56, 117, 146, 148 CLK0 – CLK4 Input Clock Inputs – CLK2 is for Tag RAM, CLK0, 1, 3, and 4 are for SRAMs.

For 1MB use all the clocks. For 512KB or less us CLK0–CLK2 only.

4, 5, 6, 7, 10, 11, 12, 14,

16, 17, 19, 20, 22, 24, 25,

26, 27, 95, 96, 97, 98, 101,

102, 103, 105, 107, 108,

110, 111, 113, 115, 119

DH0 – DH31 I/O High Data Bus – (MSB:0, LSB:31)

32, 33, 34, 37, 38, 39, 40,
43, 44, 45, 47, 49, 50, 52,

53, 54, 121, 122, 124, 125,

126, 129, 130, 131, 133,
135, 136, 138, 139, 141,

143, 144

DL0 – DL31 I/O Low Data Bus – (MSB:0, LSB:31)

9, 15, 21, 28, 35, 42, 48, 58 DP0 – DP7 I/O Data Parity Bus – (MSB:0, LSB:7)

3, 94 PD2, PD3 Output Presence detect bits 2 and 3.

2 PD0/IDSCLK Input Presence detect bit 0/EEPROM serial clock.

93 PD1/IDSDATA I/O Presence detect bit 1/EEPROM serial data.

64, 65 SRAMADS0,

SRAMADS1

Input SRAM Address Strobe – For 512KB or less us SRAM ADS0 only.

151 SRAM ALE Input SRAM Address Latch Enable – Use for asynchronous SRAM only.

155, 156 SRAMCNTEN0,

SRAMCNTEN1

Input SRAM Count Enables – For 512KB or less use SRAM CNT EN0 only.

59, 60 SRAMOE0,

SRAMOE1

Input SRAM Output Enables – For 512KB or less use SRAM OE0 only.

100, 106, 112, 120, 128,

134, 140, 150

SRAMWE0 –

SRAMWE7

Input SRAM Write Enables – (MSB:0, LSB:7)

87 TAGCLR Input Tag RAM clear.

88 TAG MATCH Output Tag RAM match indication.
178 TAG VALID Input Tag RAM valid bit.
179 TAGWE Input Tag RAM write enable.

89 TAGOE Input Tag RAM output enable.

90 DIRTYIN Input Dirty input bit.
181 DIRTYOUT Output Dirty output bit.
180 STANDBY Input Standby pin. Reduces standby power consumption.
176 RESERVED Reserved pin.

8, 23, 51, 61, 77, 99, 114,

142, 152, 168

VCC3 Input + 3.3 V power supply.

MPC2004•MPC2005
6–6

MOTOROLA FAST SRAM

Pin Locations DescriptionTypeSymbol

18, 36, 66, 67, 86, 109,

127, 157, 158, 177

VCC5 Input + 5 V power supply.

1, 13, 29, 31, 41, 46, 55,

57, 72, 81, 91, 92, 104,
116, 118, 123, 132, 137,
145, 147, 149, 163, 172,

182

GND Input Ground

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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,

and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “T ypical” parameters can and do vary in different

applications. All operating parameters, including “T ypicals” must be validated for each customer application by customer’s technical experts. Motorola does

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MCM72BB32/D

*MCM72BB32/D*

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