Datasheet MP86963DUT Datasheet (MPS)

MP86963

c

High Efficiency, 20A, 27V Intelli-Phase

(Integrated HS/LS FETs and Driver) in a 5x5mm QFN

The Future of Analog IC Technology

DESCRIPTION

The MP86963 is a monolithic Half Bridge with built-in internal power MOSFETs and gate driver. It achieves 20A continuous output current over a wide input supply range.

Integrating the Driver and MOSFETs results in high efficiency due to optimal dead time control and parasitic inductance reduction.

The MP86963 is a Monolithic IC designed to drive up to 20A per phase. Housed in a very small 5x5mm TQFN Packge, this device can be operated from 100kHz to 1MHz operation.

The IC is intended to work with 3.3V tri-state output controllers.

The MP86963 is ideal for notebook applications where efficiency and small size are a premium.

FEATURES

• Wide 4.5V to 21V Operating Input Range

• 20A Output Current

• Simple Logic Interface (3.3V)

• Operate from 100kHz to 1MHz

• Accepts 3-state PWM Input

• Suitable for single-/multi-phase operation

• Available in a 5mm x 5mm TQFN Package

• ROHS6 Compliant

APPLICATIONS

• Power modules

• Notebook, Core Voltage

• Graphic Card Core Regulators

All MPS parts are lead-free and adhere to the RoHS directive. For MPS green status, please visit MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithi Power Systems, Inc.

This Product is Patent Pending.

TM

Solution

TYPICAL APPLICATION

V

IN

4.5V-21V

C

IN

ON/OFF

V

CC

5V

4

7

6

5

EN

VCC IO

PWM

MP86963

SYNC

IN

AGND

9

BST

VCC

GND

3

SW

8

100nF

2

10-18

C6

100

95

90

85

L

Cs 1

F

0.8V to 1.2V @ 20A

C

OUT

80

75

70

65

EFFICIENCY (%)

60

55

50

2 4 6 8 10 12 14 16 18 20

OUTPUT CURRENT (A)

VIN=12V

=1.2V

V

OUT

MP86963 –20A, 27V INTELLI-PHASE

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

ORDERING INFORMATION

Part Number* Package Top Marking Free Air Temperature(TA)

MP86963DUT 5x5 TQFN 86963UT

* For Tape & Reel, add suffix –Z (e.g. MP86963DUT–Z);

For RoHS compliant packaging, add suffix –LF (e.g. MP86963DUT–LF–Z)

PACKAGE REFERENCE

PIN 1 ID

N/C

VCC

AGND

EN

SYNC

PWM

VCC IO

BST

1

IN

2

3

IN

4

5

IN

6

7

8

IN

9

IN

SW

GND

18

GND

17

GND

16

GND

15

GND

14

GND

13

GND

12

GND

11

GND

10

GND

-40°C to +85°C

EXPOSED PAD CONNECT TO PIN

ABSOLUTE MAXIMUM RATINGS

(1)

Supply Voltage VIN....................................... 27V

V

(DC) .................................-0.3V to VIN +0.3V

SW

V

(20ns) ....................................-3V to VIN +3V

SW

V

...................................................... VSW + 6V

BST

All Other Pins..................................-0.3V to +6V

Continuous Power Dissipation (T

= +25°C)

A

(2)

............................................................. 3.8W

Junction Temperature...............................150°C

Lead Temperature ....................................260°C

Storage Temperature............... -65°C to +150°C

Recommended Operating Conditions

(3)

Supply Voltage VIN...........................4.5V to 21V

V

Driver Voltage………………….4.5V to 5.5V

CC

Operating Junct. Temp (T

)...... -40°C to +125°C

J

Thermal Resistance

(4)

θ

JA

θJC

5x5 TQFN ...............................33 ....... 8.... °C/W

Notes:

1) Exceeding these ratings may damage the device.

2) The maximum allowable power dissipation is a function of the maximum junction temperature T ambient thermal resistance θ

. The maximum allowable continuous power dissipation at

T

A

any ambient temperature is calculated by P

)/ θJA. Exceeding the maximum allowable power dissipation

T

A

will cause excessive die temperature.

3) The device is not guaranteed to function outside of its operating conditions.

4) Measured on JESD51-7, 4-layer PCB.

(MAX), the junction-to-

J

, and the ambient temperature

JA

(MAX)=(TJ(MAX)-

D

MP86963 –20A, 27V INTELLI-PHASE

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

ELECTRICAL CHARACTERISTICS

VIN = 12V, TA = +25°C, unless otherwise noted.

Parameters Symbol Condition Min Typ Max Units

ICC Standby I

I

(Shutdown) I

IN

IIN Standby I

CC_StdbyVCC

VCC = 0V 1 5 μA

IN (Off)

IN_Stdby

Rise Time I

Fall Time I

Minimum On-Time 55 ns

Dead-Time Rising 5 ns

Dead-Time Falling 10 ns

V

Under Voltage Lockout Threshold

CC

Rising

VCC Under Voltage Lockout Threshold Hysteresis

SYNC Pull-Up Current I

3.7 4.2 V

470 mV

SYNC=0V -14 μA

SYNC

SYNC Logic High Voltage 2 V SYNC Logic Low Voltage 0.4 V

EN Input Low Voltage 0.4 V

En Input High Voltage 2 V

PWM Input

Input Current I

PWM

VCCIO 2.9 3.3 3.6 V PWM Low to Tri-State Threshold 1.10 V PWM Tri-State to High Threshold 2.25 V PWM High to Tri-State Threshold 2.10 V PWM Tri-State to Low Threshold 0.75 V

Tri-State Shutdown Holdoff Time t

UG/LG Three-State Propagation Delay t USW Turn-Off Propagation Delay t LSW Turn-Off Propagation Delay t USW Turn-On Propagation Delay t LSW Turn-On Propagation Delay t

TSSHD

20 ns

PTS

VCC=5V 40 ns

PDUL

VCC=5V 25 ns

PDLL

VCC=5V 30 ns

PDUH

VCC=5V 50 ns

PDLH

=5V, PWM=EN=LO 550 610 μA

VCC =5V, PWM=EN=LO 1 μA

= 20A 5 ns

OUT

= 20A 3 ns

OUT

V

=3.3V 370 μA

PWM

V

=0V -370 μA

PWM

V

=5V,

CC

Temperature=25°C

100 ns

MP86963 –20A, 27V INTELLI-PHASE

PWM

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

SW

0V

t

PDLL

PDUH

t

PDUL

t

PDLH

t

TSSHD

Figure 1—Timing Diagram

PIN FUNCTIONS

Pin # Name Description

1 NC Not Connected.

2 VCC Low-Side Driver Bias Supply. Decouple with a 1µF ceramic capacitor.

3 AGND Signal Ground.

4 EN

5 SYNC

6 PWM

7 VCC IO Reference voltage that connects to PWM driver supply.

8 BST

9

Exposed Pad

10–18

Exposed Pad

Exposed Pad SW Switch Output. These pins are fused together.

Active High On/Off Control. Pulling this Pin Low forces the SW Pin to be in a high impedance state.

Leaving this pin Open enables theLower Synchronous Switch. Pulling it Low forces the Lower Switch into Diode Emulation mode.

Pulse Width Modulation Control. Accepts three-state input. Force PWM to midstate or open to place SW into high impedance state.

Bootstrap. This capacitor is needed to drive the power switch’s gate above the supply voltage. It is connected between SW and BST pins to form a floating supply across the power switch driver.

IN

GND Power Ground.

Supply Voltage. C input.

is needed to prevent large voltage spikes from appearing at the

IN

V

OUT

MP86963 –20A, 27V INTELLI-PHASE

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 12V, VCC = 5V, V

= 1.2V, TA = +25ºC, unless otherwise noted.

OUT

100

95

90

85

80

75

70

65

EFFICIENCY (%)

60

55

50

2 4 6 8 10 12 14 16 18 20

OUTPUT CURRENT (A)

3.5

3

2.5

2

1.5

POWER LOSS (W)POWER LOSS (W)

1

0.5

0

0 5 10 15 20

OUTPUT CURRENT (A)

100

95

90

85

80

75

70

65

EFFICIENCY (%)

60

55

50

2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20

OUTPUT CURRENT (A)

4

3.5

3

2.5

2

1.5

POWER LOSS (W)

1

0.5

0

0 5 10 15 20

OUTPUT CURRENT (A)

100

95

90

85

80

75

70

65

EFFICIENCY (%)

60

55

50

OUTPUT CURR ENT (A)

4.5

4

3.5

3

2.5

2

1.5

POWER LOSS (W)

1

0.5

0

0 5 10 15 20

OUTPUT CURR ENT (A)

I

4.5

4

3.5

3

2.5

2

1.5

1

0.5

0

300 400 500 600 700 800 900 1000

SWITCHING FREQUENCY (kHz)

20A

15A

=15A

OUT

4

3.5

1.0MHz

3

2.5

2

1.5

1

POWER LOSS (W)

0.5

0

8 101214161820

INPUT VOLTAGE (V)

600kHz

300kHz

I

=15A, Fsw=600kHz

OUT

2.35

2.3

2.25

2.2

2.15

2.1

2.05

POWER LOSS (W)

2

1.95

1.9

0.8 1 1.2 1.4 1.6 1.8 2 2.2

OUTPUT VOLTAGE (V)

MP86963 –20A, 27V INTELLI-PHASE

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

VIN = 12V, VCC = 5V, V

Temperature Rise vs. Output Current

No airflow

70

C)

O

60

50

= 1.2V, TA = +25ºC, unless otherwise noted.

OUT

SW Rising Edge Dead Time

I

= 15A

OUT

SW Falling Edge Dead Time

I

OUT

= 15A

40

600kHz

30

20

10

CASE TEMPERATURE RISE (

0

0 5 10 15 20

OUTPUT CURRENT (A)

Output Waveform

I

= 20A

OUT

V

SW

5V/div.

300kHz

V

SW

500mV/div.

V

SW

10V/div.

V

OUT

1V/div.

I

OUT

25A/div.

SOA Waveform

V

= 19V, V

IN

I

= 20Α to 80A, F

OUT

= 1.2V

SW

= 600kHz

V

SW

1V/div.

MP86963 –20A, 27V INTELLI-PHASE

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

EFFICIENCY MEASUREMENT SETUP

MP86963 –20A, 27V INTELLI-PHASE

BLOCK DIAGRAM

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

EN

V

IO

CC

PWM

SYNC

10.8

5.4

V

cc

150

V

CC

EN

V

cc

PWM

VCCIO

PWM

HGate

BST

IN

SW

V

OUT

Logic

Tri-State

V

CC

Diode

Emulation

EN

LGate

Logic

LGate

M2

GND

Figure 2—Function Block Diagram

MP86963 –20A, 27V INTELLI-PHASE

OPERATION

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

The MP86963 is a 20A Monolithic Half Bridge driver with MOSFETs ideally suited for single/multi-phase Buck regulators.

Once the EN, V

, VCCIO, VCC and V

IN

signals

BST

are sufficiently high, operation begins. BST voltage has a typical rising UVLO of 2.2V and a falling UVLO of 2.0V. When BST is below the UVLO voltage, the device will be off.

MP86963 can work with most PWM controllers. The device accepts PWM signal from 100kHz up to 1MHz. There is an internal resistor divider to put PWM voltage to tri-state region if the PWM pin is open.

Internally, SYNC is tied to V

through a resistor.

CC

By default, the device will operate in synchronous mode. To enter Diode Emulation mode, drive SYNC pin LOW.

Startup and Shutdown Sequence

MP86963 can work with any startup or shutdown sequencing combination of V

, VCC, VCCIO and

IN

EN. If PWM signal is present, the MP86963 will start working whenever V

, VCC, VCCIO and EN

IN

are ready. On the other hand, if any of these signals is not ready, the MP86963 will stop working. However, it is recommended to turn on and turn off the device through the EN pin.

PCB Layout Guideline

PCB layout is very important to achieve stable operation. Please follow these guidelines to achieve optimal performance.

1) Keep the path of switching current short and minimize the loop area formed by input capacitor. Keep the connection between SW pin and input power ground as short and wide as possible.

2) Always place some input bypass ceramic capacitors next to the device and on the same layer as the device. Do not put all of the input bypass capacitors on the back side of the device. Use as many vias and input voltage planes as possible to reduce the switching spike. BST capacitor and V

capacitor should also be as

CC

close to the device as possible.

3) The recommended external BST cap is 100nF. Do not use a capacitance value lower than 100nF. Place a 1.0Ω resistor between the BST capacitor and BST pin for optimized performance.

4) Do not place via on the pad or on the pin footprint. Doing so may cause soldering issue during the assembling process. Use Figure 3 as a via placement reference.

5) Connect IN, SW and GND to large copper area and use vias to cool the chip to improve thermal performance and long-term reliability. See Figure 4 as an example.

Figure 3—Via Placement Guideline

Do not put via on the device’s pad footprint or pin footprint to avoid assembly issue. Use as many vias as possible to cool down the device.

6) Place the V

decouple capacitor close to the

CC

IC. Connect AGND and PGND at the point of V

capacitor's ground connection.

CC

Recommended SMT Setting

Stencil thickness: 0.12mm

EP Pad Opening: (Stencil opening : Real PCB Size) Length: 0.85:1 Width: 1:1

Note: The EP pad for Intelli-Phase are IN, SW and GND pad on the bottom.

Solder type: #3

MP86963 –20A, 27V INTELLI-PHASE

V

R

BST

C

BST

(SW Plane)

Intelli Phase

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

C

CC

Input Capacitors

(Vin Plane)

Inductor

(GND Plane)

Output Capacitors

Figure 4—Copper Area Guideline

Use large copper area, many vias and many IN, SW and GND inner layer planes to achieve optimal thermal performance.

MP86963 –20A, 27V INTELLI-PHASE

PACKAGE INFORMATION

FCTQFN18L (EXPOSED PAD)

TM

SOLUTION INTEGRATED HS/LS FETS AND DRIVER IN A 5X5mm QFN

PIN 1 ID MARKING

PIN 1 ID INDEX AREA

0.20 R EF

4.90

5.10

TOP VIEW

SIDE VIEW

4.90

5.10

0.00

0.05

0.70

0.80

0.40

0.60

0.40

0.60

0.50 BSC

0.18

0.30

2.80 BSC

0.50

0.70

18

10 9

0.30

0.40

1.30

1.50

BOTTOM VIEW

PIN 1 ID OP TI ON A

0.20x45” TYP.

PIN 1 I D OPTION B R0.20 TYP.

DETAIL A

PIN 1 ID SEE DETAIL A

1

0.59 BSC

9

1.77 BSC

2.95 BSC

4.13 BSC

4.90

NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.

3) LEAD COPLANARITY SHALL BE 0.10 MI LL IME TER MAX.

4) JEDEC REFERENCE IS MO-229, VARIATION WJJD.

5) DRAWING IS NOT TO SCALE.

0.60

0.50

0.25

2.80

0.70

1.50

RECOMMENDED LAND PATTERN

0.59 1.77 2.95 4.13

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third

party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications.

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