Datasheet MOS 4053 Datasheet (FREI)

CD4051B, CD4052B, CD4053B

[ /Title (CD405 1B, CD4052 B, CD4053 B) /Subject (CMOS Analog Multiplexers/Dem ultiplexers with Logic Level Conversion) /Author () /Keywords (Harris Semiconductor, CD4000

Data sheet acquired from Harris Semiconductor SCHS047G

Features

• Wide Range of Digital and Analog Signal Levels

- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V

- Analog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20V

• Low ON Resistance, 125Ω (Typ) Over 15V Range for V

• High OFF Resistance, Channel Leakage of ±100pA (Typ) at V

DD-VEE

• Logic-Level Conversion for Digital Addressing Signals of 3V to 20V (V Signals to 20V

• Matched Switch Characteristics, r V

DD-VEE

• Very Low Quiescent Power Dissipation Under All DigitalControl Input and Supply Conditions, 0.2µW (Typ) at V

DD-VSS

• Binary Address Decoding on Chip

• 5V, 10V, and 15V Parametric Ratings

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and 25

• Break-Before-Make Switching Eliminates Channel Overlap

DD-VEE

= 18V

= 15V

= VDD-VEE = 10V

= 18V

DD-VSS

= 3V to 20V) to Switch Analog

(VDD-VEE = 20V)

P-P

= 5Ω (Typ) for

ON

Signal Input

P-P

o

C

P-P

Applications

• Analog and Digital Multiplexing and Demultiplexing

• A/D and D/A Conversion

• Signal Gating

CMOS Analog Multiplexers/Dem ultiplex er s with Logic Level Conver sion

The CD4051B, CD4052B, and CD4053B analog multiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. Control of analog signals up to 20V signal amplitudes of 4.5V to 20V (if V V

DD-VEE

differences above 13V, a V required). For example, if V V

EE

controlled by digital inputs of 0V to 5V. These multiplexer circuits dissipate extremely low quiescent power over the full V independent of the logic state of the control signals. When a logic “1” is present at the inhibit input terminal, all channels are off.

of up to 13V can be controlled; for VDD-VEElevel

= -13.5V, analog signals from -13.5V to +4.5V can be

DD-VSS

and VDD-VEE supply-voltage ranges,

can be achieved by digital

P-P

DD-VSS

DD

of at least 4.5V is

= +4.5V, VSS = 0V, and

= 3V, a

August 1998 - Revised October 2003

The CD4051B is a single 8-Channel multiplexerhaving three binary control inputs, A, B, and C, and an inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to the output.

The CD4052B is a differential 4-Channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs.

The CD4053B is a triple 2-Channel multiplexer having three separate digital control inputs, A, B, and C, and an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole, double-throw conﬁguration.

When these devices are used as demultiplexers, the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs.

Ordering Information

PART NUMBER

CD4051BF3A, CD4052BF3A, CD4053BF3A

CD4051BE, CD4052BE, CD4053BE

CD4051BM, CD4051BMT, CD4051BM96 CD4052BM, CD4052BMT, CD4052BM96 CD4053BM, CD4053BMT, CD4053BM96

CD4051BNSR, CD4052BNSR, CD4053BNSR

CD4051BPW, CD4051BPWR, CD4052BPW, CD4052BPWR CD4053BPW, CD4053BPWR

NOTE: When ordering, use the entire part number. The sufﬁxes 96 and R denote tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

TEMP. RANGE

(oC) PACKAGE

-55 to 125 16 Ld CERAMIC DIP

-55 to 125 16 Ld PDIP

-55 to 125 16 Ld SOIC

-55 to 125 16 Ld SOP

-55 to 125 16 Ld TSSOP

1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Copyright

Pinouts

T

CHANNELS

IN/OUT

COM OUT/IN

CHANNELS

IN/OUT

CD4051B, CD4052B, CD4053B

CD4051B (PDIP, CDIP, SOIC, SOP, TSSOP)

TOP VIEW

16

V

DD

15

2

14

1

CHANNELS IN/OU

13

0

12

3 A

11 10

B

9

C

IN/OUT

OUT/IN CX OR CY

IN/OUT CX

CD4053B (PDIP, CDIP, SOP, TSSOP)

INH V V

EE SS

1

4

2

6

3 4

7

5

6 7 8

INH V V

by bx

EE SS

CD4052B (PDIP, CDIP, SOP, TSSOP)

TOP VIEW

16

Y CHANNELS

IN/OUT

COMMON “Y” OUT/IN

Y CHANNELS

IN/OUT

INH

V

EE

V

SS

1

0

2

3 4

3

5

1

6 7 8

V

DD

15

2

X CHANNELS IN/OUT

14

1

13

COMMON “X” OUT/IN

12

0

X CHANNELS IN/OUT

3

11 10

A

9

B

TOP VIEW

16

1 2 3

cy

4 5 6 7 8

V

DD

OUT/IN bx OR by

15 14

OUT/IN ax OR ay

13

ay 12 11 10

IN/OUT

ax

A

B

9

C

Functional Block Diagrams

11

A †

10

B †

LOGIC LEVEL

CONVERSION

9

C †

6

INH †

8 7

V

SS

†All inputs are protected by standard CMOS protection network.

CD4051B

CHANNEL IN/OUT

01234567

V

16

DD

BINARY

TO

1 OF 8

DECODER

WITH

INHIBIT

V

EE

134 2 5 1 12 15 14

TG

COMMON

OUT/IN

3

2

CD4051B, CD4052B, CD4053B

Functional Block Diagrams (Continued)

V

16

DD

CD4052B

X CHANNELS IN/OUT

0123

1211 15 14

TG

A

B †

INH †

†

10

9

6

A †

B †

C †

INH †

CONVERSION

11

10

9

6

LOGIC

LEVEL

V

SS

LOGIC

LEVEL

78

BINARY

TO

1 OF 4

DECODER

WITH

INHIBIT

V

EE

V

16

DD

CD4053B

BINARY TO

1 OF 2

DECODERS

WITH

INHIBIT

Y CHANNELS IN/OUT

IN/OUT

TG

4251 3210

axaybxbycxcy 123 5 1 2 13

TG

COMMON X

OUT/IN

13

3

COMMON Y

OUT/IN

COMMON

OUT/IN

ax OR ay

14

COMMON

OUT/IN

bx OR by

15

COMMON

OUT/IN

cx OR cy

4

8

V

SS

V

7

EE

†All inputs are protected by standard CMOS protection network.

3

V

DD

CD4051B, CD4052B, CD4053B

TRUTH TABLES

INPUT STATES

“ON” CHANNEL(S)INHIBIT C B A

CD4051B

0000 0 0001 1 0010 2 0011 3 0100 4 0101 5 0110 6 0111 7 1 X X X None

CD4052B

INHIBIT B A

0 0 0 0x, 0y 0 0 1 1x, 1y 0 1 0 2x, 2y 0 1 1 3x, 3y 1 X X None

CD4053B

INHIBIT A OR B OR C

0 0 ax or bx or cx 0 1 ay or by or cy 1 X None

X = Don’t Care

4

CD4051B, CD4052B, CD4053B

Absolute Maximum Ratings Supply Voltage (V+ to V-)

Voltages Referenced to VSS Terminal . . . . . . . . . . . -0.5V to 20V

DC Input Voltage Range . . . . . . . . . . . . . . . . . . -0.5V to VDD +0.5V

DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA

Operating Conditions

Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Electrical Speciﬁcations Common Conditions Here: If Whole Table is For the Full Temp. Range, V

RL = 100Ω, Unless Otherwise Speciﬁed (Note 3)

CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)

PARAMETER

SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)

Quiescent Device Current, IDD Max

Drain to Source ON Resistance rON Max 0 ≤ VIS≤ V

Change in ON Resistance (Between Any Two Channels), ∆r

ON

OFF Channel Leakage Current: Any Channel OFF (Max) or ALL ChannelsOFF(Common OUT/IN) (Max)

Capacitance: - -5 5- 5

Propagation Delay Time (Signal Input to Output

DD

Input, C

IS

Output, C

Feedthrough

OS

CD4051 -----30 - pF CD4052 -----18 - pF CD4053 ----- 9 - pF

C

IOS

- - - 5 5 5 150 150 - 0.04 5 µA

- - - 10 10 10 300 300 - 0.04 10 µA

- - - 15 20 20 600 600 - 0.04 20 µA

- - - 20 100 100 3000 3000 - 0.08 100 µA

- 0 0 5 800 850 1200 1300 - 470 1050 Ω

- 0 0 10 310 330 520 550 - 180 400 Ω

- 0 0 15 200 210 300 320 - 125 240 Ω

- 0 0 5 -----15 - Ω

- 0 010-----10 - Ω

- 0 015----- 5 - Ω

-0018±100 (Note 2) ±1000 (Note 2) - ±0.01 ±100

V

DD

RL = 200kΩ, CL = 50pF, tr, tf = 20ns

5 -----3060ns 10-----1530ns 15-----1020ns

Thermal Information

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W

M (SOIC) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W

NS (SOP) package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64oC/W

PW (TSSOP) package. . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature (Ceramic Package) . . . . . . . . .175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC

Maximum Storage Temperature Range. . . . . . . . . . -65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .265oC

(SOIC - Lead Tips Only)

= ±5V, AV = +1,

SUPPLY

UNITSVIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 12525MIN TYP MAX

nA

(Note 2)

----- 5 - pF

-----0.2 - pF

5

CD4051B, CD4052B, CD4053B

Electrical Speciﬁcations Common Conditions Here: If Whole Table is For the Full Temp. Range, V

RL = 100Ω, Unless Otherwise Speciﬁed (Continued) (Note 3)

CONDITIONS LIMITS AT INDICATED TEMPERATURES (oC)

PARAMETER

CONTROL (ADDRESS OR INHIBIT), V

Input Low Voltage, VIL, Max

Input High Voltage, VIH, Min

Input Current, IIN (Max) VIN = 0, 18 18 ±0.1 ±0.1 ±1 ±1-±10 Propagation Delay Time:

Address-to-Signal OUT(ChannelsON or OFF) See Figures 10, 11, 14

Propagation Delay Time:

Inhibit-to-Signal OUT (Channel Turning ON) See Figure 11

Propagation Delay Time:

Inhibit-to-Signal OUT (Channel Turning OFF) See Figure 15

Input Capacitance, C (Any Address or Inhibit Input)

NOTE:

2. Determined by minimum feasible leakage measurement for automatic testing.

VIL = V through 1kΩ; VIH = V through 1kΩ

tr, tf = 20ns, CL = 50pF, RL = 10kΩ

tr, tf = 20ns, CL = 50pF, RL = 1kΩ

tr, tf = 20ns, CL = 50pF, RL = 10kΩ

IN

C

VEE = VSS,

DD

RL = 1kΩ to VSS, IIS < 2µA on All OFF Channels

DD

-100 5 -----200400ns

-100 5 -----130300ns

5 1.5 1.5 1.5 1.5 - - 1.5 V 103333 - - 3 V 154444 - - 4 V

5 3.5 3.5 3.5 3.5 3.5 - - V 1077777 - - V 15 11 11 11 11 11 - - V

0 0 5 -----450720ns 0 010-----160320ns 0 015-----120240ns

-5 0 5 ---- -225450ns

0 0 5 -----400720ns 0 010-----160320ns 0 015-----120240ns

0 0 5 -----200450ns 0 010-----90210ns 0 015-----70160ns

----- 5 7.5pF

SUPPLY

= ±5V, AV = +1,

-5

UNITSVIS (V) VEE (V) VSS (V) VDD (V) -55 -40 85 12525MIN TYP MAX

±0.1 µA

Electrical Speciﬁcations

PARAMETER

Cutoff (-3dB) Frequency Channel ON (Sine Wave Input)

TEST CONDITIONS LIMITS

UNITSVIS (V) VDD (V) RL (kΩ) TYP

5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 30 MHz

VEE = VSS, CD4052 25 MHz

20Log

V

OS

----------- -

V

IS

3dB–=

VOS at Any Channel 60 MHz

CD4051 20 MHz

6

B

5

0

CD4051B, CD4052B, CD4053B

Electrical Speciﬁcations

TEST CONDITIONS LIMITS

PARAMETER

Total Harmonic Distortion, THD 2 (Note 3) 5 10 0.3 %

3 (Note 3) 10 0.2 % 5 (Note 3) 15 0.12 %

VEE = VSS, fIS = 1kHz Sine Wav e %

-40dB Feedthrough Frequency (All Channels OFF)

-40dB Signal Crosstalk Frequency

Address-or-Inhibit-to-Signal Crosstalk

5 (Note 3) 10 1 VOS at Common OUT/IN CD4053 8 MHz

VEE = VSS, CD4052 10 MHz

V

20Log

OS

----------- -

V

IS

–=

40d

VOS at Any Channel 8 MHz

CD4051 12 MHz

5 (Note 3) 10 1 Between Any 2 Channels 3 MHz

VEE = VSS, Between Sections,

20Log

V

OS

----------- -

V

IS

40dB–=

CD4052 Only

Between Any Two Sections, CD4053 Only

-1010

Measured on Common 6 MHz Measured on Any Chan-

10 MHz

nel In Pin 2, Out Pin 14 2.5 MHz In Pin 15, Out Pin 14 6 MHz

65 mV

(Note 4)

VEE=0,VSS=0,tr,tf=20ns,V

CC

65 mV

= VDD - VSS (Square Wave)

NOTES:

–

3. Peak-to-Peak voltage symmetrical about

4. Both ends of channel.

V

DDVEE

-----------------------------

2

UNITSVIS (V) VDD (V) RL (kΩ) TYP

PEAK

Typical Performance Curves

600

VDD - VEE = 5V

500

400

300

200

, CHANNEL ON RESISTANCE (Ω)

100

ON

r

0

-4 -3 -2 -1 0 1 2 3 4 , INPUT SIGNAL VOLTAGE (V)

V

IS

FIGURE 1. CHANNELON RESISTANCE vs INPUT SIGNAL

VOLTAGE (ALL TYPES)

TA = 125oC

= 25oC

T

A

TA = -55oC

300

V

- VEE = 10V

DD

250

200

150

100

, CHANNEL ON RESISTANCE (Ω)

50

ON

r

0

-10 -7.5 -5 -2.5 0 2.5 5 7.5 1 , INPUT SIGNAL VOLTAGE (V)

V

IS

TA = 125oC

TA = 25oC

= -55oC

T

A

FIGURE 2. CHANNELON RESISTANCE vs INPUT SIGNAL

VOLTAGE (ALL TYPES)

7

5

P

, POWER DISSIPATION PACKAGE (

W)

5

P

, POWER DISSIPATION PACKAGE (

W)

CD4051B, CD4052B, CD4053B

Typical Performance Curves (Continued)

600

TA = 25oC

500

VDD - VEE = 5V

400

300

200

10V

, CHANNEL ON RESISTANCE (Ω)

100

ON

r

15V

0

-10 -7.5 -5 -2.5 0 2.5 5 7.5 10 V

, INPUT SIGNAL VOLTAGE (V)

IS

FIGURE 3. CHANNEL ON RESISTANCE vs INPUT SIGNAL

VOLTAGE (ALL TYPES)

6

VDD = 5V V

= 0V

SS

= -5V

V

EE

4

T

= 25oC

A

2

0

-2

, OUTPUT SIGNAL VOLTAGE (V)

-4

OS

V

-6

-6 -4 -2 0 2 4 6 V

, INPUT SIGNAL VOLTAGE (V)

IS

RL = 100kΩ, RL = 10kΩ

1kΩ 500Ω

100Ω

250

VDD - VEE = 15V

200

TA = 125oC

150

100

TA = 25oC

TA = -55oC

50

, CHANNEL ON RESISTANCE (Ω)

ON

r

0

-10 -7.5 -5 -2.5 0 2.5 5 7.5 10 V

, INPUT SIGNAL VOLTAGE (V)

IS

FIGURE 4. CHANNEL ON RESISTANCE vs INPUT SIGNAL

VOLTAGE (ALL TYPES)

5

10

TA = 25oC ALTERNATING “O”

AND “I” PATTERN

C

= 50pF

L

4

10

3

10

2

10

, POWER DISSIPATION PACKAGE (µW)

D

P

10

1

VDD = 15V

VDD = 10V

VDD = 5V

CL = 15pF

2

10

SWITCHING FREQUENCY (kHz)

3

TEST CIRCUIT

V

DD

B/D

f

CD4029

ABC

V

DD

1011

100Ω

13 14 15

CD4051

12

1 5 2 4

8

7

100Ω

4

10

9

6

C

L

Ι

3

5

10

FIGURE 5. ON CHARACTERISTICS FOR 1 OF 8 CHANNELS

(CD4051B)

5

10

TA = 25oC ALTERNATING “O”

µ

D

10

CL = 50pF

4

3

2

1

AND “I” PATTERN

VDD = 15V

VDD = 5V

CL = 15pF

10

VDD = 10V

2

10

f

V

DD

100Ω

3

TEST CIRCUIT

V

DD

CD4029

B/D

AB

10

9

1 5 2

4

CD4052

6 7

8

Ι

4

10

3

C 13 12 14

15 11

SWITCHING FREQUENCY (kHz)

FIGURE 7. DYNAMIC POWER DISSIPATION vs SWITCHING

FREQUENCY (CD4052B)

8

FIGURE 6. DYNAMIC POWER DISSIPATION vs SWITCHING

FREQUENCY (CD4051B)

5

10

TA = 25oC ALTERNATING “O”

µ

AND “I” PATTERN

C

= 50pF

L

4

10

L

10

3

10

CL = 15pF

10

VDD = 5V

2

10

2

10

D

10

1

SWITCHING FREQUENCY (kHz)

100Ω

10

VDD = 15V

V

DD

100Ω

3

VDD = 10V

TEST CIRCUIT

f

9 3 5

CD4053

10 11

6 7

8

Ι

4

10

4

C

L

12 13

2 1 15 14

10

FIGURE 8. DYNAMIC POWER DISSIPATION vs SWITCHING

FREQUENCY (CD4053B)

Test Circuits and Waveforms

= 15V

V

DD

VDD = 7.5V

CD4051B, CD4052B, CD4053B

VDD = 5V

7.5V

VSS = 0V

VEE = 0V

VSS = 0V

7 8

(A)

V

EE

= -7.5V

7

8

(B)

NOTE: The ADDRESS (digital-control inputs) and INHIBIT logic levels are: “0” = VSSand “1” = VDD. The analog signal (through the TG) may swing from VEE to VDD.

FIGURE 9. TYPICAL BIAS VOLTAGES

t

= 20ns

10%

90%

50%

90%

50%

r

90%

50%

TURN-ON TIME

10%

TURN-OFF TIME

tf = 20ns

10%

1616 1616

5V

= 0V VSS = 0V

V

SS

10%

t

PHZ

7

8

(C)

t

90%

50%

VEE = -10V

5V

VEE = -5V

= 20ns

r

90%

TURN-OFF TIME

90%

50%

7 8

(D)

tf = 20ns

10%

TURN-ON TIME

FIGURE 10. WAVEFORMS, CHANNEL BEING TURNED ON

(RL = 1kΩ)

V

DD

1

16

2

15 3 4 5 6 7 8

CD4051

I

14

DD

13

12

11

10

9

FIGURE 12. OFF CHANNEL LEAKAGE CURRENT - ANY CHANNEL OFF

1 2 3 4 5 6 7 8

CD4052

FIGURE 11. WAVEFORMS, CHANNEL BEING TURNED OFF

(RL = 1kΩ)

V

DD

16 15

I

14

DD

13 12 11 10

9

1 2 3 4 5 6 7 8

CD4053

V

DD

16 15 14 13 12 11 10

I

DD

9

CD4051B, CD4052B, CD4053B

Test Circuits and Waveforms (Continued)

V

DD

1

16

2

I

DD

15

3

14

4

13

5

12

6

11

7

10

8

9

CD4051

1 2

I

3

DD

4 5 6 7 8

CD4052

V

DD

16 15 14 13 12 11 10

9

1 2 3 4 5 6 7 8

V

DD

16 15

I

DD

14 13 12 11 10

9

CD4053

FIGURE 13. OFF CHANNEL LEAKAGE CURRENT - ALL CHANNELS OFF

V

DD

OUTPUT

1

16 2 3 4 5 6 7 8

CD4051

15

14

13

12

11

10

V

DD

V

EE

V

SS

R

L

V

DD

V

SS

CLOCK

9

V

SS

IN

OUTPUT

C

L

V

EE

R

C

L

V

EE

V

SS

EE

2

L

3

V

DD

4 5 6 7 8

CD4052

1

V

16

DD

15 14 13 12 11

V

DD

10

V

SS

9

V

SS

CLOCK

IN

V

SS

EE

1 2 3 4 5 6 7 8

CD4053

V

DD

16 15 14

R

L

13 12

V

DD

11

V

SS

10

9

V

SS

CLOCK

IN

OUTPUT

C

L

V

EE

FIGURE 14. PROPAGATION DELAY - ADDRESS INPUT TO SIGNAL OUTPUT

OUTPUT

1 2 3 4 5 6 7 8

AND t

16 15 14 13 12 11 10

PLH

V V

R

DD SS

L

CLOCK

IN

50pF

V

DD

V

EE

V

SS

EE

t

PHL

CD4051

FIGURE 15. PROPAGATION DELAY - INHIBIT INPUT TO SIGNAL OUTPUT

V

DD

µA

1K

1

16

2

15

3

1K

V

IH

V

IL

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 6)

14

4

13

5

12

6

11

7

10

89

CD4051B

V

DD

OUTPUT

1

50pF

R

L R

V

DD

V

SS

CLOCK

9

V

SS

V

IH

V

IL

IN

1 2 3

IH

IL

4 5 6 7 89

V

CD4052B

2 3

V

EE

4 5

V

DD

6 7

V

EE

V

8

SS

t

AND t

PHL

CD4052

V

DD

16

1K

15 14 13

1K

12 11 10

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL 2x)

µA

16 15 14 13 12 11 10

9

PLH

V

DD

OUTPUT

50pF

L

V

DD

V

SS

CLOCK

IN

V

SS

V

IH

V

IL

V

IH

IL

1

16

V

15 14 13 12 11 10

PLH

16 15 14 13 12 11 10

DD

9

V

SS

V

DD

µA

1K

V

IH

V

IL

2 3 4

V

EE

5

V

DD

6 7

V

EE

V

8

SS

t

AND t

PHL

CD4053

1

1K

2 3 4 5 6 7 89

CD4053B

MEASURE < 2µA ON ALL “OFF” CHANNELS (e.g., CHANNEL by)

FIGURE 16. INPUT VOLTAGE TEST CIRCUITS (NOISE IMMUNITY)

10

F

CD4051B, CD4052B, CD4053B

Test Circuits and Waveforms (Continued)

V

DD

Ι

1 2 3 4 5 6 7 89

CD4052

1 2 3 4 5 6 7 89

CD4051

Ι

CD4053

16 15 14 13 12 11 10

FIGURE 17. QUIESCENT DEVICE CURRENT FIGURE 18. CHANNEL ON RESISTANCE MEASUREMENT

DD

16 15 14 13 12 11 10

10kΩ

V

DD

V

SS

“ON”

CIRCUIT

TG

KEITHLEY

160 DIGITAL

MULTIMETER

1kΩ

RANGE

H.P.

MOSELEY

7030A

Y

X-Y

PLOTTER

X

V

DD

1

16

2

15

3

14

4

13

5

12

6

11

7

10

89

V

SS

CD4051 CD4053

NOTE: Measureinputssequentially,

V

DD

Ι

V

SS

V

SS

1 2 3 4 5 6 7 89

CD4052

to both VDD and VSS connect all unused inputs to either VDDor VSS.

V

DD

16 15 14 13 12 11 10

V

DD

Ι

V

SS

NOTE: Measureinputssequentially, to both VDD and VSS connect all unused inputs to either VDDor VSS.

FIGURE 19. INPUT CURRENT

5V

P-P

R

L

CHANNEL

OFF

CHANNEL

ON

R

VM

R

L

5V

P-P

V

DD

OFF

CHANNEL

6 7 8

1K

RF VM

COMMON

CHANNEL

ON

CHANNEL

OFF

R

L

RF VM

R

L

FIGURE 20. FEEDTHROUGH (ALL TYPES) FIGURE 21. CROSSTALK BETWEEN ANY TWO CHANNELS

(ALL TYPES)

5V

P-P

CHANNEL IN X

ON OR OFF

CHANNEL IN Y

ON OR OFF

R

L

RF VM

R

L

FIGURE 22. CROSSTALK BETWEEN DUALS OR TRIPLETS (CD4052B, CD4053B)

11

CD4051B, CD4052B, CD4053B

Test Circuits and Waveforms (Continued)

DIFFERENTIAL

SIGNALS

CD4052

DIFF.

AMPLIFIER/

LINE DRIVER

DIFF.

MULTIPLEXING

FIGURE 23. TYPICAL TIME-DIVISION APPLICATION OF THE CD4052B

Special Considerations

In applications where separate power sources are used to drive V should exceed V provision avoids permanent current ﬂow or clamp action on the V CD4051B, CD4052B or CD4053B.

A B C

and the signal inputs, the VDDcurrent capability

DD

DD/RL(RL

supply when power is applied or removed from the

DD

= effective external load). This

A B

CD4051B

C INH

COMMUNICATIONS

LINK

DIFF.

RECEIVER

CD4052

DEMULTIPLEXING

Q

A

D E

1/2

B

CD4556

E

0

Q

1

Q

2

A B C INH

CD4051B

COMMON OUTPUT

FIGURE 24. 24-TO-1 MUX ADDRESSING

12

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

PACKAGING INFORMATION

Orderable Device Status

7901502EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type 8101801EA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type CD4051BE ACTIVE PDIP N 16 25 Pb-Free

CD4051BEE4 ACTIVE PDIP N 16 25 Pb-Free

CD4051BF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD4051BF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD4051BM ACTIVE SOIC D 16 40 Green (RoHS &

CD4051BM96 ACTIVE SOIC D 16 2500 Green (RoHS &

CD4051BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD4051BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS &

CD4051BME4 ACTIVE SOIC D 16 40 Green (RoHS &

CD4051BMG4 ACTIVE SOIC D 16 40 Green (RoHS &

CD4051BMT ACTIVE SOIC D 16 250 Green (RoHS &

CD4051BMTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CD4051BMTG4 ACTIVE SOIC D 16 250 Green (RoHS &

CD4051BNSR ACTIVE SO NS 16 2000 Green (RoHS &

CD4051BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS &

CD4051BPW ACTIVE TSSOP PW 16 90 Green (RoHS &

CD4051BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CD4051BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

CD4051BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

CD4052BE ACTIVE PDIP N 16 25 Pb-Free

CD4052BEE4 ACTIVE PDIP N 16 25 Pb-Free

CD4052BF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD4052BF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD4052BM ACTIVE SOIC D 16 40 Green (RoHS &

CD4052BM96 ACTIVE SOIC D 16 2500 Green (RoHS &

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

no Sb/Br)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

CU NIPDAU N / A for Pkg Type

CU NIPDAU Level-1-260C-UNLIM

23-Apr-2007

(3)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

CD4052BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

23-Apr-2007

no Sb/Br)

CD4052BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BME4 ACTIVE SOIC D 16 40 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BMG4 ACTIVE SOIC D 16 40 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BMT ACTIVE SOIC D 16 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BMTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BMTG4 ACTIVE SOIC D 16 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BNSR ACTIVE SO NS 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BPW ACTIVE TSSOP PW 16 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4052BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BE ACTIVE PDIP N 16 25 Pb-Free

CU NIPDAU N / A for Pkg Type

(RoHS)

CD4053BEE4 ACTIVE PDIP N 16 25 Pb-Free

CU NIPDAU N / A for Pkg Type

(RoHS)

CD4053BF ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD4053BF3A ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type

CD4053BM ACTIVE SOIC D 16 40 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BM96 ACTIVE SOIC D 16 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BM96E4 ACTIVE SOIC D 16 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BM96G4 ACTIVE SOIC D 16 2500 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BME4 ACTIVE SOIC D 16 40 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BMG4 ACTIVE SOIC D 16 40 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BMT ACTIVE SOIC D 16 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

(3)

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

23-Apr-2007

(3)

no Sb/Br)

CD4053BMTE4 ACTIVE SOIC D 16 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BMTG4 ACTIVE SOIC D 16 250 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BNSR ACTIVE SO NS 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BNSRE4 ACTIVE SO NS 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BNSRG4 ACTIVE SO NS 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BPW ACTIVE TSSOP PW 16 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BPWE4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BPWG4 ACTIVE TSSOP PW 16 90 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BPWR ACTIVE TSSOP PW 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BPWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

CD4053BPWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS &

CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Apr-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

Device Package Pins Site Reel

Diameter

(mm)

CD4051BM96 D 16 MLA 330 16 6.5 10.3 12.1 2 16 Q1 CD4051BM96 D 16 FMX 0 16 6.5 10.3 12.1 2 16 Q1 CD4051BNSR NS 16 MLA 330 16 8.2 10.5 2.5 12 16 Q1

CD4051BPWR PW 16 MLA 330 12 7.0 5.6 1.6 8 12 Q1

CD4052BM96 D 16 FMX 0 16 6.5 10.3 12.1 2 16 Q1 CD4052BNSR NS 16 MLA 330 16 8.2 10.5 2.5 12 16 Q1

CD4052BPWR PW 16 MLA 330 12 7.0 5.6 1.6 8 12 Q1

CD4053BM96 D 16 FMX 0 16 6.5 10.3 12.1 2 16 Q1 CD4053BNSR NS 16 MLA 330 16 8.2 10.5 2.5 12 16 Q1

CD4053BPWR PW 16 MLA 330 12 7.0 5.6 1.6 8 12 Q1

Reel

Width

(mm)

A0 (mm) B0 (mm) K0 (mm) P1

(mm)W(mm)

30-Apr-2007

Pin1

Quadrant

TAPE AND REEL BOX INFORMATION

Device Package Pins Site Length (mm) Width (mm) Height (mm)

CD4051BM96 D 16 MLA 333.2 333.2 28.58 CD4051BM96 D 16 FMX 333.2 333.2 28.58

CD4051BNSR NS 16 MLA 333.2 333.2 28.58

CD4051BPWR PW 16 MLA 338.1 340.5 20.64

CD4052BM96 D 16 FMX 333.2 333.2 28.58

CD4052BNSR NS 16 MLA 333.2 333.2 28.58

CD4052BPWR PW 16 MLA 338.1 340.5 20.64

CD4053BM96 D 16 FMX 333.2 333.2 28.58

CD4053BNSR NS 16 MLA 333.2 333.2 28.58

CD4053BPWR PW 16 MLA 338.1 340.5 20.64

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Apr-2007

Pack Materials-Page 3

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

14

0,30

0,19

8

4,50 4,30

PINS **

7

Seating Plane

0,15

0,05

8

1

A

DIM

6,60 6,20

14

0,10

M

0,10

0,15 NOM

0°–8°

2016

Gage Plane

24

0,25

0,75 0,50

28

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265