Page 1
For Audio Equipment
MN66271RA
Signal Processing LSI for Compact Disc Players
Overview
The MN66271RA is a CD signal processing LSI that,
on a single chip, combines optics servos for the CD player
(focus, tracking, and traverse servos), digital signal
processing (EFM demodulation and error correction),
digital servo processing for the spindle motor, digital
filter, and D/A converter, so thus covers all signal
processing functions from the head's RF amplifier onward.
Features
(Optics servo)
Focus, tracking, and traverse servos
Automatic adjustment functions for FO/TR gain,
FO/TR offset, and FO/TR balance
Built-in D/A converter for drive voltage output
Built-in dropout countermeasures
Anti-shock functions
Built-in track cross counter
Support for both linear motor and screw-based
traverse mechanisms
Support for 3- and 1-beam systems Digital Signal
Processing
(Spindle motor servo)
CLV digital servo
(Audio circuits)
Digital filter using 8 times oversampling
Built-in D/A converter (1-bit D/A converter)
Built-in differential operational amplifier (±PWM
output)
(Other)
Built-in playback pitch control function (±13%)
Operating voltage 4.5 to 5.5 V
Applications
CD Players
(Digital signal processing)
Built-in DSL and PLL
Frame synchronization detection, holding, and
insertion
Subcode data processing
Subcode Q data CRC check
Built-in subcode Q data register
CIRC error detection and correction
C1 decoder: duplex error correction
C2 decoder: triplex error correction
Built-in 16-K bits of RAM for use in deinterleaving
Audio data interpolation
Averaging or retention of previous values
Soft muting
Digital attenuation (256 levels)
Software attenuation (256 levels)
Audio data peak level detection function
Automatic cuing detection function
Digital audio interface (EIAJ format)
Audio data serial interface
Page 2
MN66271RA For Audio Equipment
Pin Assignment
BYTCK
CLDCK
FCLK
IPFLAG
FLAG
CLVS
CRC
DEMPH
RESY
RST2
TEST
AV
DD1
OUTL
AV
SS1
OUTR
RSEL
CSEL
PSEL
MSEL
SSEL
SS2AVDD2
VDDX2X1VSSSBCK
SUBC
PDO
PCK
EFM
AV
VCOF
PLLF
DSLF
60595857565554535251504948474645444342
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
12345678910111213141516171819
SS1
TX
BCLK
LRCK
DD1
DV
DV
SRDATA
MCLK
MDATA
MLD
SENSE
FLOCK
TLOCK
BLKCK
SQCK
REF
DRF
I
SUBQ
DMUTE
ARF
WVEL
RST
STAT
PLAY
TES
41
20
SMCK
PMCK
40
LDON
39
BDO
38
RFDET
37
TRCRS
36
OFT
35
VDET
34
RFENV
33
TE
32
FE
31
TBAL
30
FBAL
29
V
28
27
26
25
24
23
22
21
REF
FOD
TRD
KICK
ECS
ECM
PC
TVD
TRV
(TOP VIEW)
QFS080-P-1414
Page 3
For Audio Equipment MN66271RA
Block Diagram
RST2
AV
SS2
AV
DD2
CLVS
CRC
BLKCK
CLDCK
SBCK
SUBC
DEMPH
RESY
SSEL
SQCK
SUBQ
PCK
EFM
PLLF
DSLF
I
REF
DRF
ARF
RSEL
PSEL
MLD
MCLK
MDATA
VCOF
BYTCK
SMCK
FCLK
PMCK
CSEL
MSEL
X2
X1
STAT
51
50
66
67
13
62
56
55
68
69
80
14
15
BUFFER
SUBCODE
53
52
48
47
45
46
44
76
DSL•PLL VCO
78
9
7
8
49
61
19
63
20
77
79
59
58
TIMING GENERATOR
PITCH CONTROL
17
70
DIGITAL
DEEMPHASIS
8 TIMES
OVER SAMPLING
DIGITAL FILTER
EFM DEMODULATION
SYNC INTERPOLATION
SUBCODE DEMODULATION
LOGICS
1 BIT DAC
16K
SRAM
CIRC ERROR CORRECTION
DEINTERLEAVE
VCO
INTERFACE
MICROCOMPUTER
A/D CONVERTER INPUT PORT
)
R
(
PWM
)
L
(
PWM
DIGITAL
AUDIO
INTERFACE
CLV
SERVO
INTERPOLATION
SOFT MUTING
DIGITAL
ATTENUATION
PEAK DETECT
AUTO CUE
SERVO CPU
–
+
–
+
D/A
OUTPUT
SERVO
TIMING GENERATOR
75
73
74
72
65
64
6
24
23
2
3
1
16
21
26
29
25
22
27
28
31
CONVERTER
30
41
12
11
42
PORT
40
43
10
OUTR
OUTL
AV
SS1
AV
DD1
FLAG
IPFLAG
TX
ECM
PC
LRCK
SRDATA
BCLK
DMUTE
TRV
KICK
V
REF
ECS
TVD
TRD
FOD
TBAL
FBAL
TES
TLOCK
FLOCK
PLAY
LDON
WVEL
SENSE
60574518
SS
DD
V
SS1
DD1
V
DV
DV
71
RST
TEST
32
FE
33TE34
RFENV
37
TRCRS
35
VDET
39
BDO
38
RFDET
36
OFT
Page 4
MN66271RA For Audio Equipment
Pin Descriptions
Pin No. Symbol I/O Function Description
1 BCLK O SRDATA bit clock output
2 LRCK O Left/right channel discrimination signal output
3 SRDATA O Serial data output
4DV
5DV
DD1
SS1
6 TX O Digital audio interface output signal
7 MCLK I Microcomputer command clock input (Data is latched at rising edge.)
8 MDATA I Microcomputer command data input
9 MLD I Microcomputer command load signal input. "L" level: load.
10 SENSE O Sense signal output (OFT, FESL, NACEND, NAJEND, POSAD, and SFG)
11 FLOCK O Focus servo convergence signal. "L" level: convergence.
12 TLOCK O Tracking servo convergence signal. "L" level: convergence.
13 BLKCK O Subcode block clock signal (f
14 SQCK I External clock input for subcode Q register
15 SUBQ O Subcode Q data output
16 DMUTE I Muting input. "H" level: muting.
17 STAT O Status signal (CRC, CUE, CLVS, TTSTOP, FCLV, and SQOK)
18 RST I Reset input. "L" level: reset.
19 SMCK O If MSEL is at "H" level, 8.4672 MHz clock signal output.
20 PMCK O 88.2 kHz clock signal output
21 TRV O Traverse forced feed output
22 TVD O Traverse drive output
23 PC O Spindle motor ON signal. "L" level: ON.
24 ECM O Spindle motor drive signal (forced mode output) 3-State
25 ECS O Spindle motor drive signal (servo error signal output)
26 KICK O Kick pulse output
27 TRD O Tracking drive output
28 FOD O Focus drive output
29 V
REF
30 FBAL O Focus balance adjustment output
31 TBAL O Tracking balance adjustment output
32 FE I Focus error signal input (analog input)
33 TE I Tracking error signal input (analog input)
34 RFENV I RF envelope signal input (analog input)
35 VDET I Vibration detection signal input. "H" level: vibration detected.
36 OFT I Offtrack signal input. "H" level: offtrack.
37 TRCRS I Track cross signal input
38 RFDET I RF detection signal input. "L" level: detected.
39 BDO I Dropout signal input. "H" level: dropout.
40 LDON O Laser ON signal output. "H" level: ON.
I Power supply for digital circuits
I Ground for digital circuits
=75 Hz, normal playback)
BLKCK
If MSEL is at "L" level, 4.2336 MHz clock signal output.
I Reference voltage for DA output (TVD, ECS, TRD, FOD, FBAL, and
TBAL)
Page 5
For Audio Equipment MN66271RA
Pin Descriptions (continued)
Pin No. Symbol I/O Function Description
41 TES O Tracking error shunt signal. "H" level: shunt.
42 PLAY O Play signal output. "H" level: play.
43 WVEL O Double-speed status signal output. "L" level: double-speed.
44 ARF I RF signal input
45 I
REF
46 DRF I DSL bias pin
47 DSLF I/O DSL loop filter pin
48 PLLF I/O PLL loop filter pin
49 VCOF I/O VCO loop filter pin for pitch control
50 AV
51 AV
DD2
SS2
52 EFM O EFM signal output
53 PCK O PLL derived clock output with f
54 PDO O Phase comparator output for EFM and PCK signals
55 SUBC O Subcode serial output data output
56 SBCK I Serial clock input for subcode serial output
57 V
SS
58 X1 I Crystal oscillator circuit input pin. f=16.9344 MHz.
59 X2 O Crystal oscillator circuit output pin. f=16.9344 MHz.
60 V
DD
61 BYTCK O Byte clock signal output
62 CLDCK O Subcode frame clock signal output pin (f
63 FCLK O Crystal frame clock signal output (f
64 IPFLAG O Interpolation flag signal output. "H" level: interpolation.
65 FLAG O Flag signal output
66 CLVS O Spindle servo phase synchronization signal output. "H" level: CLV.
67 CRC O Subcode CRC check result output. "H" level: OK. "L" level: no good.
68 DEMPH O De-emphasis detection signal output. "H" level: ON.
69 RESY O Frame resynchronization signal. "H" level: synchronized.
70 RST2 I Reset pin for stopping operation of circuits past D/A converter
71 TEST I Test pin. Keep this pin at "H" level.
72 AV
DD1
73 OUTL O Left channel audio output
74 AV
SS1
75 OUTR O Right channel audio output
76 RSEL I RF signal polarity selection pin. "H" level: bright level is "H.
77 CSEL I Test pin. Keep this pin at "L" level.
I Reference current input pin
I Power supply for analog circuits (DSL, PLL, and D/A converter output)
I Ground for analog circuits (DSL, PLL, and D/A converter output)
=4.3218 MHz
PCK
I Ground for oscillator circuit
I Power supply for oscillator circuit
=7.35 kHz)
CLDCK
=7.35 kHz)
FCLK
"L" level: rough servo.
"L" level: out of sync.
I Power supply for analog circuits (common use for by left and right channel
audio outputs)
I Ground for analog circuits (common use for left and right channel audio
outputs)
"L" level: bright level is "L.
Page 6
MN66271RA For Audio Equipment
Pin Descriptions (continued)
Pin No. Symbol I/O Function Description
78 PSEL I Test pin. Keep this pin at "L" level.
79 MSEL I Frequency selection pin for SMCK pin output.
"H" level: SMCK=8.4672 MHz.
"L" level: SMCK=4.2336 MHz.
80 SSEL I SUBQ pin output mode selection pin. "H" level: buffered subcode Q mode.
Package Dimensions (Unit: mm)
QFS080-P-1414
16.2±0.2
14.0±0.2
4160
61
80
0.15
0.65
SEATING PLANE
0.3
201
+0.10
-
0.05
40
21
0.825
14.0±0.2
2.0±0.2
2.1±0.3
0.1±0.1
16.2±0.2
0.05
-
+0.10
0.15
1.1±0.1
0 to 10°
0.55±0.1
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