Page 1
For Communications Equipment
MN6153UC
PLL LSI with Built-In Prescaler
Overview
The MN6153UC is a CMOS LSI for a phase-locked
loop (PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (0.5
mW for V
=1.03 V, FIN= 60 MHz).
DD
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Features
Low power supply voltage: VDD=1.0 to 1.4V
Low power consumption: 0.5mW (VDD=V1.03V,
F
=60MHz)
IN
High-speed operation: FIN=60MHz
(V
=1.03V)
DD
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage:
272 to 262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and reference
frequency dividing stages
Pin Assignment
X
X
OUT
FV
V
D
V
V
F
DD
1
IN
2
3
4
5
OP
6
SS
7
CP
8
IN
SSOP016-P-0225
(TOP VIEW)
OR
16
OV
15
LC
14
FR
13
PS
12
LE
11
DATA
10
CLK
9
Page 2
MN6153UC For Communications Equipment
Block Diagram
FR
13
LC
14
Phase comparator
17-bit latch
17-bit programmable counter
Control
18-bit shift register
OVORV
15
16
CPDOP
7
5
18-bit latch
FV
3
14-bit programmable
counter
Phase
matching
1
IN
X
Swallow
counter
Data control
Prescaler and
phase matching
2
OUT
X
9
CLK
10
DATA
PS
8
IN
F
11
12
LE
Page 3
For Communications Equipment MN6153UC
Pin Descriptions
Pin No. Symbol Function Description
1X
2X
IN
OUT
3 FV Frequency divider output signal in comparator stage.
4VDDPower supply
5DOPLow-pass filter connection pin. Use a passive filter.
6VSSGround
7VCPPower supply pin for built-in charge pump
8FINFrequency divider input pin in comparator stage.
9 CLK Shift register clock input pin.
10 DATA Shift register data input pin.
11 LE Load enable signal input pin.
12 PS Power save control signal input pin.
13 FR Reference frequency divider output signal.
14 LC Charge pump control signal output pin.
15 OV Phase comparator output pin for external charge pump.
16 OR (OR provides N-channel open drain output.)
Crystal oscillator connection pins:
XIN =Oscillator circuit input pin;
X
=Oscillator circuit output pin.
OUT
Phase comparator input monitor.
The chip latches data at the rising edge of the CLK signal.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
This is the latch-write-enable signal. It is at "H" level for write.
"H" level input starts the frequency divider and places the chip in operational mode.
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
Phase comparator input monitor.
When frequency divider operation is stopped, this pin is at "L" level,
the internal charge pump output is in the high-impedance state, and the loop is
opened.
Page 4
MN6153UC For Communications Equipment
MN6153 Frequency Dividing Data Settings
The following formula shows frequency divider operation.
F
={ (16 × N) + A} × (XIN ÷ R)
IN
where
F
N : Setting for 14-bit programmable counter on comparator side
A : Setting for 4-bit swallow counter on comparator side
X
R : Setting for 17-bit programmable counter on reference side
Note that N should be greater than A.
N-Side Latch Data
MSB 3 bits 14 bits 4 bits LSB
Test data Programmable counter Swallow counter
: VCO output frequency
IN
: Reference oscillator frequency
IN
setting (N) setting (A)
Page 5
For Communications Equipment MN6153UC
Note on Setting Frequency Dividing Data Input
1) Frequency dividing data input
(1) Reference side
Data input direction
MSB LSB
1 2 17 18 19
CLK
DATA
MSB LSB
LE
(2) Comparating side
Data input direction
1
*
3-bit test data
3 bits "L" level
12345 2122 23
CLK
17-bit frequency dividing data
18-bit frequency dividing data
Control bits
1 bit
Frequencey
dividing stage selection
"H" level
Control bits
1 bit 1 bit
Frequencey
dividing stage selection
"L" level
1 bit
Write selection
"H" level
Write selection
"H" level
"L"
"L"
DATA
MSB LSB
LE
Notes
Preceding the input of the frequency dividing data for the comparating side, input test data consisting of
1.*1:
three "L" level bits to produce normal operation. Never use any other pattern.
2.
When the power is first applied, internal operation remains in an unstable state until data is written. To
eliminate the risk of excessive current consumption, keep the PS pin at "L" level.
3.
When the power is first applied, the data settings are indeterminate. Always write data to the chip before
starting operation.
4.
Enter the data to fill the entire latch:
Reference side: 19 bits (17 bits for the frequency divider setting and 2 control bits)
Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2
control bits)
5.
Drive the LE pin at "L" level while writing the data.
6.
"H" level input from the LE pin causes the chip to read the data only when the CLK pin and the DATA pin
are both at "L" level.
7.
Writes are possible when the PS pin is either "H" or "L" level.
8.
Input the data MSB first.
9.
The data are inputted at the rising edge of the CLK signal.
Page 6
MN6153UC For Communications Equipment
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Power supply voltage V
Power supply voltage V
Input pin voltage V
Output pin voltage V
Power dissipation P
Operating ambient temperature T
Storage temperature T
Operating Conditions
VSS=0V, Ta=–10 to +60˚C
Parameter Symbol Test Conditions min typ max Unit
Power supply voltage V
Power supply voltage V
Electric Characteristics
VCP=2.5V, Ta=–10 to +60˚C
Parameter Symbol Test Conditions min typ max Unit
Power supply pin V
Power supply current I
I
Dstop
Input Pins CLK, DATA, LE, PS V
"H" level input voltage V
"L" level input voltage V
Input leakage current I
Input Pin F
Input voltage V
Input current I
Input leakage current I
Maximum operating frequency F
Minimum operating frequency F
Input Pin X
Input voltage V
Input current I
Input leakage current I
VDD=1.03 to 1.4V
IN
VDD=1.0 to 1.4V
IN
INMAX
INMIN
DD
opr
stg
DD
DD
DD
LI
IF
LIF
IX
LIX
CP
I
O
D
CP
IH
IL
IN
IN
VDD=1.03V
FIN=100MHz, XIN=20MHz, 0.5 mA
PS="H"
PS="L" (at power save operation) 2.0 µA
=1.0 to 1.4V
DD
Pull-up resistor is present
(PS="L")
VIN=0 or VDD (PS="H") ±20 µA
VIN=0.4 V
VIN=0.4 V
Pull-up resistor is present
(PS="L")
VIN=0 or V
– 0.3 to +3.0
– 0.3 to +4.0
V
– 0.3 to VDD +0.3
SS
V
– 0.3 to VDD +0.3
SS
20 mW
–10 to +60
–55 to +125
p-p
p-p
DD
V
˚C
1.0 1.1 1.4 V
2.5 3.0 3.2 V
V
– 0.2 V
DD
V
SS
DD
0.2
±1.0 µ A
0.4 V
–10 –100 µA
60 MHz
10 MHz
0.4 V
– 0.2 –1.5 mA
2.0 µA
V
p-p
p-p
Page 7
For Communications Equipment MN6153UC
Electrical Characteristics (continued)
VCP=2.5V, Ta=–10 to +60˚C
Parameter Symbol Test Conditions min typ max Unit
Crystal Oscillator Pins XIN, X
Crystal oscillator frequency f
Output Pins FV, FR, LC, OV V
"H"level output voltage V
"L"level output voltage V
Output Pin X
VDD=1.0 to 1.4V
OUT
"H"level output voltage V
"L"level output voltage V
Output Pin DOP V
=1.0 to 1.4V
DD
"H"level output voltage I
"L"level output voltage I
Output leak current I
Output leak current I
Output Pin OR V
=1.0 to 1.4V
DD
"L"level output voltage I
VDD=1.0 to 1.4V
Setup time *
Hold time *
1
1
VDD=1.03 to 1.4V
OUT
Xtal
=1.0 to 1.4V
DD
OH
OL
XOH
XOL
DOH
DOL
LOH
LOL
ORL
t
sul
t
su2
t
H
12.8 MHz
IOH= –60µA VDD– 0.3 V
IOL=30µA V
I
= –100µA VDD– 0.3 V
XOH
I
=100µA V
XOL
V
Dop=VCP
V
Dop
V
Dop=VCP
V
Dop
– 0.3V –250
=0.3V 250
=0.0V –2.0
SS
SS
0.3
0.3
2.0
DD
DD
V
V
µA
VOR=0.3V 45 µA
500 ns
500 ns
500 ns
Note*1: The following timing chart shows the setup and hold times.
DATA
50%
t
su1
t
H
CLK
t
su2
LE
Usage Note
Be particularly careful with this product as it is more sensitive on the static electricity damage than most of
our other products.
Page 8
MN6153UC For Communications Equipment
Application Circuit Example
Intermittent
operation
control
Frequency dividing
data generation input
Frequency dividing
data generation input
Frequency dividing
data generation input
16
OR
MN6153UC
INXOUT
X
1
10pF
12pF
15
OV
2
12pF
14
LC
FV
3
12.8MHz
13
4
FR
V
DD
12
PS
11
LE
10
DATA
9
CLK
VCO characteristics may necessitate
1:
OP
D
5
6
CP
SS
V
7
IN
V
F
Note *
design revisions.
8
Amplifier
=3V
CC
V
1000pF
0.1µF
0.1µF
=3V
CP
V
50 to 60MHz
390Ω
10µF
=1.0V to 1.4V
DD
V
10kΩ 100Ω
1µF
35kΩ
VCO
0.22µF
*1Loop filter
VF
V
CC
Page 9
For Communications Equipment MN6153UC
Package Dimensions (Unit: mm)
SSOP016-P-0225
6.5±0.2
16
9
1.0±0.1
0.05
-
4.3±0.2
6.3±0.2
+0.10
0.15
0 to 10°
0.5±0.1
1
(0.45)
0.8
0.15
0.35±0.10
8
1.45±0.200.1±0.1
SEATING PLANE
1.55±0.30
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