Page 1
For Communications Equipment
MN6152U
PLL LSI with Built-In Prescaler
Overview
The MN6152U is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.8 to 2.5 V) and low power consumption (5 mW
for V
=2.0 V, FIN=100 MHz).
DD
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
Features
Low power supply voltage: VDD=1.8 to 2.5V
Low power consumption: 5mW (VDD=2.0V,
F
=100MHz)
IN
High-speed operation: FIN=175MHz
Frequency dividing ratios in reference frequency
dividing stage: 5 to 131,071
Frequency dividing ratios in comparator stage: 272 to
262,143
Lock detector output pin
Two types of phase comparator output
- Internal charge pump output
- Output for external charge pump
Output monitor pins for both comparator and refer-
ence frequency dividing stages
Pin Assignment
X
X
OUT
FV
V
D
V
LD
F
DD
1
IN
2
3
4
5
OP
6
SS
7
8
IN
SSOP016-P-0225
(TOP VIEW)
OR
16
OV
15
LC
14
FR
13
PS
12
LE
11
DATA
10
CLK
9
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MN6152U For Communications Equipment
Block Diagram
FR
13
LC
14
Phase comparator
17-bit latch
17-bit programmable counter
Control
18-bit shift register
16
OR
OP
D
5
FV
3
14-bit programmable
counter
LD
OV
7
15
18-bit latch
Phase
matching
Amplifier
1
IN
X
Swallow
counter
Data control
Prescaler and
phase matching
Amplifier
2
OUT
X
9
CLK
10
DATA
11
LE
12
PS
8
IN
F
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For Communications Equipment MN6152U
Pin Descriptions
Pin No. Symbol Function Description
1X
2X
IN
OUT
3FV
4VDDPower supply
Crystal oscillator connection pins:
XIN =Oscillator circuit input pin;
X
=Oscillator circuit output pin.
OUT
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
5D
OP
Low-pass filter connection pin. Use a passive filter.
6VSSGround
7LD
Phase comparator output pin:
"H" level for locked; "L"level for unlocked.
8FINFrequency divider input pin in comparating stage.
9 CLK
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
Shift register data input pin.
10 DATA
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
Load enable signal input pin.
11 LE
This is the latch-write-enable signal. It is at "H" level for write.
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational mode.
12 PS
"L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
13 FR
Reference frequency divider output signal.
Phase comparator input monitor.
Charge pump control signal output pin.
14 LC
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
15 OV
16 OR
Phase comparator output pin for external charge pump.
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MN6152U For Communications Equipment
MN6152 Frequency Dividing Data Settings
The following formula shows frequency divider operation.
F
={ (16 × N) + A} × (XIN ÷ R)
IN
where
F
N : Setting for 14-bit programmable counter on comparator side
A : Setting for 4-bit swallow counter on comparator side
X
R : Setting for 17-bit programmable counter on reference side
Note that N should be greater than A.
N-Side Latch Data
MSB 14 bits 4 bits LSB
: VCO output frequency
IN
: Reference oscillator frequency
IN
Programmable counter setting (N) Swallow counter setting (A)
Page 5
For Communications Equipment MN6152U
Absolute Maximum Ratings
Parameter Symbol Rating Unit
Power supply voltage V
DD
Input pin voltage V
Output pin voltage V
Power dissipation P
Operating ambient temperature T
Storage temperature T
opr
stg
Operating Conditions
VSS=0V, Ta=–20 to +60˚C
Parameter Symbol Test Conditions min typ max Unit
Power supply voltage V
DD
Electric Characteristics
VDD=2V, Ta=–20 to +60˚C
Parameter Symbol Test Conditions min typ max Unit
Power supply voltage I
Input Pins CLK, DATA, LE, and PS V
"H" level input voltage V
"L" level input voltage V
Input leakage current I
Input Pin F
IN
V
=1.8 to 2.5V
DD
Input voltage V
Input current I
Input leakage current I
Maximum operating frequency F
Minimum operating frequency F
Input Pin X
VDD=1.8 to 2.5V
IN
Input voltage V
Input current I
Input leakage current V
Maximum operating frequency X
DD
I
Dstop
LI
IF
LIF
INMAX
INMIN
IX
LIX
INMAX
I
O
D
FIN=100MHz, XIN=20MHz, 2.5 mA
PS="H"
PS ="L" (at power save operation) 10 µA
=1.8 to 2.5V
DD
IH
IL
IN
Pull-up resistor present –100 µA
(PS="L")
VIN=0 or 2V (PS="H") ±20 µA
VIN=0.4 V
VIN=0.4 V
IN
Pull-up resistor present 2.5 mA
(PS="L")
VIN=0 or 2V 5.0 µA
VIN=0.4 V
– 0.3 to +3.5
V
– 0.3 to VDD +0.3 V
SS
V
– 0.3 to VDD +0.3
SS
20 mW
–20 to +60
–55 to +125
1.8 2.0 2.5 V
V
– 0.2 V
DD
V
SS
0.4 V
p-p
p-p
175 MHz
0.4 V
p-p
20 MHz
˚C
DD
0.2
V
±1.0 µA
10 MHz
p-p
p-p
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MN6152U For Communications Equipment
Electrical Characteristics
VDD=2V, Ta=–20 to +60˚C
Parameter Symbol Test Condition min typ max Unit
Crystal Oscillator Pins XIN, X
Crystal oscillator frequency f
Output Pins FV, FR, LC, OV V
"H" level output voltage V
"L" level output voltage V
Output Pin X
VDD=1.8 to 2.5V
OUT
"H" level output voltage V
"L" level output voltage V
Output Pin D
VDD=1.8 to 2.5V
OP
"H" level output voltage I
"L" level output voltage I
Output Pin OR V
=1.8 to 2.5V
DD
"L" level output voltage I
OUT
Xtal
DD
OH
OL
XOH
XOL
DOH
DOL
ORL
VDD=1.8 to 2.5V
20 MHz
=1.8 to 2.5V
IOH= –100µAV
IOL= 100µAV
I
= –500µAV
XOH
I
= 500µAV
XOL
V
=1.6V –100
Dop
V
=0.4V 100
Dop
– 0.3 V
DD
SS
– 0.3 V
DD
SS
DD
0.3
DD
0.3
VOR=0.4V 100 µA
V
V
µA
Setup time *
Hold time *
1
1
t
sul
t
su2
t
H
500 ns
500 ns
500 ns
Note*1: The following timing chart shows the setup and hold times.
DATA
50%
t
su1
t
H
CLK
t
su2
LE
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For Communications Equipment MN6152U
Frequency Divider Setting
R-side latch
CLK
DATA
LE
N-side latch
CLK
DATA
LE
1 2 3 4 5 6 7 8 9 10111213141516171819
MSB
1 2 3 4 5 6 7 8 9 1011121314151617181920
MSB
LSB
LSB
· Input the data MSB first.
· The data is read at the rising edges of the CLK signal.
· Drive the LE pin at "L" level when writing data.
Usage Note
Be particularly careful with this product as it is more sensitive on the static electricity damage than most of
our other products.
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MN6152U For Communications Equipment
Package Diemnsions (Unit: mm)
SSOP016-P-0225
6.5±0.2
16
9
1.0±0.1
0.05
-
4.3±0.2
6.3±0.2
+0.10
0.15
0 to 10°
0.5±0.1
1
(0.45)
0.8
0.15
0.35±0.10
8
1.45±0.200.1±0.1
SEATING PLANE
1.55±0.30
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