Page 1
1
Motorola TMOS Power MOSFET Transistor Device Data
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance area product about one–half that of standard MOSFET s. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low R
DS(on)
Technology
• Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETS
• Avalanche Energy Specified
• I
DSS
and V
DS(on)
Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Available in 12 mm Tape & Reel
Use MMFT3055VLT1 to order the 7 inch/1000 unit reel
Use MMFT3055VLT3 to order the 13 inch/4000 unit reel
MAXIMUM RATINGS
(TC = 25°C unless otherwise noted)
Rating
Symbol Value Unit
Drain–to–Source Voltage V
DSS
60 Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) V
DGR
60 Vdc
Gate–to–Source Voltage – Continuous
Gate–to–Source Voltage – Non–repetitive (tp ≤ 10 ms)
V
GS
V
GSM
± 15
± 20
Vdc
Vpk
Drain Current – Continuous
Drain Current – Continuous @ 100°C
Drain Current – Single Pulse (tp ≤ 10 µs)
I
D
I
D
I
DM
1.5
1.2
5.0
Adc
Apk
Total PD @ TA = 25°C mounted on 1” sq. Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on 0.70” sq. Drain pad on FR–4 bd material
Total PD @ TA = 25°C mounted on min. Drain pad on FR–4 bd material
Derate above 25°C
P
D
2.1
1.7
0.94
6.3
Watts
mW/°C
Operating and Storage Temperature Range TJ, T
stg
–55 to 175 °C
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 Ω )
E
AS
58
mJ
Thermal Resistance
– Junction to Ambient on 1” sq. Drain pad on FR–4 bd material
– Junction to Ambient on 0.70” sq. Drain pad on FR–4 bd material
– Junction to Ambient on min. Drain pad on FR–4 bd material
R
θJA
R
θJA
R
θJA
70
88
159
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds T
L
260 °C
Designer’s Data for “Worst Case” Conditions —The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
Order this document
by MMFT3055VL/D
SEMICONDUCTOR TECHNICAL DATA
TM
TMOS POWER FET
1.5 AMPERES
60 VOLTS
R
DS(on)
= 0.140 OHM
D
S
G
CASE 318E–04, Style 3
TO–261AA
1
2
3
4
Motorola, Inc. 1996
Page 2
MMFT3055VL
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3)
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V
(BR)DSS
60
—
—
65
—
—
Vdc
mV/°C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C)
I
DSS
—
—
—
—
10
100
µAdc
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0 Vdc) I
GSS
— — 100 nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage (Cpk ≥ 2.0) (3)
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V
GS(th)
1.0
—
1.5
3.7
2.0
—
Vdc
mV/°C
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3)
(VGS = 5.0 Vdc, ID = 0.75 Adc)
R
DS(on)
— 0.125 0.14 Ohm
Drain–to–Source On–Voltage
(VGS = 5.0 Vdc, ID = 1.5 Adc)
(VGS = 5.0 Vdc, ID = 0.75 Adc, TJ = 150°C)
V
DS(on)
—
—
—
—
0.25
0.24
Vdc
Forward Transconductance (VDS = 8.0 Vdc, ID = 1.5 Adc) g
FS
1.0 3.5 — mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
C
iss
— 350 490 pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
C
oss
— 110 150
Transfer Capacitance
f = 1.0 MHz)
C
rss
— 29 60
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
t
d(on)
— 9.5 20 ns
Rise Time
t
r
— 18 40
Turn–Off Delay Time
VGS = 5.0 Vdc,
RG = 9.1 Ω)
t
d(off)
— 35 70
Fall Time
G
= 9.1 Ω)
t
f
— 22 40
Q
T
— 9.0 10 nC
DS
= 48 Vdc, ID = 1.5 Adc,
Q
1
— 1.0 —
(VDS = 48 Vdc, ID = 1.5 Adc,
VGS = 5.0 Vdc)
Q
2
— 4.0 —
Q
3
— 3.5 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage (1)
(IS = 1.5 Adc, VGS = 0 Vdc)
(IS = 1.5 Adc, VGS = 0 Vdc, TJ = 150°C)
V
SD
—
—
0.82
0.68
1.2
—
Vdc
t
rr
— 41 —
S
= 1.5 Adc, VGS = 0 Vdc,
t
a
— 29 —
(IS = 1.5 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
t
b
— 12 —
Reverse Recovery Stored Charge Q
RR
— 0.066 — µC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
L
D
— 4.5 —
nH
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
L
S
— 7.5 —
nH
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
Max limit – Typ
3 x SIGMA
Gate Charge
Reverse Recovery Time
(VDD = 30 Vdc, ID = 1.5 Adc,
(V
(I
ns
Page 3
MMFT3055VL
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE
(NORMALIZED)
0 1 2 3 4 5
0
1.5
2.5
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics
I
D
, DRAIN CURRENT (AMPS)
0 1 2 3 4
0
1.5
3
4
I
D
, DRAIN CURRENT (AMPS)
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0 0.5 1 2.5 4
0
0.05
0.1
0.15
R
DS(on)
, DRAIN–TO–SOURCE RESISTANCE (OHMS)
0 1 3.5 4
0
0.025
0.15
0.2
ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current
and Gate Voltage
– 50
0.6
0.8
1.2
1.6
0 20 50 60
10
100
1000
TJ, JUNCTION TEMPERATURE (
°
C)
Figure 5. On–Resistance Variation with
Temperature
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 6. Drain–To–Source Leakage
Current versus Voltage
I
DSS
, LEAKAGE (nA)
– 25 0 25 50 75 100 125 150
TJ = 25
°C
VDS ≥ 10 V
TJ = – 55
°C
25
°C
100
°C
TJ = 25
°C
VGS = 0 V
VGS = 5 V
ID = 0.75 A
3 V
2 V
2.5 V
0.5
1
2
0.5 1.5 2.5 3.5
0.5
2
3.5
VGS = 5 V
TJ = 100
°C
25
°C
– 55
°C
2 3.5 0.5 2 2.5
10 30 40
0.025
0.075
0.125
0.05
0.175
0.075
1.0
1.4
TJ = 125
°C
VGS = 10 V
15 V
175
6 7 8 9 10
2.5
1
31.5
0.175
0.2
0.125
1.5 3
0.1
0.4
0.2
0
1.8
2.0
100
°C
3
3.5
4
6 V
4.5 V
3.5 V
4.5 5 5.5
0.225
0.25
6 6.5
0.225
0.25
1
Page 4
MMFT3055VL
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are determined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculating rise and fall because drain–gate capacitance varies
greatly with applied voltage. Accordingly , gate charge data is
used. In most cases, a satisfactory estimate of average input
current (I
G(AV)
) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as
the plateau voltage, V
SGP
. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG – V
GSP
)
tf = Q2 x RG/V
GSP
where
VGG = the gate drive voltage, which varies from zero to V
GG
RG = the gate drive resistance
and Q2 and V
GSP
are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= RG C
iss
In [VGG/(VGG – V
GSP
)]
t
d(off)
= RG C
iss
In (VGG/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off–state condition when calculating t
d(on)
and is read at a voltage corresponding to the
on–state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex.
The M OSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resistance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely operated into an inductive load; however, snubbing reduces
switching losses.
10 0 10 15 25
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
C, CAPACITANCE (pF)
Figure 7. Capacitance Variation
V
GS
V
DS
TJ = 25
°C
VDS = 0 V
VGS = 0 V
600
500
400
300
200
100
0
20
C
iss
C
oss
C
rss
5 5
C
iss
C
rss
800
900
700
1000
Page 5
MMFT3055VL
5
Motorola TMOS Power MOSFET Transistor Device Data
V
DS
, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
V
GS
, GATE–TO–SOURCE VOLTAGE (VOLTS)
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
0.6 0.625 0.675 0.775
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 8. Gate–To–Source and Drain–To–Source
Voltage versus Total Charge
I
S
, SOURCE CURRENT (AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1 10 100
t, TIME (ns)
VDD = 30 V
ID = 1.5 A
VGS = 5 V
TJ = 25
°
C
t
f
t
d(off)
VGS = 0 V
TJ = 25
°
C
0
QT, TOTAL CHARGE (nC)
2 3 4 5
ID = 1.5 A
TJ = 25
°
C
V
GS
0
1.2
1.6
1000
100
10
1
10
6
2
0
1
8
4
30
27
24
21
18
15
0
V
DS
6
0.8
0.65 0.7 0.725
0.4
0.75
QT
Q1 Q2
Q3
71
t
d(on)
t
r
Figure 10. Diode Forward Voltage versus Current
7
3
9
5
12
3
6
9
1
1.4
0.6
0.2
0.8
8 9 10
0.825 0.85
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum s imultaneous drain–to–source voltage and
drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance–General
Data and Its Use.”
Switching between the off–state and the on–state may traverse any load line provided neither rated peak current (IDM)
nor rated voltage (V
DSS
) is exceeded and the transition time
(tr,tf) do not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed
(T
J(MAX)
– TC)/(R
θJC
).
A Power MOSFET designated E–FET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms o f energy, avalanche e nergy capability i s not a
constant. The energy rating decreases non–linearly with an
increase of peak current in avalanche and peak junction temperature.
Although many E–FETs can withstand the stress of drain–
to–source avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating m ust be d erated f or t emperature as shown i n the
accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to
equal the values indicated.
Page 6
MMFT3055VL
6
Motorola TMOS Power MOSFET Transistor Device Data
SAFE OPERATING AREA
TJ, STARTING JUNCTION TEMPERATURE (°C)
E
AS
, SINGLE PULSE DRAIN–TO–SOURCE
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
0.1 10 100
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
AVALANCHE ENERGY (mJ)
I
D
, DRAIN CURRENT (AMPS)
25 50 75 100 125
VGS = 15 V
SINGLE PULSE
TC = 25°C
ID = 1.5 A
1 150
Figure 13. Thermal Response
Figure 14. Diode Reverse Recovery Waveform
di/dt
t
rr
t
a
t
p
I
S
0.25 I
S
TIME
I
S
t
b
0.1
10
0.01
0
30
10
1
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
20
175
40
50
60
dc
100 ms
500 ms
1 s
10 ms
t, TIME (s)
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
0.1
0.01
0.001
D = 0.5
SINGLE PULSE
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
0.2
0.1
0.05
0.02
0.01
1.0E+02 1.0E+03
0.0001
1
Page 7
MMFT3055VL
7
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE SOT–223 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to insure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.079
2.0
0.15
3.8
0.248
6.3
0.079
2.0
0.059
1.5
0.059
1.5
0.059
1.5
0.091
2.3
0.091
2.3
mm
inches
SOT–223 POWER DISSIPATION
The power dissipation of the SOT–223 is a function of the
drain pad size. This can vary from the minimum pad size for
soldering to a pad size given for maximum power dissipation.
Power dissipation for a surface mount device is determined by
T
J(max)
, the maximum rated junction temperature of the die,
R
θJA
, the thermal resistance from the device junction to
ambient, and the operating temperature, TA. Using the values
provided on the data sheet for the SOT–223 package, PD can
be calculated as follows:
PD =
T
J(max)
– T
A
R
θJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device which in this case
is 943 milliwatts.
PD =
175°C – 25°C
159°C/W
= 943 milliwatts
The 159°C/W for the SOT–223 package assumes the use
of the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 943 milliwatts. There
are other alternatives to achieving higher power dissipation
from the SOT–223 package. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. A graph of R
θJA
versus
drain pad area is shown in Figure 17.
0.8 Watts
1.25 Watts*
1.5 Watts
R , Thermal Resistance, Junction
to Ambient ( C/W)
θ
JA
°
A, Area (square inches)
0.0 0.2 0.4 0.6 0.8 1.0
160
140
120
100
80
Figure 15. Thermal Resistance versus Drain Pad
Area for the SOT–223 Package (Typical)
Board Material = 0.0625
″
G–10/FR–4, 2 oz Copper
TA = 25°C
*Mounted on the DPAK footprint
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
SOT–223
Page 8
MMFT3055VL
8
Motorola TMOS Power MOSFET Transistor Device Data
SOLDER STENCIL GUIDELINES
Prior to placing surface mount components onto a printed
circuit board, solder paste must be applied to the pads. A
solder stencil is required to screen the optimum amount of
solder paste onto the footprint. The stencil is made of brass or
stainless steel with a typical thickness of 0.008 inches. The
stencil opening size for the SOT–223 package should be the
same as the pad size on the printed circuit board, i.e., a 1:1
registration.
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated
temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.
• Always preheat the device.
• The delta temperature between the preheat and soldering
should be 100°C or less.*
• When preheating and soldering, the temperature of the
leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10°C.
• The soldering temperature and time shall not exceed
260°C for more than 10 seconds.
• When shifting from preheating to soldering, the maximum
temperature gradient shall be 5°C or less.
• After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.
• Mechanical stress or shock should not be applied during
cooling
* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.
Page 9
MMFT3055VL
9
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control
settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. T aken together , these control settings make up
a heating “profile” for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
18 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The
line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177–189°C. When this type of
furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.
STEP 1
PREHEAT
ZONE 1
“RAMP”
STEP 2
VENT
“SOAK”
STEP 3
HEATING
ZONES 2 & 5
“RAMP”
STEP 4
HEATING
ZONES 3 & 6
“SOAK”
STEP 5
HEATING
ZONES 4 & 7
“SPIKE”
STEP 6
VENT
STEP 7
COOLING
200
°
C
150
°
C
100
°
C
50
°
C
TIME (3 TO 7 MINUTES TOTAL)
T
MAX
SOLDER IS LIQUID FOR
40 TO 80 SECONDS
(DEPENDING ON
MASS OF ASSEMBLY)
205
°
TO
219
°
C
PEAK AT
SOLDER
JOINT
DESIRED CURVE FOR LOW
MASS ASSEMBLIES
100°C
150°C
160
°
C
170°C
140
°
C
Figure 16. Typical Solder Heating Profile
DESIRED CURVE FOR HIGH
MASS ASSEMBLIES
Page 10
MMFT3055VL
10
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
CASE 318E–04
ISSUE H
H
S
F
A
B
D
G
L
4
1 2 3
0.08 (0003)
C
M
K
J
DIMAMIN MAX MIN MAX
MILLIMETERS
0.249 0.263 6.30 6.70
INCHES
B 0.130 0.145 3.30 3.70
C 0.060 0.068 1.50 1.75
D 0.024 0.035 0.60 0.89
F 0.115 0.126 2.90 3.20
G 0.087 0.094 2.20 2.40
H 0.0008 0.0040 0.020 0.100
J 0.009 0.014 0.24 0.35
K 0.060 0.078 1.50 2.00
L 0.033 0.041 0.85 1.05
M 0 10 0 10
S 0.264 0.287 6.70 7.30
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
_ _ _ _
STYLE 3:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
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MMFT3055VL/D
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