Datasheet mmdf3n04hd Datasheet

MMDF3N04HD

l

and best overall value.

s

l

Preferred Device

Power MOSFET
3 Amps, 40 Volts

N−Channel SO−8, Dual

These miniature surface mount MOSFETs feature ultra low R
and true logic level performance. They are capable of withstanding high
energy in the avalanche and c ommutation modes a nd the d rain−to−source
diode has a very low reverse recovery time. MiniMOS t devices are
designed for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc−dc converters,
and power management in portable and battery powered p roducts such a s
computers, printers, cellular and cordless phones. They can also be used
for low voltage motor controls in mass storage products such as disk
drives and tape drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.

Features

• Ultra Low R

Provides Higher Efficiency and Extends Battery Life

DS(on)

• Logic Level Gate Drive − Can Be Driven by Logic ICs

• Miniature SO−8 Surface Mount Package − Saves Board Space

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed, With Soft Recovery

• I

Specified at Elevated Temperature

DSS

• Mounting Information for SO−8 Package Provided

• Avalanche Energy Specified

• Pb−Free Package is Available

MAXIMUM RATINGS (T

Rating

Drain−to−Source Voltage V
Drain−to−Gate Voltage (RGS = 1.0 MW)
Gate−to−Source Voltage − Continuous V
Drain Current

− Continuous @ T

− Continuous @ T

− Pulsed Drain Current (Note 3)

Total Power Dissipation @ TA = 25°C (Note 1)

Linear Derating Factor (1)

Total Power Dissipation @ TA = 25°C (Note 2)

Linear Derating Factor (2)
Operating and Storage Temperature Range TJ, T
Single Pulse Drain−to−Source Avalanche

Energy − Starting T
V

= 10 Vdc, Peak IL = 9.0 Apk,

GS

L = 4.0 mH, V

= 40 Vdc)

DS

THERMAL CHARACTERISTICS

Rating Symbol Typ Max Unit

Thermal Resistance, (PCB Mount)

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously . If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. When mounted on 1″ square FR−4 or G−10 board (V

2. When mounted on minimum recommended FR−4 or G−10 board (V

3. Repetitive rating; pulse width limited by maximum junction temperature.

− Junction−to−Ambient, (Note 1)

− Junction−to−Ambient, (Note 2)

@ Steady State)

= 25°C unless otherwise noted)

J

= 25°C (Note 1)

A

= 70°C (Note 1)

A

= 25°C (VDD = 25 Vdc,

J

Symbol Value Unit

40 Vdc
40 Vdc

± 20 Vdc

3.4

3.0
40

2.0
16

1.39

11.11WmW/°C

−55 to 150 °C
162 mJ

−−62.5

= 10 V, @ 10 Secs)

GS

V

I

E

R
R

DSS
DGR

GS

I

D

I

D

DM

P

D

P

D

AS

q

JA

q

JA

stg

90

GS

DS(on)

Adc
Apk

W

mW/°C

°C/W

= 10 V ,

http://onsemi.com

(BR)DSS

40 V

G

TYP

R

DS(on)

80 mW @ TBD

N−Channel

D

S

ID MAXV

3.0 A

MARKING
DIAGRAM

8

SO−8

8

1

(Note: Microdot may be in either location)

CASE 751

STYLE 11

D3N04H = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

D3N04H

AYWWG

G

1

PIN ASSIGNMENT

Source−1

Gate−1

Source−2

Gate−2

1
2
3
4

Drain−1

8

Drain−1

7

Drain−2

6
5

Drain−2

ORDERING INFORMATION

Device Package Shipping

MMDF3N04HDR2 SO−8 2500 Tape & Ree
MMDF3N04HDR2G SO−8

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD801 1/D.

Preferred devices are recommended choices for future use

(Pb−Free)

2500 Tape & Ree

†

© Semiconductor Components Industries, LLC, 2006

February, 2006 − Rev. 4

1 Publication Order Number:

MMDF3N04HD/D

MMDF3N04HD

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted)

C

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage (Cpk ≥ 2.0) (Notes 4 & 6)

(V

= 0 Vdc, ID = 0.25 mAdc)

GS

Temperature Coefficient (Positive)

Zero Gate Voltage Drain Current

(V

= 40 Vdc, VGS = 0 Vdc)

DS

(VDS = 40 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

ON CHARACTERISTICS (Note 4)

Gate Threshold Voltage (Cpk ≥ 2.0) (Notes 4 & 6)

(V

= VGS, ID = 0.25 mAdc)

DS

Threshold Temperature Coefficient (Negative)

Static Drain−to−Source On−Resistance (Cpk ≥ 2.0) (Notes 4 & 6)

(V

= 10 Vdc, ID = 3.4 Adc)

GS

(VGS = 4.5 Vdc, ID = 1.7 Adc)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.7 Adc) (Note 4) g

DYNAMIC CHARACTERISTICS

Input Capacitance
Output Capacitance C

(VDS = 32 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Transfer Capacitance C

SWITCHING CHARACTERISTICS (Note 5)

Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t

(VDD = 20 Vdc, ID = 3.4 Adc,

= 10 Vdc, RG = 6 W) (Note 4)

V

GS

Fall Time t
Turn−On Delay Time
Rise Time t
Turn−Off Delay Time t

(VDD = 20 Vdc, ID = 1.7 Adc,

= 4.5 Vdc, RG = 6 W) (Note 4)

V

GS

Fall Time t
Gate Charge

(VDS = 40 Vdc, ID = 3.4 Adc,

V

= 10 Vdc) (Note 4)

GS

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage

(IS = 3.4 Adc, VGS = 0 Vdc) (Note 4)

(I

= 3.4 Adc, VGS = 0 Vdc, TJ = 125°C)

S

Reverse Recovery Time

(IS = 3.4 Adc, VGS = 0 Vdc,

/dt = 100 A/ms) (Note 4)

dI

S

Reverse Recovery Storage Charge Q

4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

5. Switching characteristics are independent of operating junction temperature.

6. Reflects typical values.
C

=

pk

Max limit − Typ

3 x SIGMA

Symbol Min Typ Max Unit

V

(BR)DSS

I

DSS

GSS

V

GS(th)

R

DS(on)

C

t

d(on)

d(off)

t

d(on)

d(off)

Q
Q
Q
Q

V

t
t
t

FS

iss
oss
rss

r

f

r

f

SD

rr

a

b
RR

40

−

−

−

−

4.3

0.015

0.15

−

−

2.5
10

− 0.013 500 nAdc

1.0

−

−

−

2.0

4.9

55
79

3.0

−

80

100

2.0 4.5 − Mhos

− 450 900 pF

− 130 230

− 32 96

− 9.0 18 ns

− 15 30

− 28 56

− 19 38

− 13 26 ns

− 77 144

− 17 34

− 20 40

T
1
2
3

− 13.9 28 nC

− 2.1 −

− 3.7 −

− 5.4 −

−

−

0.87

0.8

1.5

−

− 27 −

− 20 −

− 7.0 −

− 0.03 −

Vdc

mV/°C

mAdc

Vdc

mV/°C

mW

Vdc

ns

mC

http://onsemi.com

2

MMDF3N04HD

TYPICAL ELECTRICAL CHARACTERISTICS

6

VGS =

10 V

5

4

3

2

, DRAIN CURRENT (AMPS)

D

I

1

0

0 0.2 1.2 2

0.4 1.40.6 1.60.8 1.8

V

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

DS

4.5 V

4.3 V

4.1 V

1

2.7 V

3.9 V

3.7 V

3.5 V

3.3 V

3.1 V

2.9 V

Figure 1. On−Region Characteristics

0.6

ID = 3.4 A
T

0.5

0.4

0.3

0.2

0.1

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

0

DS(on)

2345 867

R

= 25°C

J

V

, GATE−TO−SOURCE VOLTAGE (VOLTS)

GS

TJ = 25°C

910

6

VDS ≥ 10 V

T

= 25°C

J

5

4

3

2

, DRAIN CURRENT (AMPS)

D

I

1

0

1.5 4.5

2 2.5 3 3.5 4

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

100°C

25°C

TJ = −55°C

Figure 2. Transfer Characteristics

0.1

TJ = 25°C

0.095

0.09

0.085

0.08

0.075

0.07

0.065

0.06

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

0.055

0.05

DS(on)

012 56

R

VGS = 4.5

10 V

34

ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

Gate−to−Source V oltage

2.0
VGS = 10 V
I

= 3.4 A

D

1.5

1.0

0.5

, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

0

−50 0 50 100 150

DS(on)

R

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation

with Temperature

100

10

, LEAKAGE (nA)

DSS

I

1257525−25

0.1

http://onsemi.com

3

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

VGS = 0 V

TJ = 125°C

100°C

1

0 5 10 15 3020 25

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

25°C

Figure 6. Drain−to−Source Leakage Current

versus Voltage

35 40

MMDF3N04HD

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, V
known as the plateau voltage, V

remains virtually constant at a level

GS

. Therefore, rise and fall

SGP

times may be approximated by the following:
t

= Q2 x RG/(VGG − V

r

tf = Q2 x RG/V

GSP

GSP

)

where

= the gate drive voltage, which varies from zero to V

V

GG

GG

RG = the gate drive resistance
and Q

and V

2

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GG

GSP

− V

)

GSP

)]

The capacitance (C

) is read from the capacitance curve at

iss

a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

1200

C, CAPACITANCE (pF)

VDS = 0 V VGS = 0 V

C

iss

900

600

C

rss

300

0

55

10 0 10 15 25

V

V

GS

VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

DS

Figure 7. Capacitance Variation

http://onsemi.com

4

T

= 25°C

J

C

iss

C

oss

C

rss

20

30

MMDF3N04HD

12

9

6

Q1

3

, GATE−TO−SOURCE VOLTAGE (VOLTS)

GS

V

0

04 8

V

Q2

Q3

QT

DS

Qg, TOTAL GATE CHARGE (nC)

V

GS

ID = 3.4 A
T

= 25°C

J

12 16

Figure 8. Gate−T o−Source and Drain−To−Source

V oltage versus Total Charge

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
to the storage of minority carrier charge, Q

, as shown in

RR

, due

rr

the typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t

and low QRR specifications to

rr

minimize these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

DS

V

1000

VDD = 20 V

= 3.4 A

I

D

= 10 V

V

GS

T

= 25°C

J

100

t

d(off)

t, TIME (ns)

10

1

1 10010

t

d(on)

RG, GATE RESISTANCE (OHMS)

t

f

t

r

40

30

20

10

0

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

high di/dts. The diode’s negative di/dt during t

is directly

a

controlled by the device clearing the stored charge.
However, the positive di/dt during t

is an uncontrollable

b

diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t

serves as a good indicator of recovery

b/ta

abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t

), have less stored charge and a softer

rr

reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.

3.5
TJ = 25°C

V

= 0 V

GS

3.0

2.5

2.0

1.5

1.0

, SOURCE CURRENT (AMPS)

0.5

S

I

0

0.5 0.55

0.6 0.65 0.7 0.75 0.8 0.85

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

http://onsemi.com

5

0.9

MMDF3N04HD

di/dt = 300 A/ms

, SOURCE CURRENT

S

I

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T

) of 25°C.

C

Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”

Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I

) nor rated voltage (V

DM

transition time (t

, tf) does not exceed 10 ms. In addition the

r

) is exceeded, and that the

DSS

total power averaged over a complete switching cycle must
not exceed (T

J(MAX)

− TC)/(R

).

JC

q

A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For

Standard Cell Density

t

rr

High Cell Density

t

rr

t

b

t

a

t, TIME

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.

Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I

), the energy rating is specified at rated

DM

), in accordance with industry

D

custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I

can safely be

D

assumed to equal the values indicated.

100

VGS = 20 V
SINGLE PULSE

T

= 25°C

C

10

10 ms

1

, DRAIN CURRENT (AMPS)

0.1

D

I

0.01

0.1

R

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

dc

LIMIT

1

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

160

ID = 9 A

1 ms

120

80

40

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN-TO-SOURCE

AS

E

10

100

0

25 50 75 100 125

TJ, STARTING JUNCTION TEMPERATURE (°C)

150

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

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6

MMDF3N04HD

TYPICAL ELECTRICAL CHARACTERISTICS

1

D = 0.5

0.1

0.01

THERMAL RESISTANCE

Rthja(t), EFFECTIVE TRANSIENT

0.001

1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

Chip

0.0106 W 0.0431 W 0.1643 W 0.3507 W 0.4302 W

Junction

t, TIME (s)

Figure 14. Thermal Response

177.14 F2.9468 F0.5064 F0.1406 F0.0253 F

Ambient

1.0E+02 1.0E+03

di/dt

I

S

t

rr

t

t

a

b

TIME

t

p

0.25 I

S

I

S

Figure 15. Diode Reverse Recovery Waveform

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7

−Y−

−Z−

MMDF3N04HD

PACKAGE DIMENSIONS

SOIC−8

CASE 751−07

ISSUE AG

−X−
A

58

B

1

S

0.25 (0.010)

4

M

M

Y

K

G

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

N

X 45

_

M

J

SOLDERING FOOTPRINT*

1.52

0.060

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8

____

N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

INCHES

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC). Company.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MMDF3N04HD/D

8