Datasheet mmdf2p02e Datasheet

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Page 1

MMDF2P02E

l l

Brochure, BRD801 1/D.

Power MOSFET 2 Amps, 25 Volts

P−Channel SO−8, Dual

These miniature surface mount MOSFET s feature ultra low R

DS(on)

and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain−to−source diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc−dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.

Features

• Ultra Low R

Provides Higher Efficiency and Extends Battery Life

DS(on)

• Logic Level Gate Drive − Can Be Driven by Logic ICs

• Miniature SO−8 Surface Mount Package − Saves Board Space

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed, with Soft Recovery

• I

Specified at Elevated Temperatures

DSS

• Avalanche Energy Specified

• Mounting Information for SO−8 Package Provided

• Pb−Free Package is Available

MAXIMUM RATINGS (T

Rating

Drain−to−Source Voltage V Gate−to−Source Voltage − Continuous V Drain Current − Continuous @ TA = 25°C

Drain Current − Continuous @ T Drain Current − Single Pulse (t

Total Power Dissipation @ T

2) Derate above 25°C

Operating and Storage Temperature Range TJ, T Single Pulse Drain−to−Source Avalanche

Energy − Starting T (VDD = 20 Vdc, VGS = 10 Vdc, Peak

= 7.0 Apk, L = 10 mH, RG = 25 W)

Thermal Resistance, Junction−to−Ambient (Note 2)

Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 sec.

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.

1. Negative sign for P−Channel device omitted for clarity.

2. Mounted on 2 ″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10 sec. max.

April, 2006 − Rev. 8

= 25°C unless otherwise noted) (Note 1)

Symbol Value Unit

DSS

= 25°C

= 100°C

≤ 10 ms)

= 25°C (Note

−55 to 150 °C

stg

25 Vdc

± 20 Vdc

2.5

1.7 13

2.0 16

245

62.5 °C/W

260 °C

Adc Apk

mW/°C

1 Publication Order Number:

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2 AMPERES, 25 VOLTS

DS(on)

F2P02 = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb−Free Package

(Note: Microdot may be in either location)

PIN ASSIGNMENT

Source−1

Gate−1

Source−2

Gate−2

ORDERING INFORMATION

Device Package Shipping

MMDF2P02ER2 SO−8 2500 Tape & Ree MMDF2P02ER2G SO−8

†For information on tape and reel specifications,

including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification

= 250 mW

P−Channel

SO−8, Dual

CASE 751

STYLE 11

1 2 3 4

Top View

(Pb−Free)

MARKING DIAGRAM

F2PO2

AYWWG

Drain−1

Drain−2

6 5

Drain−2

2500 Tape & Ree

MMDF2P02E/D

†

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MMDF2P02E

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted) (Note 3)

Characteristic

OFF CHARACTERISTICS

Drain−to−Source Breakdown Voltage

= 0 Vdc, ID = 250 mAdc)

Temperature Coefficient (Positive) Zero Gate Voltage Drain Current

= 20 Vdc, VGS = 0 Vdc)

= 20 Vdc, VGS = 0 Vdc, TJ = 125°C)

Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

ON CHARACTERISTICS (Note 4)

Gate Threshold Voltage

= VGS, ID = 250 mAdc)

Temperature Coefficient (Negative) Static Drain−to−Source On−Resistance

= 10 Vdc, ID = 2.0 Adc)

(VGS = 4.5 Vdc, ID = 1.0 Adc)

Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) g

DYNAMIC CHARACTERISTICS

Input Capacitance Output Capacitance C

(VDS = 16 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Transfer Capacitance C

SWITCHING CHARACTERISTICS (Note 5)

Turn−On Delay Time Rise Time t Turn−Off Delay Time t

(VDD = 10 Vdc, ID = 2.0 Adc,

= 5.0 Vdc, RG = 6.0 W)

Fall Time t Turn−On Delay Time Rise Time t Turn−Off Delay Time t

(VDD = 10 Vdc, ID = 2.0 Adc,

= 10 Vdc, RG = 6.0 W)

Fall Time t Gate Charge

(VDS = 16 Vdc, ID = 2.0 Adc,

= 10 Vdc)

SOURCE−DRAIN DIODE CHARACTERISTICS

Forward On−Voltage (Note 4) (IS = 2.0 Adc, VGS = 0 Vdc) V Reverse Recovery Time

See Figure 11

(IS = 2.0 Adc, VGS = 0 Vdc,

/dt = 100 A/ms)

Reverse Recovery Storage Charge Q

3. Negative sign for P−Channel device omitted for clarity.

4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

5. Switching characteristics are independent of operating junction temperature.

Symbol Min Typ Max Unit

(BR)DSS

DSS

GSS

GS(th)

DS(on)

d(on)

d(off)

d(on)

d(off)

Q Q Q

t t t

iss

oss

rss

rr a b

−

2.2

−

1.0 10

− − 100 nAdc

1.0

−

2.0

3.8

0.19

0.3

3.0

−

0.25

0.4

1.0 2.8 − Mhos

− 340 475 pF

− 220 300

− 75 150

− 20 40

− 40 80

− 53 106

− 41 82

− 13 26

− 29 58

− 30 60

T 1 2 3

− 28 56

− 10 15 nC

− 1.0 −

− 3.5 −

− 3.0 −

− 1.5 2.0 Vdc

− 32 64

− 19 −

− 12 −

− 0.035 −

Vdc

mV/°C

mAdc

Vdc

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MMDF2P02E

TYPICAL ELECTRICAL CHARACTERISTICS

, DRAIN CURRENT (AMPS)

VGS = 10

0 0.4 0.8 1.2 1.6 2

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

7 V

5 V

4.7 V

TJ = 25°C

4.5 V

4.3 V

4.1 V

3.9 V

3.7 V

3.5 V

3.3 V

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

0.6 ID = 1 A T

= 25°C

0.5

0.4

0.3

0.2

VDS ≥ 10 V

, DRAIN CURRENT (AMPS)

2.5 3 3.5 4 4.5

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

0.6 TJ = 25°C

0.5

0.4

0.3

VGS = 4.5

100°C

25°C

TJ = −55°C

0.1

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

DS(on)

345 10

, GATE−TO−SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus

Gate−to−Source V oltage

2.0

1.5

1.0

0.5

, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

DS(on)

VGS = 10 V I

= 2 A

−50 0 50 100 150

, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

1257525−25

Figure 5. On−Resistance Variation with

Temperature

0.2

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

0.1

DS(on)

0 0.5 1 1.5 2

10 V

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

100

VGS = 0 V

TJ = 125°C

, LEAKAGE (nA)

DSS

04812 20

100°C

Figure 6. Drain−to−Source Leakage Current

versus Voltage

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MMDF2P02E

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator.

The published capacitance data is difficult to use for calculating rise and fall because drain−gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that t = Q/I

G(AV)

During the rise and fall time interval when switching a resistive load, V known as the plateau voltage, V

remains virtually constant at a level

. Therefore, rise and fall

SGP

times may be approximated by the following: t

= Q2 x RG/(VGG − V

tf = Q2 x RG/V

GSP

)

where

= the gate drive voltage, which varies from zero to V

RG = the gate drive resistance and Q

and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are:

d(on)

d(off)

= RG C

In [VGG/(V

iss

In (VGG/V

iss

The capacitance (C

) is read from the capacitance curve at

iss

GSP

− V

)

GSP

)]

a voltage corresponding to the off−state condition when calculating t on−state when calculating t

and is read at a voltage corresponding to the

d(on)

d(off)

At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.

1000

VDS = 0 V VGS = 0 V

iss

800

600

400

rss

C, CAPACITANCE (pF)

200

10 0 10 15 25

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

iss

oss

rss

Figure 7. Capacitance Variation

= 25°C

, GATE−TO−SOURCE VOLTAGE (VOLTS)

02 4 6 8

Qg, TOTAL GATE CHARGE (nC)

ID = 2 A T

= 25°C

10 12

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 8. Gate−to−Source and

Drain−to−Source V oltage versus Total Charge

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MMDF2P02E

100

VDD = 10 V I

= 2 A

= 10 V

= 25°C

t, TIME (ns)

1 10010

d(off)

d(on)

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time Variation

versus Gate Resistance

di/dt = 300 A/ms

TJ = 25°C VGS = 0 V

1.6

1.2

0.8

0.4

, SOURCE CURRENT (AMPS)

0.6 0.8 1.2 1.4 1.61 VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage

Standard Cell Density

High Cell Density

versus Current

, SOURCE CURRENT

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define the maximum simultaneous drain−to−source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (T

) of 25°C.

Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, “Transient Thermal Resistance − General Data and Its Use.”

Switching between the off−state and the on−state may traverse any load line provided neither rated peak current (I

) nor rated voltage (V

transition time (t

, tf) does not exceed 10 ms. In addition the

) is exceeded, and that the

DSS

total power averaged over a complete switching cycle must not exceed (T

J(MAX)

− TC)/(R

A power MOSFET designated E−FET can be safely used in switching circuits with unclamped inductive loads. For

t, TIME

reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non−linearly with an increase of peak current in avalanche and peak junction temperature.

Although many E−FETs can withstand the stress of drain−to−source avalanche at currents up to rated pulsed current (I continuous current (I

), the energy rating is specified at rated

), in accordance with industry

custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous I

can safely be

assumed to equal the values indicated.

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Page 6

MMDF2P02E

100

VGS = 20 V SINGLE PULSE

= 25°C

Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with one die operating, 10s max.

100 ms

10 ms

, DRAIN CURRENT (AMPS)

0.1

DS(on)

LIMIT THERMAL LIMIT PACKAGE LIMIT

0.01

0.1

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

TYPICAL ELECTRICAL CHARACTERISTICS

280

I pk = 7 A

240

10 ms

200

160

120

AVALANCHE ENERGY (mJ)

, SINGLE PULSE DRAIN-TO-SOURCE

100

25 50 75 100 125

150

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

D = 0.5

0.2

0.1

THERMAL RESISTANCE

0.01

Rthja(t), EFFECTIVE TRANSIENT

0.1

0.05

0.02

0.01

Normalized to qja at 10s.

0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W

Chip

SINGLE PULSE

0.001

1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01 t, TIME (s)

Figure 14. Thermal Response

di/dt

0.25 I

TIME

107.55 F1.7891 F0.3074 F0.0854 F0.0154 F

Ambient

1.0E+02 1.0E+03

Figure 15. Diode Reverse Recovery Waveform

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Page 7

−Y−

−Z−

MMDF2P02E

PACKAGE DIMENSIONS

SOIC−8 NB

CASE 751−07

ISSUE AH

NOTES:

−X− A

0.25 (0.010)

SEATING PLANE

0.10 (0.004)

0.25 (0.010) Z

SXS

X 45

SOLDERING FOOTPRINT*

1.52

0.060

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.053 0.069 D 0.33 0.51 0.013 0.020 G 1.27 BSC 0.050 BSC H 0.10 0.25 0.004 0.010 J 0.19 0.25 0.007 0.010 K 0.40 1.27 0.016 0.050 M 0 8 0 8

____

N 0.25 0.50 0.010 0.020 S 5.80 6.20 0.228 0.244

STYLE 11:

PIN 1. SOURCE 1

2. GATE 1

3. SOURCE 2

4. GATE 2

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

8. DRAIN 1

INCHES

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

inches

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.

E−FET and MiniMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MMDF2P02E/D