Datasheet mmdf2c03hd Datasheet

MMDF2C03HD

l

and best overall value.

l

Preferred Device

Power MOSFET
2 Amps, 30 Volts

Complementary SO−8, Dual

These miniature surface mount MOSFET s feature ultra low R
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain-to-source diode has a very low reverse recovery time.
MiniMOSt devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dc-dc converters, and power management in portable
and battery powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor controls
in mass storage products such as disk drives and tape drives. The
avalanche energy is specified to eliminate the guesswork in designs
where inductive loads are switched and offer additional safety margin
against unexpected voltage transients.

DS(on)

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2 AMPERES, 30 VOLTS

R

R

DS(on)

DS(on)

= 70 mW (N-Channel)

= 200 mW (P-Channel)

N−Channel

D

P−Channel

D

Features

• Ultra Low R

Provides Higher Efficiency and Extends Battery Life

DS(on)

• Logic Level Gate Drive − Can Be Driven by Logic ICs

• Miniature SO-8 Surface Mount Package − Saves Board Space

• Diode Is Characterized for Use In Bridge Circuits

• Diode Exhibits High Speed, With Soft Recovery

• I

Specified at Elevated Temperature

DSS

• Avalanche Energy Specified

• Mounting Information for SO-8 Package Provided

• Pb−Free Package is Available

MAXIMUM RATINGS (T

Rating

Drain−to−Source Voltage V
Gate−to−Source Voltage V
Drain Current − Continuous N−Channel

Drain Current − Pulsed N−Channel

Operating and Storage Temperature Range TJ, T
Total Power Dissipation @ TA= 25°C (Note 2) P
Thermal Resistance, Junction−to−Ambient

(Note 2)
Single Pulse Drain−to−Source Avalanche

Energy − Starting T
(VDD = 30 V, VGS = 5.0 V, Peak IL = 9.0 Apk,

L = 8.0 mH, R

(VDD = 30 V, VGS = 5.0 V, Peak IL = 6.0 Apk,

L = 18 mH, R

Max Lead Temperature for Soldering, 0.0625″
from case. Time in Solder Bath is 10 seconds

Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously . If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.

1. Negative signs for P−Channel device omitted for clarity.

2. Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with

one die operating, 10 sec. max.

= 25 W) N−Channel

G

= 25 W) P−Channel

G

= 25°C unless otherwise noted) (Note 1)

J

Symbol Value Unit

= 25°C

J

P−Channel
P−Channel

I

R

E

DSS

GS

I

D

DM

−55 to 150 °C

stg

D

q

JA

AS

T

L

30 Vdc

± 20 Vdc

4.1

3.0
21
15

2.0 W

62.5 °C/W

324
324

260 °C

A

mJ

G

S

G

S

MARKING
DIAGRAM

8

SO−8

8

1

(Note: Microdot may be in either location)

CASE 751
STYLE 14

D2C03 = Device Code
A = Assembly Location
Y = Year
WW = Work Week
G = Pb−Free Package

D2C03

AYWWG

G

1

PIN ASSIGNMENT

N−Source

N−Gate

P−Source

P−Gate

1
2
3
4

N−Drain

8

N−Drain

7

P−Drain

6
5

P−Drain

ORDERING INFORMATION

Device Package Shipping

MMDF2C03HDR2 SO−8 2500 Tape & Ree
MMDF2C03HDR2G SO−8

†For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.

Preferred devices are recommended choices for future use

(Pb−Free)

2500 Tape & Ree

†

© Semiconductor Components Industries, LLC, 2006

February, 2006 − Rev. 7

1 Publication Order Number:

MMDF2C03HD/D

MMDF2C03HD

ELECTRICAL CHARACTERISTICS (T

= 25°C unless otherwise noted) (Note 3)

A

Characteristic Symbol Polarity Min Typ Max Unit

OFF CHARACTERISTICS

Drain−Source Breakdown Voltage

= 0 Vdc, ID = 250 mAdc)

(V

GS

Zero Gate Voltage Drain Current

(V

= 30 Vdc, VGS = 0 Vdc)

DS

Gate−Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) I

V

(BR)DSS

I

DSS

GSS

ON CHARACTERISTICS (Note 4)

Gate Threshold Voltage

= VGS, ID = 250 mAdc)

(V

DS

Drain−to−Source On−Resistance

(V

= 10 Vdc, ID = 3.0 Adc)

GS

(VGS = 10 Vdc, ID = 2.0 Adc)

Drain−to−Source On−Resistance

(V

= 4.5 Vdc, ID = 1.5 Adc)

GS

(V

= 4.5 Vdc, ID = 1.0 Adc)

GS

Forward Transconductance

(V

= 3.0 Vdc, ID = 1.5 Adc)

DS

(VDS = 3.0 Vdc, ID = 1.0 Adc)

V

GS(th)

R

DS(on)

R

DS(on)

g

DYNAMIC CHARACTERISTICS

Input Capacitance

Output Capacitance

(VDS = 24 Vdc, VGS = 0 Vdc,

C

C

f = 1.0 MHz)

Transfer Capacitance

C

SWITCHING CHARACTERISTICS (Note 5)

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

(VDD = 15 Vdc, ID = 3.0 Adc,

= 4.5 Vdc, RG = 9.1 W)

V

GS

(VDD = 15 Vdc, ID = 2.0 Adc,

= 4.5 Vdc, RG = 6.0 W)

V

GS

t

d(on)

d(off)

Fall Time t

Turn−On Delay Time

Rise Time t

Turn−Off Delay Time t

(VDD = 15 Vdc, ID = 3.0 Adc,

= 10 Vdc, RG = 9.1 W)

V

GS

(VDD = 15 Vdc, ID = 2.0 Adc,

= 10 Vdc, RG = 6.0 W)

V

GS

t

d(on)

d(off)

Fall Time t

Total Gate Charge

Gate−Source Charge Q

Gate−Drain Charge

(VDS = 10 Vdc, ID = 3.0 Adc,

V

= 10 Vdc)

GS

(VDS = 24 Vdc, ID = 2.0 Adc,

Q

Q

VGS = 10 Vdc)

Q

3. Negative signs for P−Channel device omitted for clarity.

4. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

5. Switching characteristics are independent of operating junction temperature.

FS

iss

oss

rss

r

f

r

f

− 30 − −

Vdc

(N)
(P)

−

−

−

−

1.0

1.0

mAdc

− − − 100 nAdc

(N)
(P)

1.0

1.0

1.7

1.5

3.0

2.0

Vdc

W

(N)
(P)

−

−

0.06

0.17

0.070

0.200

W

(N)
(P)

−

0.065

−

0.225

0.075

0.300
mhos

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

T

1

2

3

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

2.0

2.0

3.6

3.4

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

−

450
397

160
189

35
64

12
16

65
18

16
63

19

194

8.0

9.0
15

10
30

81
23

192

11.5

14.2

1.5

1.1

3.5

4.5

2.8

3.5

−

−

630
550

225
250

70

126

24
32

130

36
32

126

38

390

16
18

30
20

60

162

46

384

16
19

−

−

−

−

−

−

pF

ns

nC

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2

MMDF2C03HD

ELECTRICAL CHARACTERISTICS − continued (T

= 25°C unless otherwise noted) (Note 6)

A

Characteristic Symbol Polarity Min Typ Max Unit

SOURCE−DRAIN DIODE CHARACTERISTICS (TC = 25°C)

Forward Voltage (Note 7) (IS = 3.0 Adc, VGS = 0 Vdc)

(I

= 2.0 Adc, VGS = 0 Vdc)

S

Reverse Recovery Time

(IF = IS, dIS/dt = 100 A/ms)

Reverse Recovery Storage
Charge

6. Negative signs for P−Channel device omitted for clarity.

7. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.

TYPICAL ELECTRICAL CHARACTERISTICS

N−Channel P−Channel

6

VGS = 10 V

4.5 V

5

4.3 V

4.1 V

4

3.9 V

3.7 V

3.5 V
TJ = 25°C

3.3 V

V

SD

t

rr

t

a

t

b

Q

RR

4

3

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

(N)
(P)

VGS = 10 V

3.9 V

4.5 V

−

−

−

−

−

−

−

−

−

−

0.82

1.82
24

42
17

16

7.0
26

0.025

0.043

3.7 V

3.5 V

1.2

2.0

−

−

−

−

−

−

−

−

Vdc

ns

mC

TJ = 25°C

3.3 V

3

2

, DRAIN CURRENT (AMPS)

D

I

1

3.1 V

2.9 V

2.7 V

2.5 V

0

0.2 0.6

0 0.4 0.8 1.2 1.6 2

V

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

DS

Figure 1. On−Region Characteristics

6

VDS ≥ 10 V

5

4

TJ = 100°C

3

2

, DRAIN CURRENT (AMPS)

D

I

1

0

2 2.5 3 3.5 4

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

25°C

−55°C

3.1 V

2.9 V

2.7 V

, DRAIN CURRENT (AMPS)

D

I

2

1

2.5 V

1.81.41

0

0 0.2 0.4 0.6 0.8 2

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

1 1.2

1.4 1.6 1.8

Figure 1. On−Region Characteristics

4

VDS ≥ 10 V

3

2

, DRAIN CURRENT (AMPS)

D

I

0

1.5 1.7 1.9 2.1 2.3 3.7

VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

TJ = 100°C

25°C

−55°C

2.512.7 2.9 3.1 3.3 3.5

Figure 2. Transfer Characteristics

Figure 2. Transfer Characteristics

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3

MMDF2C03HD

TYPICAL ELECTRICAL CHARACTERISTICS

0.6

ID = 1.5 A
T

0.5

0.4

0.3

0.2

0.1

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

0

DS(on)

2345 867

R

= 25°C

J

, GATE−TO−SOURCE VOLTAGE (VOLTS)

V

GS

Figure 3. On−Resistance versus

Gate−To−Source Voltage

0.08

TJ = 25°C

0.07

VGS = 4.5

N−Channel P−Channel

910

0.6

0.5

0.4

0.3

0.2

0.1

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

DS(on)

R

ID = 1 A

T

= 25°C

J

0

01 2 3 4 10

V

, GATE−TO−SOURCE VOLTAGE (VOLTS)

GS

56789

Figure 3. On−Resistance versus

Gate−To−Source Voltage

0.30

0.25

0.20

TJ = 25°C

VGS = 4.5 V

0.06

10 V

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

0.05

DS(on)

0 0.5 1 2.5 3

R

I

, DRAIN CURRENT (AMPS)

D

1.5 2

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

2.0

1.5

1.0

0.5

, DRAIN−TO−SOURCE RESISTANCE (NORMALIZED)

DS(on)

R

VGS = 10 V
I

= 1.5 A

D

0

−50 0 50 100 150

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

10 V

0.15

, DRAIN−TO−SOURCE RESISTANCE (OHMS)

0.10

DS(on)

0 0.5 1 1.5 2 4

R

I

, DRAIN CURRENT (AMPS)

D

2.5 3 3.5

Figure 4. On−Resistance versus Drain Current

and Gate Voltage

1.6
VGS = 10 V

I

= 2 A

D

1.4

1.2

1.0

(NORMALIZED)

, DRAIN−TO−SOURCE RESISTANCE

0.8

DS(on)

R

1257525−25

0.6

−25 25 75 125

−50 0 50 100 150

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. On−Resistance Variation with

Temperature

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MMDF2C03HD

TYPICAL ELECTRICAL CHARACTERISTICS

N−Channel P−Channel

100

VGS = 0 V

TJ = 125°C

10

, LEAKAGE (nA)

DSS

I

1

0 5 10 15 3020 25

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

Figure 6. Drain−T o−Source Leakage

Current versus Voltage

100°C

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.

The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I

) can be made from a

G(AV)

rudimentary analysis of the drive circuit so that
t = Q/I

G(AV)

During the rise and fall time interval when switching a
resistive load, V
known as the plateau voltage, V

remains virtually constant at a level

GS

. Therefore, rise and fall

SGP

times may be approximated by the following:
t

= Q2 x RG/(VGG − V

r

t

= Q2 x RG/V

f

GSP

GSP

)

where
V

= the gate drive voltage, which varies from zero to V

GG

GG

RG = the gate drive resistance
and Q2 and V

are read from the gate charge curve.

GSP

During the turn−on and turn−off delay times, gate current
is not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

t

d(on)

t

d(off)

= RG C

= RG C

In [VGG/(V

iss

In (VGG/V

iss

GG

GSP

− V

)

GSP

)]

1000

100

, LEAKAGE (nA)

DSS

I

The capacitance (C

VGS = 0 V

TJ = 125°C

100°C

10

0102030

51525

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

Figure 6. Drain−T o−Source Leakage

Current versus Voltage

) is read from the capacitance curve

iss

at a voltage corresponding to the off−state condition when
calculating t
on−state when calculating t

and is read at a voltage corresponding to the

d(on)

.

d(off)

At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.

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5

1200

1000

VDS = 0 V

C

iss

MMDF2C03HD

N−Channel P−Channel

VGS = 0 V

T

= 25°C

J

1200

1000

VDS = 0 V V

C

iss

= 0 V

GS

TJ = 25°C

800

600

C

rss

400

C, CAPACITANCE (pF)

200

0

10 0 10 15 25

55

V

V

GS

DS

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

12

QT

9

6

Q1

V

DS

Q2

V

GS

3

Q3

0

02 4 68

V

, GATE−TO−SOURCE VOLTAGE (VOLTS)

GS

ID = 3 A
T

Qg, TOTAL GATE CHARGE (nC)

C

iss

C

oss

C

rss

20

= 25°C

J

10 12

800

C

rss

600

C

iss

C

oss

rss

25

30

400

C, CAPACITANCE (pF)

200

0

10 0 10 15 20 30

55

V

GS

C

V

DS

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance VariationFigure 7. Capacitance Variation

24

18

12

6

0

DS

V

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

, GATE−TO−SOURCE VOLTAGE (VOLTS)

GS

V

12

24

QT

10

V

GS

8

6

Q1

V

DS

ID = 2 A
T

= 25°C

Q2

J

4

2

20

16

12

8

4

Q3

0

0

24 6 8 16

10 12 14

0

Qg, TOTAL GATE CHARGE (nC)

Figure 8. Gate−T o−Source and Drain−To−Source

V oltage versus Total Charge

1000

VDD = 15 V
I

= 3 A

D

= 10 V

V

GS

T

= 25°C

J

100

t

d(off)

t

r

t

t, TIME (ns)

10

1

1 10010

t

d(on)

f

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

1000

100

t, TIME (ns)

10

1

1 10 100

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6

Figure 8. Gate−T o−Source and Drain−To−Source

V oltage versus Total Charge

VDD = 15 V
I

= 2 A

D

= 10 V

V

GS

T

= 25°C

J

t

d(off)

t

f

t

r

t

d(on)

RG, GATE RESISTANCE (OHMS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

MMDF2C03HD

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
to the storage of minority carrier charge, Q

, as shown in

RR

, due

rr

the typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t

and low QRR specifications to

rr

minimize these losses.

The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by

N−Channel P−Channel

3.0

TJ = 25°C
V

2.5

= 0 V

GS

high di/dts. The diode’s negative di/dt during t

is directly

a

controlled by the device clearing the stored charge.
However, the positive di/dt during t

is an uncontrollable

b

diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t

serves as a good indicator of recovery

b/ta

abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.

Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t

), have less stored charge and a softer

rr

reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.

2

TJ = 25°C
V

= 0 V

GS

1.6

2.0

1.5

1.0

0.5

, SOURCE CURRENT (AMPS)

S

I

0

0.5 0.55

0.6 0.65 0.7 0.75 0.8 0.85

VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

1.2

0.8

0.4

, SOURCE CURRENT (AMPS)

S

I

0

0.5 0.7 0.9 1.1 1.3 1.9

, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

V

SD

1.5 1.7

Figure 10. Diode Forward Voltage versus Current

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7

MMDF2C03HD

N−Channel P−Channel

di/dt = 300 A/ms

, SOURCE CURRENT

S

I

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T

) of 25°C.

C

Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”

Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I

) nor rated voltage (V

DM

transition time (t

, tf) does not exceed 10 ms. In addition the

r

) is exceeded, and that the

DSS

total power averaged over a complete switching cycle must
not exceed (T

J(MAX)

− TC)/(R

).

JC

q

A power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For

Standard Cell Density

t

rr

High Cell Density

t

rr

t

b

t

a

t, TIME

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.

Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I

), the energy rating is specified at rated

DM

), in accordance with industry

D

custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I

can safely be

D

assumed to equal the values indicated.

100

VGS = 20 V
SINGLE PULSE

T

= 25°C

C

10

1

R

LIMIT

DS(on)

, DRAIN CURRENT (AMPS)

0.1

D

I

Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.

0.01

0.1

THERMAL LIMIT
PACKAGE LIMIT

1

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

V

DS

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

100

VGS = 20 V

0.1

D

0.01

SINGLE PULSE
T

10

1

0.1

= 25°C

C

V

10 ms

100 ms

1 ms

10 ms

dc

, DRAIN CURRENT (AMPS)
I

10

100

Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.

100 ms

1 ms

10 ms

dc

R

LIMIT

DS(on)

THERMAL LIMIT
PACKAGE LIMIT

1

, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

DS

10

100

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

http://onsemi.com

8

MMDF2C03HD

N−Channel P−Channel

350

300

250

200

150

100

AVALANCHE ENERGY (mJ)

50

, SINGLE PULSE DRAIN-TO-SOURCE

AS

E

0

25 50 75 100 125

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

TYPICAL ELECTRICAL CHARACTERISTICS

10

ID = 9 A

150

350

300

250

200

150

100

AVALANCHE ENERGY (mJ)

50

, SINGLE PULSE DRAIN−TO−SOURCE

AS

E

0

25 50 75 100 125

TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

ID = 6 A

150

1

0.1

THERMAL RESISTANCE

0.01

Rthja(t), EFFECTIVE TRANSIENT

0.001

1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01

D = 0.5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

Normalized to qja at 10s.

0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W

Chip

t, TIME (s)

Figure 14. Thermal Response

di/dt

I

S

t

rr

t

t

a

b

TIME

107.55 F1.7891 F0.3074 F0.0854 F0.0154 F

Ambient

1.0E+02 1.0E+03

t

p

0.25 I

S

I

S

Figure 15. Diode Reverse Recovery Waveform

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9

−Y−

−Z−

MMDF2C03HD

PACKAGE DIMENSIONS

SOIC−8

CASE 751−07

ISSUE AG

−X−
A

58

B

1

S

0.25 (0.010)

4

M

M

Y

K

G

N

C

SEATING
PLANE

0.10 (0.004)

H

D

0.25 (0.010) Z

M

Y

SXS

X 45

_

M

J

SOLDERING FOOTPRINT*

NOTES:

1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

MILLIMETERS

DIMAMIN MAX MIN MAX

4.80 5.00 0.189 0.197

B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010

J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8

____

N 0.25 0.50 0.010 0.020

S 5.80 6.20 0.228 0.244

STYLE 14:

PIN 1. N−SOURCE

2. N−GATE

3. P−SOURCE

4. P−GATE

5. P−DRAIN

6. P−DRAIN

7. N−DRAIN

8. N−DRAIN

INCHES

1.52

0.060

7.0

0.275

0.6

0.024

4.0

0.155

1.270

0.050

SCALE 6:1

ǒ

inches

mm

Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

MiniMOS is a trademark of Semiconductor Components Industries, LLC (SCILLC).

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

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MMDF2C03HD/D