Datasheet MM74HCT373N, MM74HCT373MTC, MM74HCT373WMX, MM74HCT373SJ, MM74HCT373SJX Datasheet (Fairchild Semiconductor)
...Page 1
February 1984
Revised February 1999
MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
© 1999 Fairchild Semiconductor Corporation DS005367.prf www.fairchildsemi.com
MM74HCT373 • MM74HCT374
3-STATE Octal D-Type Latch •
3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT373 octal D-type latches and
MM74HCT374 Octal D-type flip flops advanced silicongate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply
range, but are LS-TTL input and output characteristic &
pin-out compatible. The 3-STATE outputs are capable of
driving 15 LS-TTL loads. All inputs are protected from damage due to static dischar ge by internal diode s to V
CC
and
ground.
When the MM74HCT373 LATCH ENABLE input is HIGH,
the Q outputs will follow the D inputs. When the LATCH
ENABLE goes LOW, data at the D inputs will be retained at
the outputs until LATCH ENABLE returns HIGH again.
When a high logic level is applied to t he OUTPUT CONTROL input, all outputs go to a high impedance state,
regardless of what signals are present at the other inputs
and the state of the storage elements.
The MM74HCT374 are positive edge triggered flip-flo ps.
Data at the D inputs, meeting the setup and hold time
requirements, are transferred to the Q outputs on po sitive
going transitions of the CLOC K (CK) input. When a high
logic level is applied to the OUTPUT CONTROL (OC)
input, all outputs go t o a high impe dance state, re gardless
of what signals are present at the other inputs and the state
of the storage elements.
MM74HCT devices are intended to interface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug in replacements for LS-TTL
devices and can be used to redu ce power consumption in
existing designs.
Features
■ TTL input characteristic compatible
■ Typical propagation delay: 20 ns
■ Low input current: 1 µA maximum
■ Low quiescent current: 80 µA maximum
■ Compatible with bus-oriented systems
■ Output drive capability: 15 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.
Order Number Package Number Package Descriptions
MM74HCT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HCT373WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT373SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT373MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HCT373 • MM74HCT374
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT373
Top View
MM74HCT374
Truth Tables
MM74HCT373
H = HIGH Level
L = LOW Lev el
Q0 = Level of output before steady -s ta t e input conditions were est ablished.
Z = High Impedance
MM74HCT374
H = HIGH Level
L = LOW Level
X = Don’t Care
↑ = Transition from LOW-to-HIGH
Z = High Impedance State
Q
0
= The level of the outpu t before steady state input conditions were
established.
Output LE Data 373
Control Output
LHHH
LHLL
LLXQ
0
HXXZ
Output Clock Data Output
Control (374)
L ↑ HH
L ↑ LL
LLXQ
0
HXXZ
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MM74HCT373 • MM74HCT374
Logic Diagrams
MM74HCT373
MM74HCT374
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MM74HCT373 • MM74HCT374
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperat ure derat ing — plas tic “N” p ackage: −
12 mW/°C from 65 °C to 85°C.
DC Electrical Characteristics
V
CC
= 5V ± 10% (unless otherwise specified)
Note 4: Measured per pin. All others tied to VCCor ground.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to V
CC
+1.5V
DC Output Voltage (V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±35 mA
DC V
CC
or GND Current, per pin (ICC) ±70 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage ( V
CC
)4.55.5V
DC Input or Output Voltage 0 V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) 500 ns
Symbol Parameter Conditions
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0 2.0 2.0 V
Input Voltage
V
IL
Maximum LOW Level 0.8 0.8 0.8 V
Input Voltage
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| = 20 µAV
CCVCC
− 0.1 VCC− 0.1 VCC− 0.1 V
|I
OUT
| = 6.0 mA, VCC = 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| = 7.2 mA, V
CC
= 5.5V 5.7 4.98 4.84 4.7 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Voltage |I
OUT
| = 20 µA 0 0.1 0.1 0.1 V
|I
OUT
| = 6.0 mA, V
CC
= 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| = 7.2 mA, V
CC
= 5.5V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND, ±0.1 ±1.0 ±1.0 µA
Current VIH or V
IL
I
OZ
Maximum 3-STATE V
OUT
= VCC or GND ±0.5 ±5.0 ±10 µA
Output Leakage Enable = VIH or VIL
Current
I
CC
Maximum Quiescent V
IN
= VCC or GND 8.0 80 160 µA
Supply Current I
OUT
= 0 µA
V
IN
= 2.4V or 0.5V (Note 4) 1.0 1.3 1.5 mA
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MM74HCT373 • MM74HCT374
AC Electrical Characteristics
MM74HCT373: V
CC
= 5.0V, tr = tf = 6 ns T
A
= 25°C (unless otherwise specified)
AC Electrical Characteristics
MM74HCT373: V
CC
= 5.0V ± 10%, tr = t
f
= 6 ns (unless otherwise specified)
Note 5: CPD determines th e no load dynamic power con s um ption, PD = CPD VCC2 f + ICC VCC, and the no load dynam ic c urrent consumption ,
I
S
= CPD VCCf + ICC.
Symbol Parameter Conditions Typ
Guaranteed
Units
Limit
t
PHL
, t
PLH
Maximum Propagation Delay CL = 45 pF 18 25 ns
Data to Output
t
PHL
, t
PLH
Maximum Propagation Delay CL = 45 pF 21 30 ns
Latch Enable to Output
t
PZH
, t
PZL
Maximum Enable Propagation Delay CL = 45 pF 20 28 ns
Control to Output RL = 1 kΩ
t
PHZ
, t
PLZ
Maximum Disable Propagation Delay CL = 5 pF 18 25 ns
Control to Output RL = 1 kΩ
t
W
Minimum Clock Pulse Width 16 ns
t
S
Minimum Setup Time Data to Clock 5 ns
t
H
Minimum Hold Time Clock to Data 10 ns
Symbol Parameter Conditions
TA=25°CTA=−40 to 85°CTA=−55 to 125°C
Units
Typ Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation CL = 50 pF 22 30 37 45 ns
Delay Data to Output CL = 150 pF 30 40 50 60 ns
t
PHL
, t
PLH
Maximum Propagation Delay CL = 50 pF 25 35 44 53 ns
Latch Enable to Output CL = 150 pF 32 45 56 68 ns
t
PZH
, t
PZL
Maximum Enable Propagation CL = 50 pF 21 30 37 45 ns
Delay Control to Output CL = 150 pF 30 40 50 60 ns
RL = 1 kΩ
t
PHZ
, t
PLZ
Maximum Disable Propagation CL = 50 pF 21 30 37 45 ns
Delay Control to Output RL = 1 kΩ
t
THL
, t
TLH
Maximum Output Rise CL = 50 pF 8 12 15 18 ns
and Fall Time
t
W
Minimum Clock Pulse Width 16 20 24 ns
t
S
Minimum Setup Time Data to Clock 5 6 8 ns
t
H
Minimum Hold Time Clock to Data 1 0 13 20 ns
C
IN
Maximum Input Capacitance 10 10 10 pF
C
OUT
Maximum Output Capacitance 20 20 20 pF
C
PD
Power Dissipation Capacitance OC = V
CC
5pF
(Note 5) OC = GND 52 pF
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MM74HCT373 • MM74HCT374
AC Electrical Charac teristics
MM74HCT374: V
CC
= 5.0V, tr = tf = 6 ns T
A
= 25°C (unless otherwise specified)
AC Electrical Charac teristics
MM74HCT374: V
CC
= 5.0V ± 10%, tr = t
f
= 6 ns (unless otherwise specified)
Note 6: CPD determines the no load power consumptio n, PD = CPD VCC2 f + ICC VCC, and the no load dynam ic c urrent consumption , IS = CPD VCC f + ICC.
Symbol Parameter Conditions Typ
Guaranteed
Units
Limit
f
MAX
Maximum Clock Frequency 50 30 MHz
t
PHL
, t
PLH
Maximum Propagation Delay CL = 45 pF 20 32 ns
to Output
t
PZH
, t
PZL
Maximum Enable Propagation Delay CL = 45 pF 19 28 ns
Control to Output RL = 1 kΩ
t
PHZ
, t
PLZ
Maximum Disable Propagation Delay CL = 5 pF 17 25 ns
Control to Output RL = 1 kΩ
t
W
Minimum Clock Pulse Width 20 ns
t
S
Minimum Setup Time Data to Clock 5 ns
t
H
Minimum Hold Time Clock to Data 16 ns
Symbol Parameter Conditions
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
f
MAX
Maximum Clock Frequency 30 24 20 M Hz
t
PHL
, t
PLH
Maximum Propagation Delay CL = 50 pF 22 36 45 48 ns
to Output CL = 150 pF 30 46 57 69 ns
t
PZH
, t
PZL
Maximum Enable Propagation CL = 50 pF 21 30 37 45 ns
Delay Control to Output CL = 150 pF 30 40 50 60 ns
RL = 1 kΩ
t
PHZ
, t
PLZ
Maximum Disable Propagation CL = 50 pF 21 30 37 45 ns
Delay Control to Output RL = 1 kΩ
t
THL
, t
TLH
Maximum Output Rise CL = 50 pF 8 12 15 18 ns
and Fall Time
t
W
Minimum Clock Pulse Width 16 20 24 ns
t
S
Minimum Setup Time Data to Clock 20 25 30 ns
t
H
Minimum Hold Time Clock to Data 5 5 5 ns
C
IN
Maximum Input Capacitance 10 10 10 pF
C
OUT
Maximum Output Capacitance 20 20 20 pF
C
PD
Power Dissipation Capacitance OC = V
CC
5pF
(Note 6) OC = GND 58 pF
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MM74HCT373 • MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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MM74HCT373 • MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
Page 9
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HCT373 • MM74HCT374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the
user.
2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r easonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
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