Datasheet MM74HCT240WM, MM74HCT240WMX, MM74HCT240N, MM74HCT240SJ, MM74HCT240MTC Datasheet (Fairchild Semiconductor)
...Page 1
© 1999 Fairchild Semiconductor Corporation DS005365 www.fairchildsemi.com
February 1984
Revised July 1999
MM74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-STA TE Buffer
MM74HCT240 • MM74HCT244
Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
General Description
The MM74HCT240 and MM74HCT244 3-STATE buffers
utilize advanced silicon-gate CMOS technology and are
general purpose high speed inverting and non-inverting
buffers. They possess high drive current outputs which
enable high speed op eration even w hen driving l arge bus
capacitances. These circui ts achieve speeds comparable
to low power Schottky devices, while retaining the low
power consumption of CM OS. All three devices are TTL
input compatible and have a fanout of 15 LS -TTL equivalent inputs.
MM74HCT devices are in tended to interface b etween TT L
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to reduce power co nsumption in
existing designs.
The MM74HCT240 is an inverting buffer and the
MM74HCT244 is a non-invertin g buffer. Each device has
two active low enables (1G and 2G), and each enable independently controls 4 buffers.
All inputs are protected from damage due to static discharge by diodes to V
CC
and Ground.
Features
■ TTL input compatible
■ Typical propagation delay: 14 ns
■ 3-STATE outputs for connection to system buses
■ Low quiescent current: 80 µA
■ High output drive current: 6 mA (min)
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
MM74HCT240
Top View
MM74HCT244
Order Number Package Number Package Description
MM74HCT240WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HCT244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HCT244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT244MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT244N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HCT240 • MM74HCT244
Truth Tables
MM74HCT240 MM74HCT244
H = HIGH Level
L = LOW Level
Z = High Impedance
Logic Diagrams
MM74HCT240 MM74HCT244
1G
1A 1Y 2G 2A 2Y
LLHLLH
LHLLHL
HLZHLZ
HHZHHZ
1G 1A 1Y 2G 2A 2Y
LLLLLL
LHHLHH
HLZHLZ
HHZHHZ
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MM74HCT240 • MM74HCT244
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics
V
CC
= 5V ±10% (unless otherwise specified)
Note 4: Measured pe r input. All other inputs at VCC or GND.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to V
CC
+1.5V
DC Output Voltage (V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±35 mA
DC V
CC
or GND Current, per pin (ICC) ±70 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Solderi ng 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)4.55.5V
DC Input or Output Voltage 0 V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) 500 ns
Symbol Parameter Conditions
TA = 25°CTA = −40 to 85°CTA = −55° to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0 2.0 2.0 V
Input Voltage
V
IL
Maximum LOW Level 0.8 0.8 0.8 V
Input Voltage
V
OH
Minimum HIGH Level V
IN-EE
= VIH or V
IL
Output Voltage |I
OUT
| = 20 µAV
CCVCC
−0.1 VCC−0.1 VCC−0.1 V
|I
OUT
| = 6.0 mA, V
CC
= 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| = 7.2 mA, V
CC
= 5.5V 5.2 4.98 4.84 4.7 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Voltage |I
OUT
| = 20 µA 0 0.1 0.1 0.1 V
|I
OUT
| = 6.0 mA, V
CC
= 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| = 7.2 mA, V
CC
= 5.5V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND, ±0.05 ±0.5 ±1.0 µA
Current VIH or V
IL
I
OZ
Maximum 3-STATE V
OUT
= VCC or GND ±0.25 ±2.5 ±10 µA
Output Leakage
G = V
IH
Current G = V
IL
I
CC
Maximum Quiescent V
IN
= VCC or GND 4.0 40 160 µA
Supply Current I
OUT
= 0 µA
V
IN
= 2.4V or 0.5V (Note 4) 0.6 1.0 1.3 1.5 mA
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MM74HCT240 • MM74HCT244
AC Electrical Characteristics
MM74HCT240, MM74HCT244 VCC = 5.0V, tr = tf = 6 ns, TA = 25°C (unless otherwise specified)
AC Electrical Characteristics
MM74HCT240, MM74HCT244 VCC = 5.0V ± 10%, tr = tf = 6 ns (unless otherwise specified)
Note 5: CPD determines the no lo ad dynamic power con su m pt ion, PD = CPD VCC2 f + ICC VCC, and the no load dynam ic cu rrent consumption,
I
S
= CPD VCC f + ICC.
Symbol Parameter Conditions Typ
Guaranteed
Units
Limits
t
PHL
, t
PLH
Maximum Output CL = 45 pF 14 18 ns
Propagation Delay
t
PZL
, t
PZH
Maximum Output CL = 45 pF 20 30 ns
Enable Time RL = 1 kΩ
t
PLZ
, t
PHZ
Maximum Output CL = 5 pF 16 25 ns
Disable Time RL = 1 kΩ
Symbol Parameter Conditions
TA = 25°CTA = −40 to 85°CTA = −55° to 125°C
Units
Typ Guaranteed Limits
t
PHL
, t
PLH
Maximum Output CL = 50 pF 14 20 25 30 ns
Propagation Delay CL = 150 pF 20 28 35 42 ns
t
PZH
, t
PZL
Maximum Output RL = 1 kΩ CL = 50 pF 21 30 38 45 ns
Enable Time CL = 150 pF 26 42 53 63 ns
t
PHZ
, t
PLZ
Maximum Output RL = 1 kΩ 16 25 32 38 ns
Disable Time CL = 50 pF
t
THL
, t
TLH
Maximum Output CL = 50 pF 6 12 15 18 ns
Rise and Fall Time
C
IN
Maximum Input 10 15 15 15 pF
Capacitance
C
OUT
Maximum Output 15 20 20 20 pF
Capacitance
C
PD
Power Dissipation (per buffer)
Capacitance (Note 5)
G = VCC, G = GND
5pF
G = GND, G = V
CC
90 pF
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MM74HCT240 • MM74HCT244
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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MM74HCT240 • MM74HCT244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
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MM74HCT240 • MM74HCT244 Inverting Octal 3-STATE Buffer • Octal 3-STATE Buffer
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent license s are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical componen t in any com ponent o f a l ife supp ort
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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