Datasheet MM74HCT00SJ, MM74HCT00MX, MM74HCT00MTC, MM74HCT00CW, MM74HCT00SJX Datasheet (Fairchild Semiconductor)
...Page 1
February 1984
Revised February 1999
MM74HCT00 Quad 2 Input NAND Gate
© 1999 Fairchild Semiconductor Corporation DS005356.prf www.fairchildsemi.com
MM74HCT00
Quad 2 Input NAND Gate
General Description
The MM74HCT00 is a NAND gates fabricated using
advanced silicon-gate CMOS technology which provides
the inherent benefit s of CMOS—low qui escent power and
wide power supply range. This device is input and outp ut
characteristic and pin-out compatible with standar d 74LS
logic families. All inputs are protected from static discharge
damage by internal diodes to V
CC
and ground.
MM74HCT devices are intended to i nterface between TTL
and NMOS components and standard CMOS devices.
These parts are also plug-in replacements for LS-TTL
devices and can be used to redu ce power consumption in
existing designs.
Features
■ TTL, LS pin-out and threshold compatible
■ Fast switching: t
PLH
, t
PHL
=14 ns (typ)
■ Low power: 10 µW at DC
■ High fan out, 10 LS-TTL loads
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Logic Diagram
(1 of 4 gates)
Order Number Package Number Package Description
MM74HCT00M M14A 14-Lead Small Outline Integrate Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HCT00SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HCT00MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HCT00N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HCT00
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratin gs ar e tho se va lues beyond wh ich d am-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperatur e derat ing — pl astic “N” p ackage : −
12 mW/°C from 65 °C to 85°C.
DC Electrical Characteristics
VCC = 5V ± 10% (unless otherwise specified)
Note 4: This is measured per input with all other inputs held at VCC or ground.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to VCC+1.5V
DC Output Voltage (V
OUT
) −0.5 to VCC+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±25 mA
DC V
CC
or GND Current, per pin (ICC) ±50 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)4.55.5V
DC Input or Output Voltage 0 V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf)500ns
Symbol Parameter Conditions
TA = 25°CTA = −40 to 85°CTA = -55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0 2.0 2.0 V
Input Voltage
V
IL
Maximum LOW Level 0.8 0.8 0.8 V
Input Voltage
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| = 20 µAV
CCVCC
−0.1 VCC−0.1 VCC−0.1 V
|I
OUT
| = 4.0 mA, V
CC
= 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| = 4.8 mA, V
CC
= 5.5V 5.2 4.98 4.84 4.7 V
V
OL
Maximum LOW Level V
IN
= V
IH
Voltage |I
OUT
| = 20 µA00.10.10.1V
|I
OUT
| = 4.0 mA, VCC = 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| = 4.8 mA, V
CC
= 5.5V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND, ±0.05 ±0.5 ±1.0 µA
Current VIH or V
IL
I
CC
Maximum Quiescent V
IN
= VCC or GND, 1.0 10 40 µA
Supply Current I
OUT
= 0 µA
V
IN
= 2.4V or 0.5V (Note 4) 0.18 0.3 0.4 0.5 mA
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MM74HCT00
AC Electrical Characteristics
VCC = 5.0V, tr = tr = 6 ns, CL = 15 pF, TA = 25°C (unless otherwise noted)
AC Electrical Characteristics
VCC = 5.0V ±10%, tr = tf = 6 ns, CL = 50 pF (unless otherwise noted)
Note 5: CPD determines the no load dynamic power con s um ption, PD = CPD V
CC
2
f + ICC VCC, and the no load dynam ic c urrent consumption ,
I
S
= CPDVCCf + ICC.
Symbol Parameter Conditions Typ
Guaranteed
Limit
Units
t
PLH
, t
PHL
Maximum Propagation Delay 14 18 ns
Symbol Parameter Conditions
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
t
PLH
, t
PHL
Maximum Propagation Delay 18 23 29 35 ns
t
THL
, t
TLH
Maximum Output Rise & Fall
Time
815 19 22 ns
C
PD
Power Dissipation Capacitance (Note 5) 30 pF
C
IN
Input Capacitance 5 10 10 10 pF
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MM74HCT00
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
Package Number M14A
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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MM74HCT00
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HCT00 Quad 2 Input NAND Gate
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
2. A critical component in any c omponent of a life suppor t
device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Line Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
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