Datasheet MM74HC595WMX, MM74HC595SJX, MM74HC595SJ, MM74HC595MTCX, MM74HC595CW Datasheet (Fairchild Semiconductor)
...Page 1
September 1983
Revised February 1999
MM74HC595 8-Bit Shift Registers with Output Latches
© 1999 Fairchild Semiconductor Corporation DS005342.prf www.fairchildsemi.com
MM74HC595
8-Bit Shift Registers with Output Latches
General Description
The MM74HC595 high speed shift register utilizes
advanced silicon-gate CM OS techn ology. This device possesses the high noise immunity and low power consumption of standard CM OS integrated circuits , as well as the
ability to drive 15 LS-TTL loads.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-b it D-type storage re gister. The storage register has 8 3-STATE outputs. Separate clocks are
provided for both the shift register and the storage register.
The shift register has a dire ct-overridin g clear, serial input,
and serial output (standa rd) pins for cascading. Both the
shift register and storag e register use positive-edge triggered clocks. If both clocks are connected together, the
shift register state will always be one clock pulse ahead of
the storage register.
The 74HC logic family is speed, function, an d p in-o ut co mpatible with the sta ndard 74LS logic fami ly. All inputs are
protected from damage due to static discharge by inte rnal
diode clamps to V
CC
and ground.
Features
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ 8-bit serial-in, parallel-out shift register with storage
■ Wide operating voltage range: 2V–6V
■ Cascadable
■ Shift register has direct clear
■ Guaranteed shift frequency: DC to 30 MHz
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Connection Diagram
Pin Assignments f or DIP, SOIC, SOP and TSSOP
Top View
Truth Table
Order Number Package Number Package Description
MM74HC595M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC595WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74HC595SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC595MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC595N N16E 16-Lead Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
RCK SCK SCLR G Function
XX XHQ
A
thru QH = 3-STATE
X X L L Shift Register cleared
Q
H
= 0
X ↑ H L Shift Register clocked
Q
N
= Q
n-1
, Q0 = SER
↑ X H L Contents of Shift
Register t ransferred
to output latches
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MM74HC595
Logic Diagram
(positive logic)
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MM74HC595
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a powe r supply o f 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
IH
and VIL occur at V
CC
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3 .8 5V.) The worst c as e leakage cur-
rent (I
IN
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to V
CC
+1.5V
DC Output Voltage (V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±35 mA
DC V
CC
or GND Current,
per pin (I
CC
) ±70 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage
(V
IN
, V
OUT
)0V
CC
V
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) V
CC
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
Q
H
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| ≤ 5.2 mA 6.0V 5.2 5.48 5.34 5.2 V
QA thru Q
H
V
IN
= VIH or V
IL
|I
OUT
| ≤ 6.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| ≤ 7.8 mA 6.0V 5.7 5.48 5.34 5.2 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
Q
H
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
QA thru Q
H
V
IN
= VIH or V
IL
|I
OUT
| ≤ 6.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| ≤ 7.8 mA 6.0V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
I
OZ
Maximum 3-STATE V
OUT
= VCC or GND 6.0V ±0.5 ±5.0 ±10 µA
Output Leakage
G = V
IH
I
CC
Maximum Quiescent V
IN
= VCC or GND 6.0V 8.0 80 160 µA
Supply Current I
OUT
= 0 µA
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MM74HC595
AC Electrical Characteristics
V
CC
= 5V, TA = 25°C, tr = t
f
= 6 ns
Note 5: This setup time ensures the register will see stable data from the shift-register outputs. The clocks may be connected together in which case the storage register state w ill be one clock pulse behind the shift register.
AC Electrical Characteristics
V
CC
= 2.0−6.0V, CL = 50 pF, tr = t
f
= 6 ns (unless otherwise specified)
Symbol Parameter Conditions Typ
Guaranteed
Units
Limit
f
MAX
Maximum Operating 50 30 MHz
Frequency of SCK
t
PHL
, t
PLH
Maximum Propagation CL = 45 pF 12 20 ns
Delay, SCK to Q
H’
t
PHL
, t
PLH
Maximum Propagation CL = 45 pF 18 30 ns
Delay, RCK to QA thru Q
H
t
PZH
, t
PZL
Maximum Output Enable RL = 1 kΩ
Time from G to QA thru Q
H
CL = 45 pF 17 28 ns
t
PHZ
, t
PLZ
Maximum Output Disable RL = kΩ 15 25 ns
Time from G to QA thru Q
H
CL = 5 pF
t
S
Minimum Setup Time 20 ns
from SER to SCK
t
S
Minimum Setup Time 20 ns
from SCLR to SCK
t
S
Minimum Setup Time 40 ns
from SCK to RCK
(Note 5)
t
H
Minimum Hold Time 0ns
from SER to SCK
t
W
Minimum Pulse Width 16 ns
of SCK or RCK
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
f
MAX
Maximum Operating CL = 50 pF 2.0V 10 6 4.8 4.0 MHz
Frequency 4.5V 45 30 24 20 MHz
6.0V 50 35 28 24 MHz
t
PHL
, t
PLH
Maximum Propagation CL = 50 pF 2.0V 58 210 265 315 ns
Delay from SCK to Q
H
CL = 150 pF 2.0V 83 294 367 441 ns
CL = 50 pF 4.5V 14 42 53 63 ns
CL = 150 pF 4.5V 17 58 74 88 ns
CL = 50 pF 6.0V 10 36 45 54 ns
CL = 150 pF 6.0V 14 50 63 76 ns
t
PHL
, t
PLH
Maximum Propagation CL = 50 pF 2.0V 70 175 220 265 ns
Delay from RCK to QA thru QHCL = 150 pF 2.0V 105 245 306 368 ns
CL = 50 pF 4.5V 21 35 44 53 ns
CL = 150 pF 4.5V 28 49 61 74 ns
CL = 50 pF 6.0V 18 30 37 45 ns
CL = 150 pF 6.0V 26 42 53 63 ns
t
PHL
, t
PLH
Maximum Propagation 2.0V 175 221 261 ns
Delay from SCLR to Q
H
4.5V 35 44 52 ns
6.0V 30 37 44 ns
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MM74HC595
AC Electrical Characteristics (Continued)
Note 6: CPD determines the no load dynamic power con s um ption, PD = CPD V
CC
2
f + ICC VCC, and the no load dynam ic cu rrent consumption,
I
S
= CPDVCCf + ICC.
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
t
PZH
, t
PZL
Maximum Output Enable RL = 1 kΩ
from G to QA thru Q
H
CL = 50 pF 2.0V 75 175 220 265 ns
CL = 150 pF 2.0V 100 245 306 368 ns
CL = 50 pF 4.5V 15 35 44 53 ns
CL = 150 pF 4.5V 20 49 61 74 ns
CL = 50 pF 6.0V 13 30 37 45 ns
CL = 150 pF 6.0V 17 42 53 63 ns
t
PHZ
, t
PLZ
Maximum Output Disable RL = 1 kΩ 2.0V 75 175 220 265 ns
Time f rom G to QA thru Q
H
CL = 50 pF 4.5V 15 35 44 53 ns
6.0V 13 30 37 45 ns
t
S
Minimum Setup Time 2.0V 100 125 150 ns
from SER to SCK 4.5V 20 25 30 ns
6.0V 17 21 25 ns
t
R
Minimum Removal Time 2.0V 50 63 75 ns
from SCLR to SCK
4.5V 10 13 15 ns
6.0V 9 11 13 ns
t
S
Minimum Setup Time 2.0V 100 125 150 ns
from SCK to RCK 4.5V 20 25 30 ns
6.0V 17 21 26 ns
t
H
Minimum Hold Time 2.0V 5 5 5 ns
SER to SCK 4.5V 5 5 5 ns
6.0V 5 5 5 ns
t
W
Minimum Pulse Width 2.0V 30 80 100 120 ns
of SCK or SCLR
4.5V 9 16 20 24 ns
6.0V 8 14 18 22 ns
tr, t
f
Maximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time, Clock 4.5V 500 500 500 ns
6.0V 400 400 400 ns
t
THL
, t
TLH
Maximum Output 2.0V 25 60 75 90 ns
Rise and Fall Time 4.5V 7 12 15 18 ns
QA–Q
H
6.0V 6 10 13 15 ns
t
THL
, t
TLH
Maximum Output 2.0V 75 95 110 ns
Rise & Fall Time 4.5V 15 19 22 ns
Q
H
6.0V 13 16 19 ns
C
PD
Power Dissipation
G = V
CC
90 pF
Capacitance, Outputs
G = GND
150 pF
Enabled (Note 6)
C
IN
Maximum Input 5 10 10 10 pF
Capacitance
C
OUT
Maximum Output 15 20 20 20 pF
Capacitance
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MM74HC595
Timing Diagram
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MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M16B
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MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC595
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC595 8-Bit Shift Registers with Output Latches
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual--Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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