Datasheet MM74HC4051M, MM74HC4051SJ, MM74HC4051SJX, MM74HC4051MTC, MM74HC4051MTCX Datasheet (Fairchild Semiconductor)

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August 1984 Revised May 1999
MM74HC4051 • MM74HC4052 • MM74HC4053 8-Channel Analog Multiplexer •
© 1999 Fairchild Semiconductor Corporation DS005353.prf www.fairchildsemi.com
MM74HC4051 • MM74HC4052 • MM74HC4053 8-Channel Analog Multiplexer •
Dual 4-Channel Analog Multiplexer • Triple 2-Channel Analog Multiplexer
The MM74HC4051, MM74HC4052 and MM74HC4053 multiplexers are digitally controlled analog switches imple­mented in advanced silicon-gate CMOS technology. These
switches have low “on” resista nce and low “off” leakages. They are bidirectional switches, thus any an al og inp ut m ay be used as an output and vice-versa. Also these switches contain linearization circuitry which lowers the on resis­tance and increases switch linearity. These devices allow control of up to ±6V (peak) ana log signals wi th digital con­trol signals of 0 to 6V. Three supply pins are provided for V
CC
, ground, and VEE. This enables the connection of 0–
5V logic signals when V
CC
= 5V and an analog input range
of ±5V when V
EE
= 5V. All three devices also have an
inhibit control which when HIGH will disable all switches to their off state. All analog inputs and outputs and digital inputs are protected from electrostatic dama ge by diodes to V
CC
and ground.
MM74HC4051: This de vice connects to gether the outp uts of 8 switches, thus achieving an 8 channel Multiplexer. The binary code placed on the A, B , and C select lines dete r­mines which one o f the eight switches is “on”, and con­nects one of the eight inputs to the common output.
MM74HC4052: This d evice connects toge ther the output s of 4 switches in two sets, thus achieving a pair of 4-channel multiplexers. The binary code placed on the A, and B select lines determine which switch in each 4 channel sec­tion is “on”, connecting one of the fo ur inputs in each sec­tion to its common output. This enables the implementation of a 4-channel differential multiplexer.
MM74HC4053: This device contains 6 switches whose out­puts are connected t ogether in pairs, thus implementing a triple 2 channel multi plexer, or the equivalent of 3 singl e­pole-double throw con figurations. Each of the A, B, or C select lines independently controls one pair of switches, selecting one of the two switches to be “on”.
Features
Wide analog input voltage range: ±6V
Low “on” resistance:
50 typ. (V
CC–VEE
= 4.5V)
30 typ. (V
CC–VEE
= 9V)
Logic level translat ion to enable 5V logic w ith ±5V ana- log signals
Low quiescent current: 80 µA maximum (74HC)
Matched Switch characteristic
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering cod e.
Order Number Package Number Package Description
MM74HC4051M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC4051WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MM74HC4051SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC4051MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC4051N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-0010.300” Wide MM74HC4052M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC4052WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MM74HC4052SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC4052MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC4052N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-0010.300” Wide MM74HC4053M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow MM74HC4053WM M16B 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide MM74HC4053SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC4053MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC4053N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-0010.300” Wide
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MM74HC4051 • MM74HC4052 • MM74HC4053
Connection Diagrams
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Top View
Top View
Tr uth Tables
MM744051
MM744052
MM744053
Input “ON”
InhCBAChannel
H XXX None L LLL Y0 LLLH Y1 LLHL Y2 LLHH Y3 LHLL Y4 LHLH Y5 LHHL Y6 L HHH Y7
Inputs “ON” Channels
Inh B A X Y
H X X None None
LLL 0X 0Y LLH 1X 1Y LHL 2X 2Y LHH 3X 3Y
Input “ON” Channels
InhCBA C b a
H X X X Non e None None L L L L CX BX AX LLLHCX BX AY L L H L CX BY AX LLHHCX BY AY L H L L CY BX AX LHLHCY BX AY L H H L CY BY AX L HHH CY BY AY
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MM74HC4051 • MM74HC4052 • MM74HC4053
Logic Diagrams
MM74HC4051
MM74HC4052
MM74HC4053
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MM74HC4051 • MM74HC4052 • MM74HC4053
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temper ature dera ting — plas tic “N” packa ge:
12 mW/°C from 65 °C to 85°C.
DC Electrical Characteristics (Note 4)
Supply Voltage (V
CC
) 0.5 to +7.5V
Supply Voltage (V
EE
) +0.5 to 7.5V
Control Input Voltage (V
IN
) 1.5 to V
CC
+1.5V
Switch I/O Voltage (V
IO
)V
EE
0.5 to V
CC
+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
Output Current, per pin (I
OUT
) ±25 mA
V
CC
or GND Current, per pin (ICC) ±50 mA
Storage Temperature Range (T
STG
) 65°C to +150°C
Power Dissipation (P
D
) (Note 3) 600 mW S.O. Package only 500 mW
Lead Temperature (T
L
) (Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
Supply Voltage (V
EE
)0−6V
DC Input or Output Voltage
(V
IN
, V
OUT
)0V
CC
V
Operating Temperature Range (T
A
) 40 +85 °C
Input Rise or Fall Times
(t
r
, tf) VCC = 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
VEEV
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum LOW Level 2.0V 0.5 0.5 0.5 V Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
R
ON
Maximum “ON” Resistance V
INH
= VIL, IS = 2.0 mA GND 4.5V 40 160 200 240
(Note 5) V
IS
= VCC to V
EE
4.5V 4.5V 30 120 150 170 (Figure 1) −6.0V 6.0V 20 100 125 140 V
INH
= VIL, IS = 2.0 mA GND 2.0V 100 230 280 320
V
IS
= VCC or V
EE
GND 4.5V 40 110 140 170
(Figure 1) −4.5V 4.5V 20 90 120 140
6.0V 6.0V 15 80 100 115
R
ON
Maximum “ON” Resistance V
CTL
= V
IL
GND 4.5V 10 20 25 25
Matching V
IS
= VCC to GND 4.5V 4.5V 5 10 15 15
6.0V 6.0V 5 10 12 15
I
IN
Maximum Control V
IN
= VCCor GND ±0.1 ±1.0 ±1.0 µA
Input Current V
CC
= 26V
I
CC
Maximum Quiescent V
IN
= VCC or GND GND 6.0V 8 80 160 µA
Supply Current I
OUT
= 0 µA 6.0V 6.0V 16 160 320 µA
I
IZ
Maximum Switch “OFF” V
OS
= VCCor V
EE
GND 6.0V ±60 ±600 ±600 nA
Leakage Current V
IS
= VEEor V
CC
6.0V 6.0V ±100 ±1000 ±1000 nA
(Switch Input) V
INH
= VIH (Figure 2)
I
IZ
Maximum Switch V
IS
= VCC to V
EE
GND 6.0V ±0.2 ±2.0 ±2.0 µA
“ON” Leakage HC4051 V
INH
= V
IL
6.0V 6.0V ±0.4 ±4.0 ±4.0 µA
Current (Figure 3)
V
IS
= VCC to V
EE
GND 6.0V ±0.1 ±1.0 ±1.0 µA
HC4052 V
INH
= V
IL
(Figure 3) −6.0V 6.0V ±0.2 ±2.0 ±2.0 µA
V
IS
= VCC to V
EE
GND 6.0V ±0.1 ±1.0 ±1.0 µA
HC4053 V
INH
= VIL (Figure 3) −6.0V 6.0V ±0.1 ±1.0 ±1.0 µA
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MM74HC4051 • MM74HC4052 • MM74HC4053
DC Electrical Characteristics (Continued)
Note 4: For a power sup ply o f 5V ±10% the worst case on resistances (RON) occurs for HC at 4.5 V. Thus the 4.5V val ues shou ld be us ed w hen de sign ing
with this supply. Worst case V
IH
and VIL occur at V
CC
= 5.5V and 4. 5V respectively. (The VIH value at 5.5V is 3.85V.) The worst c as e leakage curre nt occur for CMOS at the higher v oltage and so the 5.5V v alues should be used. Note 5: At supply voltages (V
CC–VEE
) approaching 2V the anal og switc h on resist ance beco mes ext remely non -linear. Therefore it is reco mmended t hat
these devices be use d t o tr ansmit digital only when using these supply vo lta ges.
AC Electrical Characteristics
V
CC
= 2.0V6.0V, V
EE
= 0V6V, C
L
= 50 pF (unless otherwise specified)
Symbol Parameter Conditions
VEEV
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
I
IZ
Maximum Switch V
OS
= VCC or V
EE
GND 6.0V ±0.2 ±2.0 ±2.0 µA
“OFF” Leakage HC4051 V
IS
= VEE or V
CC
6.0V 6.0V ±0.4 ±4.0 ±4.0 µA
Current (Common Pin) V
INH
= V
IH
V
OS
= VCC or V
EE
GND 6.0V ±0.1 ±1.0 ±1.0 µA
HC4052 V
IS
= VEE or V
CC
6.0V 6.0V ±0.2 ±2.0 ±2.0 µA
V
INH
= V
IH
V
OS
= VCC or V
EE
GND 6.0V ±0.1 ±1.0 ±1.0 µA
HC4053 V
IS
= VEE or V
CC
6.0V 6.0V ±0.1 ±1.0 ±1.0 µA
V
INH
= V
IH
Symbol Parameter Conditions
VEEV
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation GND 2.0V 25 60 75 90 ns Delay Switch In to Out GND 4.5V 5 12 15 18 ns
4.5V 4.5V 4 8 12 14 ns
6.0V 6.0V 3 7 11 13 ns
t
PZL
, t
PZH
Maximum Switch Turn RL = 1 kΩ GND 2.0V 92 355 435 515 ns “ON” Delay GND 4.5V 69 87 103 ns
4.5V 4.5V 16 46 58 69 ns
6.0V 6.0V 15 41 51 62 ns
t
PHZ
, t
PLZ
Maximum Switch Turn GND 2.0V 65 290 365 435 ns “OFF” Delay GND 4.5V 28 58 73 87 ns
4.5V 4.5V 18 37 46 56 ns
6.0V 6.0V 16 32 41 48 ns
f
MAX
Minimum Switch GND 4.5V 30 MHz Frequency Response 4.5V 4.5V 35 MHz 20 log (VI/VO) = 3 dB Control to Switch RL = 600Ω,VIS = 4 VPP0V 4.5V 1080 mV Feedthrough Noise f = 1 MHz, VIS = 8 VPP−4.5V 4.5V 250 mV
CL = 50 pF Crosstalk between RL = 600Ω,VIS = 4 VPP0V 4.5 52 dB any Two Switches f = 1 MHz V
IS
= 8 VPP−4.5V 4.5V 50 dB
Switch OFF Signal RL = 600Ω,V
IS
= 4 VPP0V 4.5V 42 dB
Feedthrough f = 1 MHz, V
IS
= 8 VPP−4.5V 4.5V 44 dB
Isolation V
CTL
= V
IL
THD Sinewave Harmonic RL = 10 kΩ,V
IS
= 4 VPP0V 4.5V 0.013 %
Distortion CL = 50 pF, V
IS
= 8 VPP−4.5V 4.5V 0.008 %
f = 1 kHz
C
IN
Maximum Control 5 10 10 10 pF Input Capacitance
C
IN
Maximum Switch Input 15 pF Input Capacitance 4051 Common 90
4052 Common 45
4053 Common 30
C
IN
Maximum Feedthrough Capacitance
5pF
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MM74HC4051 • MM74HC4052 • MM74HC4053
AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” C hannel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. t
PHL, tPLH
Propagation Delay Time Signal Input to Signal Output
FIGURE 5. t
PZL, tPLZ
Propagation Delay Time Control to Signal Output
FIGURE 6. t
PZH, tPHZ
Propagation Delay Time Control to Signal Output
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MM74HC4051 • MM74HC4052 • MM74HC4053
AC Test Circuits and Switching Time Wavef orms (Continued)
FIGURE 7. Crosstalk: Control Input to Signal Output
FIGURE 8. Crosstalk Between Any Two Switches
Typical Performance Characteristics
Typical “On” Resistance vs Input Voltage
V
CC
=−V
EE
Special Considerations
In certain applications the external load-resistor current may include both V
CC
and signal line components. To
avoid drawing V
CC
current when switch curr ent flows into
the analog switch p ins, th e voltage drop a cross t he switch must not exceed 1.2V (calculated from the ON resistance).
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MM74HC4051 • MM74HC4052 • MM74HC4053
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
Package Number M16B
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MM74HC4051 • MM74HC4052 • MM74HC4053
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC4051 • MM74HC4052 • MM74HC4053
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
Page 11
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC4051 • MM74HC4052 • MM74HC4053 8-Channel Analog Multiplexer •
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:
1. Life sup por t de vices o r systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided i n the labe li ng, can be re a­sonably expected to result in a significant injury to the user.
2. A c ritica l compo nent i n any compo nent o f a life s uppor t device or system whose failu re to perform can b e rea­sonably expected to c ause th e fa i lure of the li fe s upp or t device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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