Datasheet MM74HC4049N, MM74HC4049MTCX, MM74HC4049CW, MM74HC4049M Datasheet (Fairchild Semiconductor)
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© 1999 Fairchild Semiconductor Corporation DS005214 www.fairchildsemi.com
February 1984
Revised October 1999
MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter
MM74HC4049 • MM74HC4050
Hex Inverting Logic Level Down Converter •
Hex Logic Level Down Converter
General Description
The MM74HC4049 and the MM74HC4050 utilize
advanced silicon-gate CMOS technology, and have a modified input protection structu re that enables these parts to
be used as logic level translators which will convert high
level logic to a low level logic while operating from the low
logic supply. For example, 0–15V CMOS logic can be converted to 0–5V logic when usin g a 5V su pply. The modified
input protection has no diode connected to V
CC
, thus allow-
ing the input voltage to exceed the supply. The lower zener
diode protects the input fr om both positive and negative
static voltages. In addition each part can be used as a sim-
ple buffer or inverter without level translation. The
MM74HC4049 is pin and functionally compatible to the
CD4049BC and the MM74HC4050 is compatible to the
CD4050BC
Features
■ Typical propagation delay: 8 ns
■ Wide power supply range: 2V–6V
■ Low quiescent supply current: 20 µA maximum (74HC)
■ Fanout of 10 LS-TTL loads
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagrams
MM74HC4049
MM74HC4050
Order Number Package Number Package Description
MM74HC4049M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4049SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4049MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide
MM74HC4049N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74HC4050M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC4050SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC4050MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153. 4.4mm Wide
MM74HC4050N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HC4049 • MM74HC4050
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temper ature dera ting — plas tic “N” packa ge: −
12 mW/°C from 65 °C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a power supply of 5V ±10% the wor st case output vo ltages (VOH and VOL) occur for HC a t 4.5 V. Thus the 4.5V values should be u sed wh en
designing with this supply. Worst case V
IH
and VIL occur at V
CC
= 5.5V and 4.5V res pectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage c ur-
rent (I
IN
, ICC, IOZ) occur for CMOS at the higher voltage and so the 6. 0V values should be use d.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to +18V
DC Output Voltage (V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
ZK
, IOK) −20 mA
DC Output Current, per pin (I
OUT
) ±25 mA
DC V
CC
or GND Current, per pin (ICC) ±50 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input Voltage 0 15 V
(V
IN
)
DC Output Voltage 0 V
CC
V
(V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) V
CC
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40°C to 85°CTA = −55°C to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level Input 2.0V 1.5 1.5 1.5 V
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum LOW Level Input 2.0V 0.5 0.5 0.5 V
Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4 mA 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input Current V
IN
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
V
IN
= 15V 2.0V ±0.5 ±5 ±5 µA
I
CC
Maximum Quiescent Supply V
IN
= VCC or GND 6.0V 2.0 20 40 µA
Current I
OUT
= 0 µA
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MM74HC4049 • MM74HC4050
AC Electrical Characteristics
V
CC
= 5V, T
A
= 25°C, C
L
= 15 pF, tr = t
f
= 6 ns
AC Electrical Characteristics
V
CC
= 2.0V to 6.0V, CL = 50 pF, tr = t
f
= 6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynamic power con s um ption, PD = CPD V
CC
2
f + ICC VCC, and the no load dynam ic current consumpt ion,
I
S
= CPDVCCf + ICC.
Symbol Parameter Conditions Typ
Guaranteed
Units
Limit
t
PHL
, t
PLH
Maximum Propagation Delay 8 15 ns
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40° to 85°CTA = −55° to 125°C
Units
Typ Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation 2.0V 30 85 100 130 ns
Delay 4.5V 10 17 20 26 ns
6.0V 9 15 18 22 ns
t
THL
, t
TLH
Maximum Output 2.0V 25 75 95 110 ns
Rise and Fall 4.5V 7 15 19 22 ns
Time 6.0V 6 13 16 19 ns
C
PD
Power Dissipation (per gate) 25 pF
Capacitance (Note 5)
C
IN
Maximum Input 5 10 10 10 pF
Capacitance
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MM74HC4049 • MM74HC4050
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC4049 • MM74HC4050
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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MM74HC4049 • MM74HC4050 Hex Inverting Logic Level Down Converter • Hex Logic Level Down Converter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be reasonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.
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