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MM74HC273
Octal D-Type Flip-Flops with Clear
MM74HC273 Octal D-Type Flip-Flops with Clear
September 1983
Revised May 2005
General Description
The MM74HC273 edge triggered flip-flops utilize advanced
silicon-gate CMOS technology to implement D-type flipflops. They possess high noi se immunity, low power, and
speeds comparable to low power Schottky TTL circuits.
This device contains 8 master-slave flip-flops with a common clock and common clear. Data on the D input having
the specified se tup and hold times is tran sferred to th e Q
output on the LOW-to-HIG H tra nsiti o n of t he CL OC K i np ut.
The CLEAR input when LOW, sets all outputs to a low
state.
Each output can dri ve 10 low power S chottky TT L equivalent loads. The MM74HC 273 is function ally as well as pi n
compatible to the 74LS273. All inputs are protec ted from
damage due to static discharge by diodes to V
ground.
CC
Features
■ Typical propagation delay: 18 ns
■ Wide operating voltage range
■ Low input current: 1
■ Low quiescent current: 80
■ Output drive: 10 LS-TTL loads
and
P
A maximum
P
A (74 Series)
Ordering Code:
Order Number Package Number Package Description
MM74HC273WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
MM74HC273SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC273MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC273N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also availab l e in Tape and Reel. Specify by appending the suffix lett er “X” to the ordering code .
Connection Diagram
Top View
© 2005 Fairchild Semiconductor Corporation DS005331 www.fairchildsemi.com
Page 3
Truth Table
(Each Flip-Flop)
Clear Clock D Q
MM74HC273
H HIGH Level (S t eady State)
L LOW Level (S t eady State)
X Don’t Care
n
Transition from LOW-to-HIGH level
The level of Q before the indica ted ste ady state inp ut co ndit ions were
Q
0
established
Inputs Outputs
LXXL
H
H
n
n
HH
LL
HLXQ
Logic Diagram
0
www.fairchildsemi.com 2
Page 4
Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC)
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
)
IN
)
OUT
, IOK)
IK
)
OUT
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (T
Power Dissipation (P
)
D
STG
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (TL)
(Soldering 10 seconds) 260qC
1.5 to V
0.5 to V
65q
0.5 to 7.0V
CC
CC
C to 150qC
r
20 mA
r
25 mA
r
50 mA
Recommended Operating
Conditions
1.5V
Supply Voltage (V
0.5V
DC Input or Output Voltage
(VIN, V
OUT
Operating Temperature Range (TA)4085
Input Rise or Fall Times
(tr, tf) V
CC
V
CC
V
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwis e s pecified all voltages are ref erenced to ground.
Note 3: Power Dissipation tem perature d erating — plastic “N” package:
12 mW/qC from 65qC to 85qC.
CC
)26V
CC
)0V
2.0V 1000 ns
4.5V 500 ns
6.0V 400 ns
Min Max Units
CC
DC Electrical Characteristics (Note 4)
TA
Symbol Parameter Conditions
V
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
V
Minimum HIGH Level V
OH
Output Voltage |I
V
Maximum LOW Level V
OL
Output Voltage |I
I
Maximum Input V
IN
Current
I
Maximum Quiescent V
CC
Supply Current I
Note 4: For a power supply of 5V r10% the worst case output voltages (VOH, and VOL) occur for HC a t 4.5V. Thus the 4.5V values s hould b e used w hen
designing with this s upply. Worst case VIH and VIL occur at V
rent (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
VIH or V
V
|I
|I
V
|I
|I
OUT
IN
OUT
IN
OUT
OUT
IN
OUT
IN
OUT
OUT
IN
IN
IL
| d 20 PA 2.0V 2.0 1.9 1.9 1.9 V
VIH or V
IL
| d 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
| d 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
VIH or V
IL
| d 20 PA 2.0V 0 0.1 0.1 0.1 V
VIH or V
IL
| d 4 mA 4.5V 0.2 0.26 0.33 0.4 V
| d 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
VCC or GND 6.0V
VCC or GND 6.0V 8 80 160
0 PA
CC
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
25qCTA
Typ Guaranteed Limits
r
0.1
40 to 85qCTA
r
1.0
55 to 125qC
r
1.0
MM74HC273
V
q
C
Units
P
A
P
A
3 www.fairchildsemi.com
Page 5
AC Electrical Characteristics
V
5V, T
CC
25qC, C
A
15 pF, t
L
t
6 ns
r
f
Symbol Parameter Conditions Typ
f
MAX
MM74HC273
, t
t
PHL
PLH
Maximum Operating Frequency 50 30 MHz
Maximum Propagation 18 27 ns
Delay, Clock to Output
t
PHL
Maximum Propagation 18 27 ns
Delay, Clear to Output
t
REM
Minimum Removal Ti me, 10 20 ns
Clear to Clock
t
s
Minimum Setup Time 10 20 ns
Data to Clock
t
H
Minimum Hold Time
Clock to Data
t
W
Minimum Pulse Width 10 16 ns
Clock or Clear
AC Electrical Characteristics
C
50 pF, t
t
L
Symbol Parameter Conditions
f
MAX
t
, t
PHL
PLH
t
PHL
t
REM
t
s
t
H
t
W
tr, t
f
t
, t
THL
TLH
C
PD
C
IN
Note 5: CPD determines the no lo ad dynamic power con s um ption, P
I
CPDVCCf ICC.
S
6 ns (unless otherwise specified)
r
f
V
CC
TA
25qCTA
Typ Guaranteed Limits
Maximum Operating 2.0V 16 5 4 3 MHz
Frequency 4.5V 74 27 21 18 MHz
6.0V 78 31 24 20 MHz
Maximum Propagation 2.0V 38 135 170 205 ns
Delay, Clock to Output 4.5V 14 27 34 41 ns
6.0V 12 23 29 35 ns
Maximum Propagation 2.0V 42 135 170 205 ns
Delay, Clear to Output 4.5V 19 27 34 41 ns
6.0V 18 23 29 35 ns
Minimum Removal Time 2.0V 0 25 32 37 ns
Clear to Clock 4.5V 0 5 6 7 ns
6.0V 0 4 5 6 ns
Minimum Setup Time 2.0V 26 100 125 150 ns
Data to Clock 4.5V 7 20 25 30 ns
6.0V 5 17 21 25 ns
Minimum Hold Time 2.0V
Clock to Data 4.5V
6.0V
15 0 0 0 ns
60 0 0 ns
40 0 0 ns
Minimum Pulse Width 2.0V 34 80 100 120 ns
Clock or Clear 4.5V 11 16 20 24 ns
6.0V 10 14 18 20 ns
Maximum Input Rise and 2.0V 1000 1000 1000 ns
Fall Time, Clock 4.5V 500 500 500 ns
6.0V 400 400 400 ns
Maximum Output Rise 2.0V 28 75 95 110 ns
and Fall Time 4.5V 11 15 19 22 ns
6.0V 9 13 16 19 ns
Power Dissipation (per flip-flop) 45 pF
Capacitance (Note 5)
Maximum Input 7 10 10 10 pF
Capacitance
2
CPD V
D
f ICC VCC, and the no load dynamic current consumption,
CC
Guaranteed
Limit
20ns
40 to 85qCTA
55 to 125qC
Units
Units
www.fairchildsemi.com 4
Page 6
Physical Dimensions inches (millimeters) unless otherwise noted
MM74HC273
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5 www.fairchildsemi.com
Page 7
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC273
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
www.fairchildsemi.com 6
Package Number M20D
Page 8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC273
20-Lead Thin Shrin k Small Ou tlin e Pack age (TSSOP), JEDEC MO-153, 4.4mm Wid e
Package Number MTC20
7 www.fairchildsemi.com
Page 9
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC273 Octal D-Type Flip-Flops with Clear
Fairchild does not assume any responsibility for use of any circu itry described, no circuit patent licenses are imp lied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant inju ry to the
user.
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
2. A critical component in any componen t of a life support
device or system whose failu re to perform can be reasonably expected to cause the failure of the l ife su pp ort
device or system, or to affect its safety or effectiveness.
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