Datasheet MM74HC251MX, MM74HC251SJX, MM74HC251N, MM74HC251MTCX, MM74HC251M Datasheet (Fairchild Semiconductor)
...Page 1
September 1983
Revised February 1999
MM74HC251 8-Channel 3-STATE Multiplexer
© 1999 Fairchild Semiconductor Corporation DS005328.prf www.fairchildsemi.com
MM74HC251
8-Channel 3-STATE Multiplexer
General Description
The MM74HC251 8-channel digital multiplexer with 3STATE outputs utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power
consumption of standar d CMOS integrated c ircuits, it possesses the ability to drive 10 LS-TTL loads. The large output drive capability and 3-STATE feature make this part
ideally suited for interfacing with bus lines in a bus oriented
system.
This multiplexer features both true (Y) and complement
(W) outputs as well as a STROBE input. The STROBE
must be at a low logic level to enable this device. When the
STROBE input is HIGH, both outputs are in the high
impedance state. When e nabled, address information on
the data select inputs determines which data input is routed
to the Y and W outputs. The 74HC logic family is speed,
function, as well as pinout co mpatible with the standard
74LS logic family. All inputs are protected from damage
due to static discharge by internal diode clamps to V
CC
and
ground.
Features
■ Typical propagation delay
Data select to Y: 26 ns
■ Wide supply range: 2–6V
■ Low power supply quiescent current:
80 µA maximum (74 HC)
■ 3-STATE outputs for interface to bus oriented
systems
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Order Number Package Number Package Description
MM74HC251M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74HC251SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC251MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC251N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HC251
Truth Table
H = HIGH Logic Level, L = LOW Logic Level
X = Irrelevant, Z = High Impedance (o ff)
D0, D1. . . D7 = The level of the respective D input
Logic Diagram
Inputs Outputs
Select Strobe
YW
CBA S
XXX H ZZ
L L L L D0 D0
L L H L D1 D1
L H L L D2 D2
L H H L D3 D3
H L L L D4 D4
H L H L D5 D5
H H L L D6 D6
HHH L D7D7
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MM74HC251
Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Note 1: Absolute Maximum Rati ngs are tho se values b eyond which d am-
age to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to gro und.
Note 3: Power Dissipation temperature de rating — p lastic “N” p ackage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
Note 4: For a power supply o f 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4 .5V. Thus the 4.5V values s hould be us ed wh en
designing with this supply. Worst case V
IH
and VIL occur at V
CC
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values s hould be used.
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
IN
) −1.5 to V
CC
+1.5V
DC Output Voltage (V
OUT
) −0.5 to V
CC
+0.5V
Clamp Diode Current (I
IK
, IOK) ±20 mA
DC Output Current, per pin (I
OUT
) ±25 mA
DC V
CC
or GND Current, per pin (ICC) ±50 mA
Storage Temperature Range (T
STG
) −65°C to +150°C
Power Dissipation (P
D
)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage
(V
IN
, V
OUT
)0V
CC
V
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) V
CC
= 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
V
IH
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 1.35 V
6.0V 1.8 1.8 1.8 V
V
OH
Minimum HIGH Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
|I
OUT
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
V
OL
Maximum LOW Level V
IN
= VIH or V
IL
Output Voltage |I
OUT
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
V
IN
= VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
|I
OUT
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input V
IN
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
Current
I
OZ
Maximum 3-STATE Strobe = V
CC
6.0V ±0.5 ±5 ±10 µA
Leakage Current V
OUT
= VCC or GND
I
CC
Maximum Quiescent V
IN
= VCC or GND 6.0V 8.0 80 160 µA
Supply Current I
OUT
= 0 µA
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MM74HC251
AC Electrical Charac teristics
V
CC
= 5V, T
A
= 25°C, C
L
= 15 pF, tr = t
f
= 6 ns
AC Electrical Charac teristics
C
L
= 50 pF, tr = t
f
= 6 ns (unless otherwise specified)
Note 5: CPD determines the no load dynamic power cons um ption, PD = CPD V
CC
2
f + ICC VCC, and the no load dynam ic c urrent consumption,
I
S
= CPDVCCf + ICC.
Symbol Parameter Conditions Typ
Guaranteed
Units
Limit
t
PHL
, t
PLH
Maximum Propagation Delay 26 35 ns
A, B or C to Y
t
PHL
, t
PLH
Maximum Propagation 27 35 ns
Delay, A, B or C to W
t
PHL
, t
PLH
Maximum Propagation 22 29 ns
Delay, Any D to Y
t
PHL
, t
PLH
Maximum Propagation 24 32 ns
Delay, Any D to W
t
PZH
, t
PZL
Maximum Output Enable RL = 1 kΩ 19 27 ns
Time, W Output CL = 50 pF
t
PZH
, t
PZL
Maximum Output Enable RL = 1 kΩ 19 26 ns
Time, Y Output CL = 50 pF
t
PHZ
, t
PLZ
Maximum Output Disable Time RL = 1 kΩ 26 40 ns
W Output CL = 5 pF
t
PHZ
, t
PLZ
Maximum Output Disable Time RL = 1 kΩ 27 35 ns
Y Output CL = 5 pF
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Units
Typ Guaranteed Limits
t
PHL
, t
PLH
Maximum Propagation Delay 2.0V 90 205 256 300 ns
A, B or C to Y 4.5V 31 41 51 60 ns
6.0V 26 35 44 51 ns
t
PHL
, t
PLH
Maximum Propagation 2.0V 95 205 256 300 ns
Delay, A, B or C to W 4.5V 32 41 51 60 ns
6.0V 27 35 44 51 ns
t
PHL
, t
PLH
Maximum Propagation 2.0V 70 195 244 283 ns
Delay, any D to Y 4.5V 27 39 49 57 ns
6.0V 23 33 41 48 ns
t
PHL
, t
PLH
Maximum Propagation 2.0V 75 185 231 268 ns
Delay, any D to W 4.5V 29 37 46 54 ns
6.0V 25 32 40 46 ns
t
PZH
, t
PZL
Maximum Output Enable Time RL = 1 kΩ 2.0V 45 150 188 218 ns
W Output 4.5V 21 30 38 44 ns
6.0V 18 26 33 38 ns
t
PZH
, t
PZL
Maximum Output Enable Time RL = 1 kΩ 2.0V 45 145 181 210 ns
Y Output 4.5V 21 29 36 42 ns
6.0V 18 25 31 36 ns
t
PHZ
, t
PLZ
Maximum Output Disable Time RL = 1 kΩ 2.0V 60 220 275 319 ns
W Output 4.5V 29 44 55 64 ns
6.0V 25 37 46 54 ns
t
PHZ
, t
PLZ
Maximum Output Disable Time RL = 1 kΩ 2.0V 60 195 244 283 ns
Y Output 4.5V 30 39 49 57 ns
6.0V 26 33 41 48 ns
t
THL
, t
TLH
Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
C
PD
Power Dissipation Capacitance (Note 5) (per package) 110 pF
C
IN
Maximum Input Capacitance 5 10 10 10 pF
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MM74HC251
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC251
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change sai d circuitry and specifications.
MM74HC251 8-Channel 3-STA TE Multiplexer
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the
user.
2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r easonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16A
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