Datasheet MM74HC151M, MM74HC151MTC, MM74HC151MTCX, MM74HC151SJ, MM74HC151MX Datasheet (Fairchild Semiconductor)
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MM74HC151
8-Channel Digital Multiplexer
MM74HC151 8-Channel Digital Multiplexer
September 1983
Revised February 1999
General Description
The MM74HC151 high speed Digital multiplexer utilizes
advanced silicon-gate CMOS technology. Along with the
high noise immunity and low pow er dissip ation of stan dard
CMOS integrated circuits, it possesses the ability to drive
10 LS-TTL loads. The MM74HC151 selects o ne of the 8
data sources, depend ing on the address p resented o n the
A, B, and C inputs. I t features both true (Y) and complement (W) outputs. The STROBE input must be at a low
logic level to enable this multiplexer. A high logic level at
the STROBE forces the W output HIGH and the Y output
LOW.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to V
and ground.
CC
Features
■ Typical propagation delay data select to output Y: 26 ns
■ Wide operating supply voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent supply current: 80 µA maximum (74HC)
■ High output drive current: 4 mA minimum
Ordering Code:
Order Number Package Number Package Description
MM74HC151M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC151SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC151MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC151N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also availab le in Tape and Reel. Specify by appending th e s uffix let t er “X” to the ordering code.
Connection Diagram
Pin Assignments for DIP, SOIC, SOP and TSSOP
Top View
Truth Table
Inputs Outputs
Select Strobe
CBA S Y W
XXX H L H
LLL L D0D0
LLH L D1D1
LHL L D2D2
LHH L D3D3
HLL L D4D4
HLH L D5D5
HHL L D6D6
HHH L D7D7
H = HIGH Level, L = LOW Level, X = Don't Care
D0, D1...D7 = the level of the respective D input
© 1999 Fairchild Semiconductor Corporation DS005313.prf www.fairchildsemi.com
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Logic Diagram
MM74HC151
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Absolute Maximum Ratings(Note 1)
(Note 2)
Supply Voltage (VCC) −0.5 to +7.0V
DC Input Voltage (V
DC Output Voltage (V
Clamp Diode Current (I
DC Output Current, per pin (I
or GND Current, per pin (ICC) ±50 mA
DC V
CC
Storage Temperature Range (T
Power Dissipation (P
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
(Soldering 10 seconds )
) −1.5 to V
IN
) −0.5 to V
OUT
, IOK) ±20 mA
IK
) ±25 mA
OUT
) −65°C to +150°C
STG
)
D
)260°C
L
CC
CC
Recommended Operating
Conditions
+1.5V
Supply Voltage (V
+0.5V
DC Input or Output Voltage 0 V
, V
(V
IN
OUT
Operating Temperature Range (T
Input Rise or Fall Times
, tf) V
(t
r
CC
V
CC
V
Note 1: Absolute Maximum Ra tings are those valu es beyond w hich damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
CC
)26V
CC
)
) −40 +85 °C
A
= 2.0V 1000 ns
= 4.5V 500 ns
= 6.0V 400 ns
Min Max Units
CC
DC Electrical Characteristics (Note 4)
Symbol Parameter Conditions
V
Minimum HIGH Level 2.0V 1.5 1.5 1.5 V
IH
Input Voltage 4.5V 3.15 3.15 3.15 V
V
Maximum LOW Level 2.0V 0.5 0.5 0.5 V
IL
Input Voltage 4.5V 1.35 1.35 1.35 V
V
Minimum HIGH Level V
OH
Output Voltage |I
V
Maximum LOW Level V
OL
Output Voltage |I
I
Maximum Input V
IN
Current
I
Maximum Quiescent V
CC
Supply Current I
Note 4: For a powe r supply o f 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when
designing with this supply. Worst case V
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be us ed.
rent (I
IN
= VIH or V
IN
OUT
V
IN
|I
OUT
|I
OUT
IN
OUT
V
IN
|I
OUT
|I
OUT
IN
IN
OUT
and VIL occur at V
IH
IL
| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V
= VIH or V
IL
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
= VIH or V
IL
| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V
= VIH or V
IL
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
= VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA
= VCC or GND 6.0V 8.0 80 160 µA
= 0 µA
CC
V
CC
6.0V 4.2 4.2 4.2 V
6.0V 1.8 1.8 1.8 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
= 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3 .8 5V.) The worst c as e leakage cur-
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
MM74HC151
V
Units
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AC Electrical Characteristics
V
= 5V, T
CC
= 25°C, C
A
= 15 pF, tr = t
L
= 6 ns
f
Symbol Parameter Conditions Typ
t
, t
PHL
PLH
MM74HC151
t
, t
PHL
PLH
Maximum Propagation Delay 26 35 ns
A, B or C to Y
Maximum Propagation Delay 27 35 ns
A, B or C to W
t
PHL
, t
PLH
Maximum Propagation Delay 22 29 ns
Any D to Y
t
PHL
, t
PLH
Maximum Propagation Delay 24 32 ns
any D to W
t
PHL
, t
PLH
Maximum Propagation Delay 17 23 ns
Strobe to Y
t
PHL
, t
PLH
Maximum Propagation Delay 16 21 ns
Strobe to W
AC Electrical Characteristics
C
= 50 pF, tr = t
L
Symbol Parameter Conditions
t
, t
PHL
PLH
t
, t
PHL
PLH
t
, t
PHL
PLH
t
, t
PHL
PLH
t
, t
PHL
PLH
t
, t
PHL
PLH
t
, t
TLH
THL
C
PD
C
IN
Note 5: CPD determines the no lo ad dynamic power con s um ption, PD = CPD V
= CPD VCC f + ICC.
I
S
= 6 ns (unless otherwise specified)
f
V
CC
TA = 25°CTA = −40 to 85°CTA = −55 to 125°C
Typ Guaranteed Limits
Maximum Propagation Delay 2.0V 90 205 256 300 ns
A, B or C to Y 4.5V 31 41 51 60 ns
6.0V 26 35 44 51 ns
Maximum Propagation Delay 2.0V 95 205 256 300 ns
A, B or C to W 4.5V 32 41 51 60 ns
6.0V 27 35 44 51 ns
Maximum Propagation Delay 2.0V 70 195 244 283 ns
any D to Y 4.5V 27 39 49 57 ns
6.0V 23 33 41 48 ns
Maximum Propagation Delay 2.0V 75 185 231 268 ns
any D to W 4.5V 29 37 46 54 ns
6.0V 25 32 40 46 ns
Maximum Propagation Delay 2.0V 50 140 175 203 ns
Strobe to Y 4.5V 21 28 35 41 ns
6.0V 18 24 30 35 ns
Maximum Propagation Delay 2.0V 45 127 159 185 ns
Strobe to W 4.5V 20 25 32 37 ns
6.0V 17 22 28 32 ns
Maximum Output Rise 2.0V 30 75 95 110 ns
and Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
Power Dissipation (per package) 110 pF
Capacitance (Note 5)
Maximum Input 5 10 10 10 pF
Capacitance
2
f + ICC VCC, and the no load dynamic current consu m pt ion,
CC
Guaranteed
Limit
Units
Units
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Physical Dimensions inches (millimeters) unless otherwise noted
MM74HC151
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16A
Package Number M16D
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC151
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
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Package Number MTC16
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
MM74HC151 8-Channel Digital Multiplexer
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provide d in the labe l ing, can be re asonably expected to result in a significant injury to the
user.
Package Number N16E
2. A critical component in any com ponen t of a life s uppor t
device or system whose failu re to perform can b e reasonably expected to cause the failure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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