Datasheet MM74HC138N, MM74HC138SJ, MM74HC138SJX, MM74HC138M, MM74HC138MTC Datasheet (Fairchild Semiconductor)
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September 1983
Revised February 1999
MM74HC138 3-to-8 Line Decoder
© 1999 Fairchild Semiconductor Corporation DS005120.prf www.fairchildsemi.com
MM74HC138
3-to-8 Line Decoder
General Description
The MM74HC138 decoder utilizes advanced silicon-gate
CMOS technology and is well suited to memory address
decoding or data routing applications. The circuit features
high noise immunity and l ow power consumption usually
associated with CMOS circuitry, yet has speeds compar able to low power Schottky TTL logic.
The MM74HC138 has 3 binary select inp uts (A, B, an d C).
If the device is enabled, these inputs determine which one
of the eight normally HIGH outputs will go LOW. Two active
LOW and one active HIGH enables (G1, G2A
and G2B)
are provided to ease the cascading of decoders.
The decoder’s outputs can drive 10 low power Schottky
TTL equivalent load s, and are functionall y and pin equivalent to the 74LS138. All i nputs are prot ected from d amage
due to static discharge by diodes to V
CC
and ground.
Features
■ Typical propagation delay: 20 ns
■ Wide power supply range: 2V–6V
■ Low quiescent current: 80 µA maximum (74HC Series)
■ Low input current: 1 µA maximum
■ Fanout of 10 LS-TTL loads
Ordering Code:
Devices also availab le in Tape and Reel. Specify by appending su ffix let te r “X” to the ordering code .
Connection Diagram
Pin Assignment for DIP, SOIC, SOP and TSSOP
Order Number Package Number Package Description
MM74HC138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74HC138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC138MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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MM74HC138
Truth Table
H = HIGH Level, L = LOW Level, X = don’t care
Note 1: G2
= G2A+G2B
Logic Diagram
Inputs Outputs
Enable Select
G1 G2
(Note 1) C B A Y0Y1Y2Y3Y4Y5Y6Y7
X H XXXHHHHHHHH
L X XXXHHHHHHHH
H L LL LLHHHHHHH
H L LLHHLHHHHHH
H L LHLHHLHHHHH
H L LHHHHHLHHHH
H L HLLHHHHLHHH
H L HLHHHHHHLHH
H L HHLHHHHHHLH
H L HHHHHHHHHHL
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MM74HC138
Absolute Maximum Ratings(Note 2)
(Note 3)
Recommended Operating
Conditions
Note 2: Absolute Maximum Ra tings are those valu es beyond w hich dam-
age to the device may occur.
Note 3: Unless otherwise specified all voltages are referenced to ground.
Note 4: Power Dissipation te mperature d erating — pl astic “N” pa ckage: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 5)
Note 5: For a powe r su pply of 5V ± 10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values sho uld be used when
designing with this supply. Worst case V
IH
and VIL occur at VCC = 5.5V and 4.5 V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-
rent (I
IN
, ICC, and IOZ) occur for CMOS at the higher voltage and so th e 6. 0V values should be used.
Supply Voltage (VCC) − 0.5 to + 7.0V
DC Input Voltage (V
IN
) − 1.5 to V
CC
+ 1.5V
DC Output Voltage (V
OUT
) − 0.5 to V
CC
+ 0.5V
Clamp Diode Current (I
IK
, IOK) ± 20 mA
DC Output Current, per pin (I
OUT
) ± 25 mA
DC V
CC
or GND Current, per pin (ICC) ± 50 mA
Storage Temperature R ange (T
STG
) − 65°C to + 150°C
Power Dissipation (P
D
)
(Note 4) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 second s) 260°C
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage 0 V
CC
V
(V
IN
, V
OUT
)
Operating Temperature Range (T
A
) −40 +85 °C
Input Rise or Fall Times
(t
r
, tf) VCC = 2.0V 1000 ns
V
CC
= 4.5V 500 ns
V
CC
= 6.0V 400 ns
Symbol Parameter Conditions
V
CC
TA = 25°CTA = −40 to 85°C
Units
Typ Guar anteed Limits
V
IH
Minimum HIGH Level 2.0V 1.5 1.5 V
Input Voltage 4.5V 3.15 3.15 V
6.0V 4.2 4.2 V
V
IL
Maximum LOW Level 2.0V 0.5 0.5 V
Input Voltage 4.5V 1.35 1.35 V
6.0V 1.8 1.8 V
V
OH
Minimum HIGH Level VIN = VIH or VIL
Output Voltage | I
OUT
| ≤ 20 µA 2.0V 2.0 1.9 1.9 V
4.5V 4.5 4.4 4.4 V
6.0V 6.0 5.9 5.9 V
VIN = VIH or V
IL
|I
OUT
| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 V
| I
OUT
| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 V
V
OL
Maximum LOW Level VIN = VIH or VIL
Output Voltage | I
OUT
| ≤ 20 µA 2.0V 0 0.1 0 .1 V
4.5V 0 0.1 0.1 V
6.0V 0 0.1 0.1 V
VIN = VIH or VIL
| I
OUT
| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 V
| I
OUT
| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 V
I
IN
Maximum Input VIN = VCC or GND 6.0V ±0.1 ±1.0 µA
Current
I
CC
Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 µA
Supply Current I
OUT
= 0 µA
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MM74HC138
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Note 6: CPD determines the no lo ad dynamic power con s um ption, PD = CPD V
CC
2
f + ICC VCC, and the no load dynam ic c urrent consumption ,
I
S
= CPDVCCf + ICC.
Symbol Parameter Conditions Typ
Guaranteed
Units
Limit
t
PLH
Maximum Propagation 18 25 ns
Delay, Binary Select to any Output
t
PHL
Maximum Propagation 28 35 ns
Delay, Binary Select to any Output
t
PHL
, t
PLH
Maximum Propagation 18 25 ns
Delay, G1 to any Output
t
PHL
Maximum Propagation 23 30 ns
Delay G2A or G2B to
Output
t
PLH
Maximum Propagation 18 25 ns
Delay G2A or G2B to Output
Symbol Parameter Conditions
V
CC
TA= 25°CT
A
= −40 to 85°C
Units
Typ Guaranteed Limits
t
PLH
Maximum Propagation 2.0V 75 150 189 ns
Delay Binary Select to 4.5V 15 30 38 ns
any Output LOW-to-HIGH 6.0V 13 26 32 ns
t
PHL
Maximum Propagation 2.0V 100 200 252 ns
Delay Binary Select to any 4.5V 20 40 50 ns
Output HIGH-to-LOW 6.0V 17 34 43 ns
t
PHL
, t
PLH
Maximum Propagation 2.0V 75 150 189 ns
Delay G1 to any 4.5V 15 30 38 ns
Output 6.0V 13 26 32 ns
t
PHL
Maximum Propagation 2.0V 82 175 221 ns
Delay G2A or G2B to
4.5V 28 35 44 ns
Output 6.0V 22 30 37 ns
t
PLH
Maximum Propagation 2.0V 75 150 189 ns
Delay G2A or G2B to
4.5V 15 30 38 ns
Output 6.0V 13 26 32 ns
t
TLH
, t
THL
Output Rise and 2.0V 30 75 95 ns
Fall Time 4.5V 8 15 19 ns
6.0V 7 13 16 ns
C
IN
Maximum Input 3 10 10 pF
Capacitance
C
PD
Power Dissipation (Note 6) 75 pF
Capacitance
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MM74HC138
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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MM74HC138
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
MM74HC138 3-to-8 Line Decoder
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re asonably expected to result in a significant injury to the
user.
2. A critical componen t in any com ponen t of a life supp ort
device or system whose failu re to perform can b e reasonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N16E
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