Datasheet MM74C906MX, MM74C906M, MM74C906N Datasheet (Fairchild Semiconductor)

October 1987
Revised January 1999

MM74C906 • MM74C907 Hex Open Drain N-Channel Buffers • Hex Open Drain P-Channel Buffers

© 1999 Fairchild Semiconductor Corporation DS005911.prf www.fairchildsemi.com

MM74C906 • MM74C907
Hex Open Drain N-Channel Buffers •

Hex Open Drain P-Channel Buffers

General Description

The MM74C906 and MM74C907 buffers employ monolithic
CMOS technology in achieving open drain outputs. The
MM74C906 consists of six inverters driving six N-ch annel
devices; and the MM74C907 consists of six inverters dr iv­ing six P-channel devices. The open drain feature of these
buffers makes level shifting or wire AND and wire OR func­tions by just the addition of pull-up or pull-down re sistors.

All inputs are protected from static discharge by diode
clamps to V

CC

and to ground.

Features

■ Wide supply voltage range: 3V to 15V

■ Guaranteed noise margin: 1V

■ High noise immunity: 0.45 V

CC

(typ.)

■ High current sourcing and sinking open drain outputs

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Top View

Logic Diagrams

MM74C906

MM74C907

Order Number Package Number Package Description

MM74C906M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C906N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C907N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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MM74C906 • MM74C907

Absolute Maximum Ratings(Note 1)

Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the

safety of the device cannot be guaranteed. Ex ce pt for “Operating Tempera­ture Range” they are not mean t to imply that the devices sho uld be oper­ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device op eration.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Voltage at Any Input Pin −0.3V to VCC +0.3V
Voltage at Any Output Pin
Operating Temperature Range

MM74C906/MM74C907 −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Power Dissipation

Dual-In-Line 700 mW

Small Outline 500 mW

Operating V

CC

Range 3V to 15V

Absolute Maximum V

CC

18V

Lead Temperature (T

L

)

(Soldering, 10 seconds) 260°C

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical “1” Input Voltage VCC = 5V 3.5 V

VCC = 10V 8.0 V

V

IN(0)

Logical “0” Input Voltage VCC = 5V 1.5 V

VCC = 10V 2 V

I

IN(1)

Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1 µA

I

IN(0)

Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA

I

CC

Supply Current VCC = 15V, Output Open 0.05 15 µA
Output Leakage

MM74C906 VCC = 4.75V, VIN = VCC − 1.5V 0.005 5 µA

VCC = 4.75V, V

OUT

= 18V

MM74C907 VCC = 4.75V, VIN = 1V + 0.1 V

CC

0.005 5 µA

VCC = 4.75V, V

OUT

= VCC −18V

CMOS/LPTTL INTERFA CE

V

IN(1)

Logical “1” Input Voltage VCC = 4.75V VCC − 1.5V V

V

IN(0)

Logical “0” Input Voltage VCC = 4.75V 0.8 V

OUTPUT DRIVE CURRENT

MM74C906 VCC = 4.75V, VIN = 1V +0.1 V

CC

VCC = 4.75V, V

OUT

= 0.5V 2.1 8.0 mA

VCC = 4.75V, V

OUT

= 1.0V 4.2 12.0 mA

MM74C907 VCC = 4.75V, VIN = VCC −1.5V

VCC = 4.75V, V

OUT

= VCC − 0.5V −1.05 −1.5 mA

VCC = 4.75V, V

OUT

= VCC − 1V −2.1 −3.0 mA

MM74C906 VCC = 10V, VIN = 2V

VCC = 10V, V

OUT

= 0.5V 4.2 −20 mA

VCC = 10V, V

OUT

= 1V 8.4 −30 mA

MM74C907 VCC = 10V, VIN = 8V

VCC = 10V, V

OUT

= 9.5V −2.1 −4.0 mA

VCC = 10V, V

OUT

= 9V −4.2 −8.0 mA

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MM74C906 • MM74C907

AC Electrical Characteristics (Note 2)

T

A

= 25°C, C

L

= 50 pF, unless otherwise specified

Note 2: AC Parameters are guaranteed by DC correlated testing.
Note 3: “C” used in calcu lating propagation inc ludes output load capacity (C

L

) plus device output capacity (C

OUT

).

Note 4: Capacitance is guaranteed by periodic testing.
Note 5: C

PD

determines th e no load AC power con sumption of any CMOS device. For comp lete explanatio n see Family Characte ristics App lication No te,

AN-90. (Assumes ou t puts are open).

Typical Applications

Wire OR Gate

Note: Can be extended to more t han 2 inputs.

Wire AND Gate

Note: Can be extended to more than 2 inputs.

CMOS or TTL to PMOS Interface

Note: VCC + VDD ≤ 18V

V

CC

≤ 15V

CMOS or TTL to CMOS at a Higher V

CC

Symbol Parameter Conditions Min Typ Max Units

t

pd

Propagation Delay Time

to a Logical “0”

MM74C906 VCC = 5.0V, R = 10k 150 ns

VCC =10V, R = 10k 75 ns

MM74C907 VCC = 5.0V (Note 3) 150 + 0.7 RC ns

VCC = 10V (Note 3) 75 + 0.7 RC ns

t

pd

Propagation Delay Time
to a Logical “1”

MM74C906 VCC = 5.0V (Note 3) 150 + 0.7 RC ns

VCC = 10V (Note 3) 75 + 0.7 RC ns

MM74C907 VCC = 5.0V, R = 10k 150 ns

VCC = 10V, R = 10k 75 ns

C

IN

Input Capacitance (Note 4) 5.0 pF

C

OUT

Output Capacity (Note 4) 20 pF

C

PD

Power Dissipation Capacity (Note 5) Per Buffer 30 pF

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MM74C906 • MM74C907

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

Package Number M14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are impli ed and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

MM74C906 • MM74C907 Hex Open Drain N-Channel Buffers • Hex Open Drain P-Channel Buffers

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injur y to the
user.

2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r ea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A