Datasheet MM74C74MX, MM74C74M, MM74C74N Datasheet (Fairchild Semiconductor)

October 1987
Revised January 1999

MM74C74 Dual D-Type Flip-Flop

© 1999 Fairchild Semiconductor Corporation DS005885.prf www.fairchildsemi.com

MM74C74
Dual D-Type Flip-Flop

General Description

The MM74C74 dual D- type fli p-f lop i s a m on ol ithic comple­mentary MOS (CMOS ) integrated circuit constructed w ith
N- and P-channel enhancement transisto rs. Each flip-flop
has independent data, preset, clear and clock inputs and Q
and Q

outputs. The logic level pres ent at the data input is
transferred to the output during the positive going transition
of the clock pulse. Preset or clear is independent of the
clock an d acc om pl i s hed by a low l evel at t he pr e set or c lea r
input.

Features

■ Supply voltage range: 3V to 15V

■ Tenth power TTL compatible: Drive 2 LPT

2

L loads

■ High noise immunity: 0.45 V

CC

(typ.)

■ Low power: 50 nW (typ.)

■ Medium speed operation: 10 MHz (typ.) with 10V

supply

Applications

• Automotive

• Data terminals

• Instrumentation

• Medical electronics

• Alarm system

• Industrial electronics

• Remote metering

• Computers

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Note: A logic “0” on clear s et s Q t o logic “0”.

A logic “0” on preset se ts Q to logic “1”.

Top View

Truth Table

Note 1: No change in output from previous state.

Order Number Package Number Package Description

MM74C74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Preset Clear Q

n

Q

n

0000
0110
1001
11Q

n

(Note 1) Qn (Note 1)

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MM74C74

Logic Diagram

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MM74C74

Absolute Maximum Ratings(Note 2)

Note 2: “Absolute Maximum Rat ings” are tho se values beyond which the

safety of the device cannot be guaranteed. Exc ept for “ Operating Tempera­ture Range” they are not mea nt to imply that the devices sh ould be oper­ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device o peration.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Voltage at Any Pin (Note 2) −0.3V to VCC +0.3V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Power Dissipation

Dual-In-Line 700 mW
Small Outline 500 mW

Lead Temperature

(Soldering, 10 seconds ) 260°C

Operating V

CC

Range 3V to 15V

V

CC

(Max) 18V

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical “1” Input Voltage VCC = 5V 3.5 V

VCC = 10V 80 V

V

IN(0)

Logical “0” Input Voltage VCC = 5V 1.5 V

VCC = 10V 2.0 V

V

OUT(1)

Logical “1” Output Voltage VCC = 5V 4.5 V

VCC = 10V 9.0 V

V

OUT(0)

Logical “0” Output Voltage VCC = 5V 0.5 V

VCC = 10V 1.0 V

I

IN(1)

Logical “1” Input Current VCC = 15V 1.0 µA

I

IN(0)

Logical “0” Input Current VCC = 15V −1.0 µA

I

CC

Supply Current VCC = 15V 0.05 60 µA

CMOS/LPTTL INTERFACE

V

IN(1)

Logical “1” Input Voltage VCC = 4.75V VCC−1.5

V

IN(0)

Logical “0” Input Voltage VCC = 4.75V 0.8 V

V

OUT(1)

Logical “1” Output Voltage VCC = 4.75V, ID = −360 µA2.4 V

V

OUT(0)

Logical “0” Output Voltage VCC = 4.75V, ID = 360 µA0.4V

OUTPUT DRIVE (See Family Characteristics Data Sheet)

I

SOURCE

Output Source Current VCC = 5V, V

IN(0)

= 0V −1.75 mA

TA = 25°C, V

OUT

= 0V

I

SOURCE

Output Source Current VCC = 10V, V

IN(0)

= 0V −8.0 mA

TA = 25°C, V

OUT

= 0V

I

SINK

Output Sink Current VCC = 5V, V

IN(1)

= 5V 1.75 mA

TA = 25°C, V

OUT

= V

CC

I

SINK

Output Sink Current VCC = 10V, V

IN(1)

= 10V 8.0 mA

TA = 25°C, V

OUT

= V

CC

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MM74C74

AC Electrical Charac teristics (Note 3)

TA = 25°C, CL = 50 pF, unless otherwise noted

Note 3: AC Parameters are guara nt eed by DC correlated testin g.
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: C

PD

determines t he no loa d AC power c ons um ption of a ny CM OS d evice. For com plet e expla natio n se e Family Cha ract eris tics Appl icat ion Note—

AN-90.

Typical Applications

Ripple Counter (Divide by 2n)

Shift Register

74C Compatibility

Guarantee d Noise Margin as a Function of V

CC

Symbol Parameter Conditions Min Typ Max Units

C

IN

Input Capacitance Any Input (Note 4) 5.0 pF

t

pd

Propagation Delay Time to a VCC = 5V 180 300 ns

Logical “0” t

pd0

or Logical “1” VCC = 10V 70 110 ns

t

pd1

from Clock to Q or Q

t

pd

Propagation Delay Time to a VCC = 5V 180 300 ns
Logical “0” from Preset or Clear VCC = 10V 70 110 ns

t

pd

Propagation Delay Time to a VCC = 5V 250 400 ns
Logical “1” from Preset or Clear VCC = 10V 100 150 ns

tS0, t

S1

Time Prior to Clock Pulse that VCC = 5V 100 50 ns
Data Must be Present t

SETUP

VCC = 10V 40 20 ns

tH0, t

H1

Time after Clock Pulse that VCC = 5V −20 0 ns
Data Must be Held VCC = 10V −8.0 0 ns

t

PW1

Minimum Clock Pulse VCC = 5V 100 250 ns
Width (tWL = tWH)V

CC

= 10V 40 100 ns

t

PW2

Minimum Preset and VCC = 5V 100 160 ns
Clear Pulse Width VCC = 10V 40 70 ns

tr, t

f

Maximum Clock Rise VCC = 5V 15.0 µs
and Fall Time VCC = 10V 5.0 µs

f

MAX

Maximum Clock Frequency VCC = 5V 2.0 3.5 MHz

VCC = 10V 5.0 8.0 MHz

C

PD

Power Dissipation Capacitance (Note 5) 40 pF

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MM74C74

Switching Time Waveform

CMOS to CMOS

tr = tf = 20 ns

AC Test Circuit

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MM74C74

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

Package Number M14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

MM74C74 Dual D-Type Flip-Flop

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s a re devices or syste ms

which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injur y to the
user.

2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r ea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A