Datasheet MM74C74 Datasheet (Fairchild)

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MM74C74 Dual D-Type Flip-Flop

October 1987 Revised January 1999

General Description

The MM74C74 dual D- type fli p-f lop i s a m on ol ithi c co mp lementary MOS (C MOS) integrated circuit constructe d with N- and P-channel enhancement transisto rs. Each flip-flop has independent data, preset, clear and clock inputs and Q

outputs. The logic l evel present at the data input i s

and Q transferred to the output during the positive going transition of the clock pulse. Preset or clear is independent of the clock an d acc om pl i s he d b y a l o w l e vel at the pr e s et or cl ea r input.

Features

■ Supply voltage range: 3V to 15V

■ Tenth power TTL compatible: Drive 2 LPT

L loads

■ High noise immunity: 0.45 V

■ Low power: 50 nW (typ.)

■ Medium speed operation: 10 MHz (typ.) with 10V

supply

Applications

• Automotive

• Data terminals

• Instrumentation

• Medical electronics

• Alarm system

• Industrial electronics

• Remote metering

• Computers

(typ.)

Ordering Code:

Order Number Package Number Package Description

MM74C74M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow MM74C74N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.

Connection Diagram

Pin Assignments for DIP and SO IC

Truth Table

Preset Clear Q

0000 0110 1001 11Q

Note 1: No change in output from previous state.

(Note 1) Qn (Note 1)

Note: A logic “0” on clear s et s Q t o logic “0”.

A logic “0” on preset se ts Q to logic “1”.

Top View

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Logic Diagram

MM74C74

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Absolute Maximum Ratings(Note 2)

Voltage at Any Pin (Note 2) −0.3V to VCC +0.3V Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Power Dissipation

Dual-In-Line 700 mW Small Outline 500 mW

Lead Temperature

(Soldering, 10 seconds ) 260°C

Operating V

(Max) 18V

Range 3V to 15V

Note 2: “Absolute Maximum Rat ings” are tho se values beyond which the safety of the device cannot be guaranteed. E x c ept for “ Operating Temperature Range” they are not mea nt to imply that the devices sh ould be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device o peration.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

IN(1)

IN(0)

OUT(1)

OUT(0)

IN(1)

IN(0)

CMOS/LPTTL INTERFACE

IN(1)

IN(0)

OUT(1)

OUT(0)

OUTPUT DRIVE (See Family Characteristics Data Sheet)

SOURCE

SINK

Logical “1” Input Voltage VCC = 5V 3.5 V

VCC = 10V 80 V

Logical “0” Input Voltage VCC = 5V 1.5 V

VCC = 10V 2.0 V

Logical “1” Output Voltage VCC = 5V 4.5 V

VCC = 10V 9.0 V

Logical “0” Output Voltage VCC = 5V 0.5 V

VCC = 10V 1.0 V Logical “1” Input Current VCC = 15V 1.0 µA Logical “0” Input Current VCC = 15V −1.0 µA Supply Current VCC = 15V 0.05 60 µA

Logical “1” Input Voltage VCC = 4.75V VCC−1.5 Logical “0” Input Voltage VCC = 4.75V 0.8 V Logical “1” Output Voltage VCC = 4.75V, ID = −360 µA2.4 V Logical “0” Output Voltage VCC = 4.75V, ID = 360 µA0.4V

Output Source Current VCC = 5V, V

TA = 25°C, V Output Source Current VCC = 10V, V

TA = 25°C, V Output Sink Current VCC = 5V, V

TA = 25°C, V Output Sink Current VCC = 10V, V

TA = 25°C, V

= 0V −1.75 mA

IN(0)

= 0V

OUT

= 0V −8.0 mA

IN(0)

= 0V

OUT

= 5V 1.75 mA

IN(1)

= V

OUT

= 10V 8.0 mA

IN(1)

= V

OUT

MM74C74

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AC Electrical Charac teristics (Note 3)

TA = 25°C, CL = 50 pF, unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

MM74C74

Input Capacitance Any Input (Note 4) 5.0 pF Propagation Delay Time to a VCC = 5V 180 300 ns

Logical “0” t t

pd1

or Logical “1” VCC = 10V 70 110 ns

pd0

from Clock to Q or Q Propagation Delay Time to a VCC = 5V 180 300 ns Logical “0” from Preset or Clear VCC = 10V 70 110 ns

Propagation Delay Time to a VCC = 5V 250 400 ns Logical “1” from Preset or Clear VCC = 10V 100 150 ns

tS0, t

tH0, t

Time Prior to Clock Pulse that VCC = 5V 100 50 ns Data Must be Present t

SETUP

VCC = 10V 40 20 ns Time after Clock Pulse that VCC = 5V −20 0 ns Data Must be Held VCC = 10V −8.0 0 ns

PW1

PW2

Minimum Clock Pulse VCC = 5V 100 250 ns Width (tWL = tWH)V

= 10V 40 100 ns

Minimum Preset and VCC = 5V 100 160 ns Clear Pulse Width VCC = 10V 40 70 ns

tr, t

Maximum Clock Rise VCC = 5V 15.0 µs and Fall Time VCC = 10V 5.0 µs

MAX

Maximum Clock Frequency VCC = 5V 2.0 3.5 MHz

VCC = 10V 5.0 8.0 MHz

Note 3: AC Parameters are guara nt eed by DC correlated testing. Note 4: Capacitance is guaranteed by periodic testing. Note 5: C

AN-90.

Power Dissipation Capacitance (Note 5) 40 pF

determines t he no loa d AC power c ons um ption of a ny CM OS d evice. For com plet e expla natio n se e Family Cha ract eris tics Appl icat ion No te—

Typical Applications

Ripple Counter (Divide by 2n)

Shift Register

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74C Compatibility

Guaranteed Noise Margin as a Function of V

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Switching Time Waveform

MM74C74

CMOS to CMOS

tr = tf = 20 ns

AC Test Circuit

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Physical Dimensions in ches (millimeters) unless otherwise noted

MM74C74

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

Package Number M14A

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

MM74C74 Dual D-Type Flip-Flop

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s a re devices or syste ms which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injur y to the user.

Package Number N14A

2. A critical comp onent in any com ponent of a l ife support device or system whose failure to perform can be reasonably expected to cause the failure of the life suppor t device or system, or to affect its safety or effectiveness.

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Fairchild does not assume any responsibility for use of any circuitry described, no circui t patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.