Datasheet MM74C373WM, MM74C373WMX, MM74C373N Datasheet (Fairchild Semiconductor)

October 1987
Revised January 1999

MM74C373 • MM74C374 3-STATE Octal D-T ype Latch • 3-STATE Octal D-Type Flip-Flop

© 1999 Fairchild Semiconductor Corporation DS005906.prf www.fairchildsemi.com

MM74C373 • MM74C374
3-STATE Octal D-Type Latch •

3-STATE Octal D-Type Flip-Flop

General Description

The MM74C373 and MM74C374 are integrated, comple­mentary MOS (CMOS), 8-bit storage elements with 3­STATE outputs. These outputs have been specially
designed to drive high capaci tive loads, such as on e might
find when driving a bus, and to have a fan out of 1 when
driving standard TT L. When a high log ic level is applied to
the OUTPUT DISABLE input, all outputs go to a high
impedance state, regardless of what signal s are prese nt at
the other inputs and the state of the storage elements.

The MM74C373 is an 8-bit latch. When LATCH

ENABLE is
high, the Q outputs will follow the D inputs. When LATCH
ENABLE goes low, data at the D inputs, which meets the
set-up and hold time requirements, will be retained at the
outputs until LATCH

ENABLE returns high again.

The MM74C374 is an 8-bit, D-type, positive-edge triggered
flip-flop. Data at the D input s, meeting the set-up and hold
time requirements, is transferred to the Q outputs on posi­tive-going transitions of the CLOCK input.

Both the MM74C373 and the MM74C374 are being assem-

bled in 20-pin dual-in-l ine packages with 0.300” pin cen­ters.

Features

■ Wide supply voltage range: 3V to 15V

■ High noise immunity: 0.45 V

CC

(typ.)

■ Low power consumption

■ TTL compatibility:

Fan out of 1driving standard TTL

■ Bus driving capability

■ 3-STATE outputs

■ Eight storage elements in one package

■ Single CLOCK/LATCH

ENABLE and OUTPUT DIS-

ABLE control inputs

■ 20-pin dual-in-line package with 0.300” centers takes
half the board space of a 24-pin package

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to t he ordering code.

Order Number Package Number Package Description

MM74C373M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74C373N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C374M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
MM74C374N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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MM74C373 • MM74C374

Connection Diagrams

Pin Assignments for DIP and SOIC

MM74C373

Top View

MM74C374

Top View

Truth Tables

MM74C373 MM74C374

L = LOW logic level
H = HIGH logic level
X = Irrelevant



= LOW-to-HIGH logic level transition
Q = Preexisting output level
Hi-Z = High impedance output state

Output LATCH DQ

Disable ENABLE

LHHH
LHLL
LLXQ
H X X Hi-Z

Output Clock D Q

Disable

L



HH

L



LL
LLXQ
LHXQ
H X X Hi-Z

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MM74C373 • MM74C374

Block Diagrams

MM74C373 (1 of 8 Latches)

MM74C374 (1 of 8 Flip-Flops)

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MM74C373 • MM74C374

Absolute Maximum Ratings(Note 1)

Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the

safety of the device cannot be guaranteed. Ex ce pt for “O perating Tempera­ture Range” they are not mean t to imply that the devices sho uld be oper­ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device op eration.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Note 2: These are peak output current capabilities. Continuous output current is rated at 12 mA max.

Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range (T

A

)

MM74C373 −40°C to +85°C

Storage Temperature Range (T

S

) −65°C to +150°C

Power Dissipation

Dual-In-Line 700 mW
Small Outline 500 mW

Operating V

CC

Range 3V to 15V

Absolute Maximum V

CC

18V

Lead Temperature (T

L

)

(Soldering, 10 seconds) 260°C

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical “1” Input Voltage VCC = 5V 3.5 V

VCC = 10V 8.0 V

V

IN(0)

Logical “0” Input Voltage VCC = 5V 1.5 V

VCC = 10V 2.0 V

V

OUT(1)

Logical “1” Output Voltage VCC = 5V, IO = −10 µA4.5 V

VCC = 10V, IO = −10 µA9.0 V

V

OUT(0)

Logical “0” Output Voltage VCC = 5V, IO = 10 µA0.5V

VCC = 10V, IO = 10 µA1.0V

I

IN(1)

Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA

I

IN(0)

Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA

I

OZ

3-STATE Leakage Current VCC = 15V, VO = 15V 0.005 1.0 µA

VCC = 15V, VO = 0V −1.0 −0.005 µA

I

CC

Supply Current VCC = 15V 0.05 300 µA

CMOS/LPTTL INTERFA CE

V

IN(1)

Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V

V

IN(0)

Logical “0” Input Voltage VCC = 4.75V 0.8 V

V

OUT(1)

Logical “1” Output Voltage VCC = 4.75V, IO = −360 µAV

CC

− 0.4 V

VCC = 4.75V, IO = −1.6 mA 2.4 V

V

OUT(0)

Logical “0” Output Voltage VCC = 4.75V, IO = 1.6 mA 0.4 V

OUTPUT DRIVE (Short Circuit Current)

I

SOURCE

Output Source Current VCC = 5V, V

OUT

= 0V −12 −24 mA

TA = 25°C (Note 2)

I

SOURCE

Output Source Current VCC = 10V, V

OUT

= 0V −24 −48 mA

TA = 25°C (Note 2)

I

SINK

Output Sink Current VCC = 5V, V

OUT

= V

CC

612 mA

(N-Channel) TA = 25°C (Note 2)

I

SINK

Output Sink Current VCC = 10V, V

OUT

= V

CC

24 48 mA

(N-Channel) TA = 25°C (Note 2)

5 www.fairchildsemi.com

MM74C373 • MM74C374

AC Electrical Characteristics (Note 3)

MM74C373, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted

Note 3: AC Parameters are guaranteed by DC correlated testing.
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: C

PD

determines th e no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note

AN-90.

Symbol Parameter Conditions Min Typ Max Units

t

pd0

, t

pd1

Propagation Delay, VCC = 5V, CL = 50 pF 165 330 ns
LATCH ENABLE to Output

VCC = 10V, CL = 50 pF 70 140 ns
VCC = 5V, CL = 150 pF 195 390 ns
VCC = 10V, CL = 150 pF 85 170 ns

t

pd0

, t

pd1

Propagation Delay Data

LATCH ENABLE = V

CC

In to Output VCC = 5V, CL = 50 pF 155 310 ns

VCC = 10V, CL = 50 pF 70 140 ns
VCC = 5V, CL = 150 pF 185 370 ns
VCC = 10V, CL = 150 pF 85 170 ns

t

SET-UP

Minimum Set-Up Time Data In t

HOLD

= 0 ns

to CLOCK/LATCH ENABLE

VCC = 5V 70 140 ns
VCC = 10V 35 70 ns

f

MAX

Maximum LATCH ENABLE
Frequency VCC = 5V 3.5 6.7 MHz

VCC = 10V 4.5 9.0 MHz

t

PWH

Minimum LATCH ENABLE

VCC 5V 75 150 ns

Pulse Width VCC = 10V 55 110 ns

tr, t

f

Maximum LATCH ENABLE

VCC = 5V NA µs

Rise and Fall Time VCC = 10V NA µs

t1H, t

0H

Propagation Delay OUTPUT RL = 10k, CL = 5 pF
DISABLE to High Impedance VCC = 5V 105 210 ns
State (from a Logic Level) VCC = 10V 60 120 ns

tH1, t

H0

Propagation Delay OUTPUT RL = 10k, CL = 50 pF
DISABLE to Logic Level VCC = 5V 105 210 ns
(from High Impedance State) VCC = 10V 45 90 ns

t

THL

, t

TLH

Transition Time VCC = 5V, CL = 50 pF 65 130 ns

VCC = 10V, CL = 50 pF 35 70 ns
VCC = 5V, CL = 150 pF 110 220 ns
VCC = 10V, CL = 150 pF 70 140 ns

C

LE

Input Capacitance

LE Input (Note 4)

7.5 10 pF

C

OD

Input Capacitance OUTPUT DISABLE 7.5 10 pF

Input (Note 4)

C

IN

Input Capacitance Any Other Input (Note 4) 5 7.5 pF

C

OUT

Output Capacitance High Impedance 10 15 pF

State (Note 4)

C

PD

Power Dissipation Capacitance Per Package (Note 5) 200 pF

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MM74C373 • MM74C374

AC Electrical Charac teristics (Note 6)

MM74C374, TA = 25°C, CL = 50 pF, tr = tf = 20 ns, unless otherwise noted

Note 6: AC Parameters are guara nt eed by DC correlated testing.
Note 7: Capacitance is guaranteed by periodic testing.
Note 8: C

PD

determines the no load AC power consumption of any C M OS device. For complete explanation se e Family Characteristics Applic ation Note

AN-90.

Symbol Parameter Conditions Min Typ Max Units

t

pd0

, t

pd1

Propagation Delay, VCC = 5V, CL = 50 pF 150 300 ns
CLOCK to Output VCC = 10V, CL = 50 pF 65 130 ns

VCC = 5V, CL = 150 pF 180 360 ns
VCC = 10V, CL = 150 pF 80 160 ns

t

SET-UP

Minimum Set-Up Time Data In t

HOLD

= 0 ns

to CLOCK/LATCH ENABLE

VCC = 5V 70 140 ns
VCC = 10V 35 70 ns

t

PWH

, t

PWL

Minimum CLOCK Pulse Width VCC = 5V 70 140 ns

VCC = 10V 50 100 ns

f

MAX

Maximum CLOCK Frequency VCC = 5V 3.5 7.0 MHz

VCC = 10V 5 10 MHz

t1H, t

0H

Propagation Delay OUTPUT RL = 10k, CL = 50 pF
DISABLE to High Impedance VCC = 5V 105 210 ns
State (from a Logic Level) VCC = 10V 60 120 ns

tH1, t

H0

Propagation Delay OUTPUT RL = 10k, CL = 50 pF
DISABLE to Logic Level VCC = 5V 105 210 ns
(from High Impedance State) VCC = 10V 45 90 ns

t

THL

, t

TLH

Transition Time VCC = 5V, CL = 50 pF 65 130 ns

VCC = 10V, CL = 50 pF 35 70 ns
VCC = 5V, CL = 150 pF 110 220 ns
VCC = 10V, CL = 150 pF 70 140 ns

tr, t

f

Maximum CLOCK Rise VCC = 5V 15 >2000 µs
and Fall Time VCC = 10V 5 >2000 µs

C

CLK

Input Capacitance CLOCK Input (Note 7) 7.5 10 pF

C

OD

Input Capacitance OUTPUT DISABLE 7.5 10 pF

Input (Note 7)

C

IN

Input Capacitance Any Other Input (Note 7) 5 7.5 pF

C

OUT

Output Capacitance High Impedance 10 15 pF

State (Note 7)

C

PD

Power Dissipation Capacitance Per Package (Note 8) 250 pF

7 www.fairchildsemi.com

MM74C373 • MM74C374

Typical Performance Charact eristics

MM74C373

Propagation Delay, LATCH ENABLE

to Output vs

Load Capacitance

MM74C373

Propagation Delay, Data In to Output

vs Load Capacitance

MM74C373

Propagation Delay, CLOCK to Output

vs Load Capacitance

MM74C373, MM74C374

Change in Propagation Delay

per pF of Load Capacitance

(∆t

PD

/pF) vs Power Supply Voltage

MM74C373, MM74C374

Output Sink Current vs V

OUT

MM74C373, MM74C374

Source Current vs V

CC

− V

OUT

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MM74C373 • MM74C374

Typical Applications

Data Bus Interfacing Element

Simple, Latching, Octal, LED Indicator

Driver with Blanking for Use as Data Display,

Bus Monitor, µP Front Panel Display, Etc.

3-STATE Test Circuits and Switching Time Waveforms

t1H, t

H1

t1H, CL = 5 pF

t

H1

, CL = 50 pF

t

0H

, tH0

t

0H

, CL = 5 pF

t

H0

, CL = 50 pF

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MM74C373 • MM74C374

Switching Time Waveforms

MM74C373

Output Disable = GND

MM74C374

Output Disable = GND

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MM74C373 • MM74C374

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013. 0.300” Wide

Package Number M20B

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

MM74C373 • MM74C374 3-STATE Octal D-Type Latch • 3-STATE Octal D-Type Flip-Flop

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s a re devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injur y to the
user.

2. A critical compon ent in any com ponent of a li fe support
device or system whose failure to p erform can be r ea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A