Datasheet MM74C32N, MM74C32MX, MM74C32M Datasheet (Fairchild Semiconductor)

October 1987
Revised January 1999

MM74C32 Quad 2-Input OR Gate

© 1999 Fairchild Semiconductor Corporation DS005881.prf www.fairchildsemi.com

MM74C32
Quad 2-Input OR Gate

General Description

The MM74C32 employs complementary MOS (CMOS)
transistors to achieve low power and high noise margin,
these gates provide the ba sic functions us ed in the imple­mentation of digital integrated circuit systems. The N- and
P-channel enhancemen t mode transistors provide a sym ­metrical circuit with output swings essentially equal to the
supply voltage. This results in high noise immunity over a
wide supply voltage ran ge. No DC power other than th at
caused by leakage current is c onsumed dur ing static co n-

ditions. All inputs are protected against static discharge
damage.

Features

■ Wide supply voltage range: 3.0V to 15V

■ Guaranteed noise margin: 1.0V

■ High noise immunity: 0.45V V

CC

(typ.)

■ Low power TTL compatibility: fan out of 2 driving 74L

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the or dering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Top View

Order Number Package Number Package Description

MM74C32M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C32N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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MM74C32

Absolute Maximum Ratings(Note 1)

Note 1: “Absolute Maxi mum Ratings” are those valu es beyond which the

safety of the device cannot be guaranteed. Exce pt for “O perating Tempera­ture Range” they are not mean t to imply that the devices sho uld be oper­ated at these limits. The Electrical Charact eristics table provides co nditions
for actual device operation.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

AC Electrical Charac teristics (Note 2)

TA = 25°C, CL = 50 pF, unless otherwise specified

Note 2: AC Parameters are guara nt eed by DC correlated testin g.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C

PD

determines t he no loa d AC power c ons um ption of a ny CM OS d evice. For com plet e expla natio n se e Family Cha ract eris tics Appl icat ion No te—

AN-90.

Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Power Dissipation (P

D

)
Dual-In-Line 700 mW
Small Outline 500 mW

Operating V

CC

Range 3.0V to 15V

Absolute Maximum V

CC

18V

Lead Temperature

(Soldering, 10 seconds) 260°C

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical “1” Input Voltage VCC = 5.0V 3.5 V

VCC = 10V 8.0 V

V

IN(0)

Logical “0” Input Voltage VCC = 5.0V 1.5 V

VCC = 10V 2.0 V

V

OUT(1)

Logical “1” Output Voltage VCC = 5.0V, IO = −10 µA4.5 V

VCC = 10V, IO = −10 µA9.0 V

V

OUT(0)

Logical “0” Output Voltage VCC = 5.0V, IO = 10 µA0.5V

VCC = 10V, IO = 10 µA1.0V

I

IN(1)

Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA

I

IN(0)

Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA

I

CC

Supply Current VCC = 15V 0.05 15 µA

CMOS/LPTTL INTERFACE

V

IN(1)

Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V

V

IN(0)

Logical “0” Input Voltage VCC = 4.75V 0.8 V

V

OUT(1)

Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V

V

OUT(0)

Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V

OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current)

I

SOURCE

Output Source Current VCC = 5.0V, V

OUT

= 0V −1.75 −3.3 mA

(P-Channel)

I

SOURCE

Output Source Current VCC = 10V, V

OUT

= 0V −8.0 −15 mA

(P-Channel)

I

SINK

Output Sink Current VCC = 5.0V, V

OUT

= V

CC

1.75 3.6 mA

(N-Channel)

I

SINK

Output Sink Current VCC = 10V, V

OUT

= V

CC

8.0 16 mA

(N-Channel)

Symbol Parameter Conditions Min Typ Max Units

t

pd

Propagation Delay Time to VCC = 5.0V 80 150 ns
Logical “1” or “0” VCC = 10V 35 70 ns

C

IN

Input Capacitance Any Input (Note 3) 5 pF

C

PD

Power Dissipation Capacitance Per Gate (Note 4) 15 pF

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MM74C32

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

Package Number M14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

MM74C32 Quad 2-Input OR Gate

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injury to the
user.

2. A critical component in any c omponent of a life suppor t
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N14A