Datasheet MM74C193MX, MM74C193N, MM74C193M Datasheet (Fairchild Semiconductor)

© 1999 Fairchild Semiconductor Corporation DS005901 www.fairchildsemi.com

January 1991
Revised October 1999

MM74C192 • MM74C193 Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary

Counter

MM74C192 • MM74C193
Synchronous 4-Bit Up/Down Decade Counter •

Synchronous 4-Bit Up/Down Binary Counter

General Description

The MM74C192 and MM74C193 up/down counters are
monolithic complementary MOS (CMOS) integrated cir­cuits. The MM74C192 is a BCD counter, while the
MM74C193 is a binary counter.

Counting up and counting do wn is pe rform ed by two cou nt
inputs, one being held hig h whil e the other is cloc ked. T he
outputs change on the positive-going transition of this
clock.

These counters feature preset inputs that are set when

load is a logical “0” and a clear which forces all outputs to
“0” when it is at a logical “1 ”. The counter s also have car ry
and borrow outputs so th at t hey c an be cascaded using no
external circuitry.

Features

■ High noise margin: 1V guaranteed

■ Tenth power TTL compati ble: Drive 2 LPTTL loads

■ Wide supply range: 3V to 15V

■ Carry and borrow outputs for N-bit cascading

■ Asynchronous clear

■ High noise immunity: 0.45 V

CC

(typ.)

Ordering Code:

Device also available in Tape and Reel. Specify by appending s uffix let te r “X” to the ordering code.

Connection Diagram

Top View

Order Number Package Number Package Description

MM74C192N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C193M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74C193N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

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MM74C192 • MM74C193

Absolute Maximum Ratings(Note 1)

Note 1: “Absolute Maximum Ratings” ar e those value s beyond which the

safety of the device cannot be guaranteed. Except for “Operating Tempera­ture Range” they are not m eant to i mply that t he devices should be oper­ated at these limits. The Electrical Charac te ris t ic s ta ble provides condition s
for actual device operation.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise noted

Voltage at Any Pin −0.3V to VCC + 0.3V
Operating Temperature Range (T

A

) −40°C to +85°C

Storage Temperature Range (T

S

) −65°C to +150°C

Maximum V

CC

Voltage 18V

Power Dissipation (P

D

)
Dual-In-Line 700 mW
Small Outline 500 mW

Operating V

CC

Range 3V to 15V

Lead Temperature (T

A

)
(Soldering, 10 seconds) 260°C

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical “1” Input Voltage VCC = 5V 3.5 V

V

CC

= 10V 8.0 V

V

IN(0)

Logical “0” Input Voltage VCC = 5V 1.5 V

VCC = 10V 2.0 V

V

OUT(1)

Logical “1” Output Voltage VCC = 5V, IO = −10 µA4.5 V

VCC = 10V, IO = −10 µA9.0 V

V

OUT(0)

Logical “0” Output Voltage VCC = 5V, IO = 10 µA0.5V

VCC = 10V, IO = 10 µA1.0V

I

IN(1)

Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA

I

IN(0)

Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA

I

CC

Supply Current VCC = 15V 0.05 300 µA

CMOS TO LPTTL INTERFACE

V

IN(1)

Logical “1” Input Voltage VCC = 4.75V VCC − 1.5 V

V

IN(0)

Logical “0” Input Voltage VCC = 4.75V 0.8 V

V

OUT(1)

Logical “1” Output Voltage VCC = 4.75V, IO = −100 µA2.4 V

V

OUT(0)

Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V

OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)

I

SOURCE

Output Source Current VCC = 5V, V

IN(0)

= 0V −1.75 mA

TA = 25°C, V

OUT

= 0V

I

SOURCE

Output Source Current VCC = 10V, V

IN(0)

= 0V −8mA

TA = 25°C, V

OUT

= 0V

I

SINK

Output Sink Current VCC = 5V, V

IN(1)

= 5V 1.75 mA

TA = 25°C, V

OUT

= V

CC

I

SINK

Output Sink Current VCC = 10V, V

IN(1)

= 10V 8 mA

TA = 25°C, V

OUT

= V

CC

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MM74C192 • MM74C193

AC Electrical Characteristics (Note 2)

T

A

= 25°C, CL = 50 pF, unless otherwise noted

Note 2: AC Parameters are guaranteed by DC c orrelated testing.
Note 3: Capacitance is guaranteed by periodic t es t ing.
Note 4: C

PD

determines the no load AC power consump t ion of any CMOS device. F or c omplete explanation, see Application No te AN -90.

Cascading Packages

Guaranteed Noise Margin

as a Function of V

CC

Symbol Parameter Conditions Min Typ Max Units

t

pd

Propagation Delay VCC = 5V 250 400 ns
Time to Q from Count Up or Down VCC = 10V 100 160 ns

t

pd

Propagation Delay VCC = 5V 120 200 ns
Time to Q Borrow from Count Down VCC = 10V 50 80 ns

t

pd

Propagation Delay VCC = 5V 120 200 ns
Time to Carry from Count Up VCC = 10V 50 80 ns

t

S

Time Prior to Load VCC = 5V 100 160 ns
that Data Must be Present V

CC

= 10V 30 50 ns

t

W

Minimum Clear Pulse Width VCC = 5V 300 480 ns

V

CC

= 10V 120 190 ns

t

W

Minimum Load Pulse Width VCC = 5V 100 160 ns

V

CC

= 10V 40 65 ns

t

pd0

Propagation Delay VCC = 5V 300 480 ns

t

pd1

Time to Q from Load VCC = 10V 120 190 ns

t

W

Minimum Count Pulse Width VCC = 5V 120 200 ns

VCC = 10V 35 80 ns

f

MAX

Maximum Count Frequency VCC = 5V 2.5 4 MHz

V

CC

= 10V 6 10 MHz

t

r

Count Rise and Fall Time VCC = 5V 15 µs

t

f

VCC = 10V 5 µs

C

IN

Input Capacitance (Note 3) 5 pF

C

PD

Power Dissipation Capacitance (Note 4) 100 pF

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MM74C192 • MM74C193

Timing Diagrams

MM74C192

Note A: Clear outputs to zero.

Note B: Load (preset) to binar y thirteen.
Note C: Count up to fourteen, fifteen, carry, zero, one and two.
Note D: Count down to one, zero, borrow, fifteen, fourteen, and thirteen.

MM74C193

Note A: Clear outputs to zero.

Note B: Load (preset) to BCD seven.
Note C: Count up to eight, nine, carry, zero, one, and two.
Note D: Count down to one, zero, borrow, nine, eight, and seven.
Note E: Clear overrides load, data, and count inputs.
Note F: When counting up, count down input must be HIGH; when counting down, count-up input must be HIGH.

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MM74C192 • MM74C193

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

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MM74C192 • MM74C193 Synchronous 4-Bit Up/Down Decade Counter • Synchronous 4-Bit Up/Down Binary

Counter

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit pate nt licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant inju ry to the
user.

2. A critical component i n any compon ent of a lif e support
device or system whose failu re to perform can be rea­sonably expected to ca use the fa i lure of the life su pp ort
device or system, or to affect its safety or effectiveness.

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