Datasheet MM74C174N, MM74C174M, MM74C174MX Datasheet (Fairchild Semiconductor)

October 1987
Revised January 1999

MM74C174 Hex D-Type Flip-Flop

© 1999 Fairchild Semiconductor Corporation DS005899.prf www.fairchildsemi.com

MM74C174
Hex D-Type Flip-Flop

General Description

The MM74C174 hex D-type flip-flop is a monolithic comple­mentary MOS (CMOS ) integrated circuit constructed w ith
N- and P-channel enhancement transistors. All have a
direct clear input. Inform ation at the D inpu ts meeting the
setup time requirements is transferred to the Q outp uts on
the positive-going edge of the clock pulse. Cle ar is inde­pendent of clock and accomplished by a low level at the
clear input. All inputs are prot ected by diodes to V

CC

and

GND.

Features

■ Wide supply voltage range: 3.0V to 15V

■ Guaranteed noise margin: 1.0V

■ High noise immunity: 0.45 V

CC

(typ.)

■ Low power TTL compatibility:
Fan out of 2 driving 74L

Ordering Code:

Device also available in Tape and Reel. Specify by appendin g s uf f ix let t er “X” to the ordering code.

Connection Diagram

Pin Assignments for DIP and SOIC

Top View

Truth Table

Order Number Package Number Package Description

MM74C174M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
MM74C174N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Inputs Output

Clear Clock D Q

LXXL
H ↑ HH
H ↑ LL
HLXQ

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MM74C174

Logic Diagrams

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MM74C174

Absolute Maximum Ratings(Note 1)

Note 1: “Absolute Maximum Rat ings” are tho se values beyond which the

safety of the device cannot be guaranteed. Ex c ept for “Operating Tempera­ture Range” they are not mea nt to imply that the devices sh ould be oper­ated at these limits. The Electrical Charac t eristics table provides c onditions
for actual device operation.

DC Electrical Characteristics

Min/Max limits apply across temperature range unless otherwise specified

Voltage at Any Pin −0.3V to VCC +0.3V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Power Dissipation (P

D

)
Dual-In-Line 700 mW
Small Outline 500 mW

Operating V

CC

Range 3.0V to 15V

Absolute Maximum V

CC

18V

Lead Temperature

(Soldering, 10 seconds) 260°C

Symbol Parameter Conditions Min Typ Max Units

CMOS TO CMOS

V

IN(1)

Logical “1” Input Voltage VCC = 5V 3.5 V

VCC = 10V 8.0 V

V

IN(0)

Logical “0” Input Voltage VCC = 5V 1.5 V

VCC = 10V 2.0 V

V

OUT(1)

Logical “1” Output Voltage VCC = 5V, IO = −10 µA4.5 V

VCC = 10V, IO = −10 µA9.0 V

V

OUT(0)

Logical “0” Output Voltage VCC = 5V, IO = 10 µA0.5V

VCC = 10V, IO = 10 µA1.0V

I

IN(1)

Logical “1” Input Current VCC = 15V, VIN = 15V 0.005 1.0 µA

I

IN(0)

Logical “0” Input Current VCC = 15V, VIN = 0V −1.0 −0.005 µA

I

CC

Supply Current VCC = 15V 0.05 300 µA

CMOS/LPTTL INTERFACE

V

IN(1)

Logical “1” Input Voltage VCC = 4.75V VCC−1.5 V

V

IN(0)

Logical “0” Input Voltage VCC = 4.75V 0.8 V

V

OUT(1)

Logical “1” Output Voltage VCC = 4.75V, IO = −360 µA2.4 V

V

OUT(0)

Logical “0” Output Voltage VCC = 4.75V, IO = 360 µA0.4V

OUTPUT DRIVE (See Family Characteristics Data Sheet) (short circuit current)

I

SOURCE

Output Source Current VCC = 5V −1.75 −3.3 mA
(P-Channel) TA = 25°C, V

OUT

= 0V

I

SOURCE

Output Source Current VCC = 10V −8.0 −15 mA
(P-Channel) TA = 25°C, V

OUT

= 0V

I

SINK

Output Sink Current VCC = 5V 1.75 3.6 mA
(N-Channel) TA = 25°C, V

OUT

= 0V

I

SINK

Output Sink Current VCC = 5V 8.0 16 mA
(N-Channel) TA = 25°C, V

OUT

= 0V

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MM74C174

AC Electrical Charac teristics (Note 2)

T

A

= 25°C, CL = 50 pF, unless otherwise noted

Note 2: AC Parameters are guara nt eed by DC correlated testing.
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: C

PD

determines the no load AC power consumption of any C M OS device. For complete explanation se e Family Characteristics Applic ation Note

AN-90.

AC Test Circuit Switching Time Waveforms

CMOS to CMOS

tr = tf = 20 ns

Symbol Parameter Conditions Min Typ Max Units

t

pd

Propagation Delay Time to a Logical VCC = 5V 150 300 ns

“0” or Logical “1” from Clock to Q VCC = 10V 70 110 ns

t

pd

Propagation Delay Time to VCC = 5V 110 300 ns
a Logical “0” from Clear VCC = 10V 50 110 ns

tS1, t

S0

Time Prior to Clock Pulse that VCC = 5V 75 ns
Data Must be Present VCC = 10V 25 ns

tH1, t

H0

Time after Clock Pulse VCC = 5V 0 −10 ns
that Data Must be Held VCC = 10V 0 −5.0 ns

t

W

Minimum Clock Pulse Width VCC = 5V 50 250 ns

VCC = 10V 35 100 ns

t

W

Minimum Clear Pulse Width VCC = 5V 65 140 ns

VCC = 10V 35 70 ns

tr, t

f

Maximum Clock Rise and VCC = 5V 15 >1200 µs
Fall Time VCC = 10V 5.0 >1200 µs

f

MAX

Maximum Clock Frequency VCC = 5V 2.0 6.5 MHz

VCC = 10V 5.0 12 MHz

C

IN

Input Capacitance Clear Input (Note 3) 11 pF

Any Other Input 5.0 pF

C

PD

Power Dissipation Capacitance Per Package (Note 4) 95 pF

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MM74C174

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow

Package Number M16A

Fairchild does not assume any responsibility for use of any circuitr y described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

MM74C174 Hex D-Type Flip-Flop

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or system s ar e devices or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea­sonably expected to result in a significant injury to the
user.

2. A critical component in any c omponent of a life suppor t
device or system whose failure to perform can be rea­sonably expected to cause the failure of the life suppor t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N16E