Datasheet MM58174AN Datasheet (NSC)

MM58174A
Microprocessor-Compatible Real-Time Clock

Y

General Description

The MM58174A is a low-threshold metal-gate CMOS circuit
that functions as a real-time clock and calendar in bus-ori­ented microprocessor systems. The device includes an in­terrupt timer which may be programmed to one of three
times. Timekeeping is maintained down to 2.2V to allow low
power standby battery operation. The timebase is generat­ed from a 32768 Hz crystal-controlled oscillator.

Features

Y

Microprocessor compatible

Y

Tenths of seconds, seconds, tens of seconds, minutes,
tens of minutes, day of week, days, tens of days,
months, tens of months, independent registers

Y

Automatic leap year calculation

Y

Internal pull-ups to safeguard data

Y

Protection for read during data changing

Y

Independent interrupt system with open drain output

Block Diagram

TTL compatible

Y

Low power standby operation (2.2V, 10 mA)

Y

Low cost internally biased oscillator

Y

Low cost 16-pin dual-in-line package

Y

Available for commercial and military temperature
ranges

Applications

Y

Point-of-sale terminals

Y

Word processors

Y

Teller terminals

Y

Event recorders

Y

Microprocessor-controlled instrumentation

Y

Microprocessor time clock

Y

TV/VCR reprogramming

Y

Intelligent telephone

MM58174A Microprocessor-Compatible Real-Time Clock

May 1991

FIGURE 1

TL/F/6681– 1

TRI-STATEÉis a registered trademark of National Semiconductor Corporation.

C

1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

TL/F/6681

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.

Voltage at All Inputs and Outputs V

Operating Temperature

MM58174AN

DD

a

0.3 to V

SS

b

40§Ctoa85§C

b

0.3

Storage Temperature

VDD–V

SS

b

65§Ctoa150§C

6.5V

Lead Temperature (Soldering, 10 seconds) 300§C

Electrical Characteristics T

eb

40§Ctoa85§C, V

A

e

0V

SS

Symbol Parameter Conditions Min Typ Max Units

V

DD

Supply Voltage Standby Mode

(no READ or WRITE Instructions)

2.2 5.5 V

Operational Mode 4.5 5.5 V

I

DD

Supply Current V

Input Logic Levels V
for Signals:

e

2.2V (Standby) 10 mA

DD

e

V

5V (Operating) 1 mA

DD

e

5V

DD

AD0–AD3, DB0–DB3, WR, RD, CS

Logic ‘‘1’’ 2 V
Logic ‘‘0’’ 0.8 V

Input Capacitance 10 pF

Input Current Levels V

Current to V
for Signals:

SS

AD0–AD3, DB0–DB3, RD

Internal Resistor to V
for Signals:

DD

WR

e

5V

DD

e

V

V

IN

DD

30 mA

30 100 kX

CS 30 100 kX

Output Logic Levels V
for Signals:

DD

e

5V

DB0–DB3

Logic ‘‘1’’ I
Logic ‘‘0’’ I

INTERRUPT (Open Drain)

Logic ‘‘0’’ For I
Off Leakage V

eb

0.1 mA 2.4 V

OH

e

1.6 mA 0.4 V

OL

e

1.6 mA 0.4 V

DS

e

5V 5 mA

OUT

2

Functional Description

The MM58174 is a microprocessor bus-oriented real-time
clock. The circuit includes addressable real-time counters
for tenths of seconds through months and a write only regis­ter for leap year calculation. The counters are arranged as
bytes of four bits each. When addressed a byte will appear
on the data I/O bus so that each word can be accessed
independently. If any byte does not contain four bits (e.g.,
days of the week uses only 3 bits), the unused bits will be
unrecognized during a write operation and tied to V
a read operation.

The addressable reset latch causes the pre-scaler, tenths of
seconds, seconds, and tens of seconds to be held in a reset
condition. If a register is updated during a read operation the
I/O data is prevented from updating and a subsequent read
will return the illegal b.c.d. code ’1111’. The interrupt timer
may be programmed for intervals of 0.5 second, 5 seconds,
or 60 seconds and may be coded as a single or repeated
operation. The open drain interrupt output is pulled to V
when the timer times out and reading the interrupt register
provides the internal selected information.

SS

during

SS

Circuit Description

The block diagram shown in
the CMOS clock chip. A 16-pin DIL package is used.

CRYSTAL OSCILLATOR

This consists of a CMOS inverter/amplifier with on-chip bias
resistor and capacitors. A single 6 pF – 36 pF trimmer is all
that is required to fine tune the crystal (see
ever, for improved stability, some crystals may require a ca­pacitor of typical value 20 pF to be added between pin 14
and ground. The output of the oscillator is blocked by the
start/stop F/F.

NON-INTEGER DIVIDER

This counter divides the incoming 32,768 Hz frequency by
15/16 down to 30,720 Hz.

FIXED DIVIDER (512)

This is a standard 9-stage binary ripple counter. Output fre­quency is 60 Hz. This counter is reset to zero by start/stop
F/F.

FIXED DIVIDER (6)

This is a 3-stage Johnson counter with a 10 Hz output sig­nal. This counter is reset to zero state by the start/stop F/F.

SYNCHRONIZATION STAGE

Both 10 Hz and 32,768 Hz clocks are fed into this section. It
is used to generate a pulse of 15.25 ms width on the rising
edge of each 10 Hz pulse.

This pulse is used to increment all the seconds, minutes,
hours, days, months, and year counter and also to set the
data changed F/F.

DATA CHANGED F/F

This is set by the rising edge of each 10 Hz pulse to indicate
that the clock value has changed since the last read opera­tion. It is reset by any clock read command.

The flip flop sets all data bus bits to a ‘‘1’’ during RD time
indicating that a register has been updated. This transient
condition may occur at the end of the Read Data strobe.
Hence, invalid data may still be read from the clock, if the
strobe width was less than 3 ms.

Figure 1

shows the structure of

Figure 2

). How-

Connection Diagram

Dual-In-Line Package

TL/F/6681– 2

Top View

Order Number MM58174AN

See NS Package Number N16A

The possibility may be overcome by implementing a further
read of the tenths of seconds register at the end of every
series of reads (starting with a read at the tenths of seconds
register) and checking for unchanged data.

SECONDS COUNTERS

There are three counters for Seconds:

a) tenths of seconds

b) units of seconds

c) tens of seconds

The outputs of all three counters can be separately multi­plexed on to the command 4-bit output bus. Table I shows
the address decoding for each counter. All three counters
are reset to zero by the start/stop F/F.

MINUTES COUNTERS

There are two Minutes counters:

a) units of minutes

b) tens of minutes

Both counters are parallel loaded with data from the 4-bit
input bus when addressed by the microprocessor and a
Write Data Strobe pulse given. Similarly, the output of both
counters can be read separately onto the common 4-bit out­put bus (Table I).

HOURS COUNTERS

There are two Hours counters which will count in a 24-hour
mode:

a) units of hours

b) tens of hours

Both counters have identical parallel load and read multi­plex features to the Minutes counters.

SEVEN DAY COUNTER

There is a 7-state counter which increments every 24 hours.
It will have identical parallel load and read multiplex capabili­ties to the Minutes and Hours counters. The counter counts
cyclically from 1 – 7.

3

Circuit Description (Continued)

FIGURE 2. Crystal Oscillator

DAYS COUNTER

There are two Days counters:

a) units of days

b) tens of days

The Days counters will count up to 28, 29, 30, or 31 days
depending on the state of the Months counters and the
Years Status Register. Days counters have parallel load and
read multiplex capabilities.

MONTHS COUNTERS

There are two Months counters:

a) units of months

b) tens of months

The Months counters have parallel load and read multiplex
capabilities.

YEARS STATUS REGISTER

The Years Status register is a shift register of 4 bits. It will be
shifted every year on December 31st. The status register
must be set in accordance with Table III. No readout capa­bility is provided.

CHIP SELECT (CS

An external chip select is provided. The chip enable is ac­tive low.

COUNTER AND REGISTER SELECTION

Table I shows the coding on the address lines AD0– AD3
which select the registers in the circuit to be either parallel
loaded or read on to the output bus.

)

TL/F/6681– 3

FIGURE 3. Test Mode Organization

START/STOP (RESET) LATCH

A logic ‘‘1’’ on DB0 at chip address 14 (E) will start the clock
running, a logic ‘‘0’’ will stop the clock. This function allows
the loading of time data into the clock and its precise start­ing. The clock starts at 0.1 seconds.

TEST MODE

This mode is incorporated to facilitate production testing of
the circuit. In this mode, the 32,768 Hz clock is fed forward
as shown in
be set to the non-test mode as part of the system initializa­tion. This is accomplished by writing a logic ‘‘0’’ to DB3 at
AD0.

0 Test Only 0 0 0 0 Write Only
1 Tenths of Secs. 0 0 0 1 Read Only
2 Units of Secs. 0 0 1 0 Read Only
3 Tens of Secs. 0 0 1 1 Read Only
4 Units of Mins. 0 1 0 0 Read or Write
5 Tens of Mins. 0 1 0 1 Read or Write
6 Units of Hours 0 1 1 0 Read or Write
7 Tens of Hours 0 1 1 1 Read or Write
8 Units of Days 1 0 0 0 Read or Write

9 Tens of Days 1 0 0 1 Read or Write
10 Day of Week 1 0 1 0 Read or Write
11 Units of Months 1 0 1 1 Read or Write
12 Tens of Months 1 1 0 0 Read or Write
13 Years 1 1 0 1 Write Only
14 Stop/Start 1 1 1 0 Write Only
15 Interrupt 1 1 1 1 Read or Write

Figure 3.

TABLE I. Address Decoding for Internal Registers

Selected

Counter

For normal operation, the circuit must

Address Bits

AD3 AD2 AD1 AD0

TL/F/6681– 4

Mode

4

Circuit Description (Continued)

TABLE IIa. Interrupt Selection Data

Mode: Address 15, Write Mode

Function DB3 DB2 DB1 DB0

No Interrupt X 0 0 0
Int. at 60 Sec. Intervals* 0/1 1 0 0
Int. at 5.0 Sec. Intervals* 0/1 0 1 0
Int. at 0.5 Sec. Intervals* 0/1 0 0 1

*a16.6 ms

e

DB3

0, single interrupt

e

DB3

1, repeated interrupt

TABLE IIb. Interrupt Read Back (Status)

Mode: Address 15, Read Mode

Interrupt Status DB3 DB2 DB1 DB0

Reset X 0 0 0
60 Sec. Signal X 1 0 0

5.0 Sec. Signal X 0 1 0

0.5 Sec. Signal X 0 0 1

Xedon’t care state

TABLE III. Years Status Register

Mode: Address 13, Write Mode

DB3 DB2 DB1 DB0

Leap Year 1 0 0 0
Leap Year-1 0 1 0 0
Leap Year-2 0 0 1 0
Leap Year-3 0 0 0 1

Note: Leap year counter rolls over on December 31@23:59:59.

INTERRUPT SYSTEM

The interrupt output and its frequency of operation is en­abled by writing to address 15 (see Table IIa). To ensure
correct operation, the interrupt should be serviced within

16.6 ms.

The interrupt is initialized by writing ‘‘0’’ to address 15 and
reading the interrupt, i.e., reading at address 15 three times.
Initialization must be performed at power on and also if the
interrupt is not serviced correctly within 16.6 ms.

SERVICING THE INTERRUPT

In a typical system the open drain interrupt output is wired to
the processor interrupt system. Hence, when the interrupt
timer times out, the interrupt output is pulled low and the
processor is interrupted.

The processor may then reset the interrupt by utilizing the
following procedure:

Read Address 15 three times.

This resets the interrupt output and restarts the interrupt
timer when in the repeat mode.

It is recommended that the interrupt output is connected to
a unique processor port.

CRYSTAL PARAMETERS

Figure 4

is an electrical representation of the crystal along
with some typical values. The 32.768 kHz crystal is an NT
CUT (tuning fork type) or XY BAR for use in a parallel reso­nant Pierce oscillator.

&

C

1

C

0

0.003 pF R

&

3.0 pF

&

35 k X

S

TL/F/6681– 5

FIGURE 4. Typical Crystal Parameters

DEVICE INITIALIZATION AND OSCILLATOR SETTING

When first installed or if the battery back-up has failed, the
MM58174A will require to be properly initialized. The follow­ing sequence is a suggested flow of operations to achieve
this.

Action Result

1) Apply power. Clears interrupt timer

2) Write ‘‘0’’ to address 15.

chain.

3) Read 3 times from Clears interrupt output
address 15. logic.

4) Write ‘‘0’’ on DB3 to Clears test mode.
address 0.

5) Write ‘‘0’’ on DB0 to Stops clock running.
address 14.

6) Set up timekeeping Load real-time into device
registers. time registers, minutes to

leap years.

7) Write ‘‘1’’ on DB0 to Starts timekeeping
address 14. synchronized to an

external time source.

8) Program and start Commence interrupt
interrupts. timing, if so required.

OSCILLATOR SETTING

Directly connecting a frequency meter to the Crystal Out pin
(14) will not allow correct frequency setting because of the
extra capacitive loading of the meter. One possibility for set­ting is to use a high impedance probe or a CMOS buffer to
keep the loading as low as possible (e.g., 100x2pFprobe).
Alternatively, a buffered output of 16.384 kHz OSC/2 can
be produced on DB0 by applying the following procedure:

Action Result

1) Write a ‘‘1’’ on DB3 to Selects test mode.
address 0.

2) Write a ‘‘1’’ on DB0 to Starts clock timing.
address 14.

3) Read at address 1 (tenths ‘‘Data Changed’’ signal is
of secs). read.

4) Read at address 1 and 16.384 kHz appears on
HOLD the strobe LOW. DB0.

5) Adjust trimmer capacitor.

There must be no extra activity on the RD

line between
steps 3 and 4 or only the normal ‘‘Data Changed’’ signal will
be observed on the data bus. Thus if the normal host proc­essor system is being used to generate the chip waveforms,
proper care must be taken.

5

Timing Waveforms

READ MODE

Figure 6

gives detailed timing for the transfer of data from

peripheral to microprocessor. See Table IV.

All times are measured from (or to) valid logic ‘‘0’’ level

0.8V or valid logic ‘‘1’’ levele2.0V.

WRITE MODE

Figure 7

gives detailed timing for the transfer of data from

microprocessor to peripheral. See Table V.

e

FIGURE 5. Typical Microprocessor Interface

FIGURE 6. Read Cycle Waveforms

FIGURE 8. Typical Supply Current vs Supply Voltage during Power Down

TL/F/6681– 7

TL/F/6681– 6

TL/F/6681– 8

FIGURE 7. Write Cycle Waveforms

TL/F/6681– 9

6

Operating Conditions MM58174AN T

A

eb

40§Cto85§C, V

DD

e

5V

TABLE IV. Read Timing: Data from Peripheral to Microprocessor

Symbol Parameter

t

ACS0

t

CSR

t

RD

t

RH

t

RA

t

ACS1

t

AD

t

HZ

t

RW

t

AR

Note 1: In order not to degrade timekeeping accuracy, the number of Read strobes in any one second should be less than 10,000.

Note 2: If address and read occur simultaneously then they must exist for t

Address Bus Valid to Chip Select ON (CSe0) 0 ns

Chip Select ON to Read Strobe 0 ns

Read Cycle Access Time from
Read Strobe to Data Bus Valid

Data Hold Time from Trailing Edge of
Read Strobe

Address Bus Hold Time from
Trailing Edge of Read Strobe

Address Change to Chip Select OFF 0 40 ns

Address Bus Valid to Data Valid 1850 850 ns C

Time from Trailing Edge of Read
Strobe until Interface Device Bus 0 330 ns
Drivers are in TRI-STATE

É

Mode

Read Strobe Width 14 ms

Address Bus Valid to Read Strobe 500 ns

AR

MM58174AN

Min Max

Typ Units Comments

900 450 ns

0 330 ns

70 500 ns

a

tAD.

TABLE V. Write Timing: Data from Microprocessor to Peripheral

Symbol Parameter

t

ACS0

t

CSW

t

AW

t

WW

t

DW

t

WA

t

WD

t

ACS1

Note 3: If address and write occur simultaneously, then they must exist for tAWand tWW.

Address Bus Valid to Chip Select ON (CSe0) 0 ns

Chip Select ON to Write Strobe 0 450 ns

Address Bus Valid to Write Strobe 725 ns

Write Strobe Width 670 ns

Data Bus Valid before Write Strobe 70 ns

Address Bus Hold Time following Write Strobe 165 ns

Data Bus Hold Time following Write Strobe 185 ns

Address Change to Chip Select OFF (CSe1) 0 ns

MM58174AN

Min Max

Typ Units Comments

e

C

100 pF

L

e

100 pF

L

7

Physical Dimensions inches (millimeters)

Molded Dual-In-Line Package (N)

Order Number MM58174AN

NS Package Number N16A

MM58174A Microprocessor-Compatible Real-Time Clock

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:

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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.

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