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TL/F/5206
MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator
January 1988
MM54HC123A/MM74HC123A
Dual Retriggerable Monostable Multivibrator
General Description
The MM54/74HC123A high speed monostable multivibrators (one shots) utilize advanced silicon-gate CMOS technology. They feature speeds comparable to low power
Schottky TTL circuitry while retaining the low power and
high noise immunity characteristic of CMOS circuits.
Each multivibrator features both a negative, A, and a positive, B, transition triggered input, either of which can be
used as an inhibit input. Also included is a clear input that
when taken low resets the one shot. The ’HC123 can be
triggered on the positive transition of the clear while A is
held low and B is held high.
The ’HC123A is retriggerable. That is it may be triggered
repeatedly while their outputs are generating a pulse and
the pulse will be extended.
Pulse width stability over a wide range of temperature and
supply is achieved using linear CMOS techniques. The out-
put pulse equation is simply: PW
e
(R
EXT
)(C
EXT
); where PW
is in seconds, R is in ohms, and C is in farads. All inputs are
protected from damage due to static discharge by diodes to
V
CC
and ground.
Features
Y
Typical propagation delay: 25 ns
Y
Wide power supply range: 2V– 6V
Y
Low quiescent current: 80 mA maximum (74HC Series)
Y
Low input current: 1 mA maximum
Y
Fanout of 10 LS-TTL loads
Y
Simple pulse width formula TeRC
Y
Wide pulse range: 400 ns to%(typ)
Y
Part to part variation:g5% (typ)
Y
Schmitt TriggerA&Binputs enable infinite signal input
rise and fall times.
Connection Diagram
Dual-In-Line Package
TL/F/5206– 1
Top View
Order Number MM54HC123A or MM74HC123A
Timing Component
TL/F/5206– 2
Note: Pin 6 and Pin 14 must be
hard-wired to GND.
Truth Table
Inputs Outputs
Clear AB Q Q
LXX L H
XHX L H
XXL L H
HL
u
Éß
H
v
HÉß
u
LH Éß
H
e
High Level
L
e
Low Level
u
e
Transition from Low to High
v
e
Transition from High to Low
É
e
One High Level Pulse
ß
e
One Low Level Pulse
X
e
Irrelevant
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Page 2
Absolute Maximum Ratings (Notes1&2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Supply Voltage (V
CC
)
b
0.5V toa7.0V
DC Input Voltage (VIN)
b
1.5V to V
CC
a
1.5V
DC Output Voltage (V
OUT
)
b
0.5V to V
CC
a
0.5V
Clamp Diode Current (IIK,IOK)
g
20 mA
DC Output Current, per pin (I
OUT
)
g
25 mA
DC VCCor GND Current, per pin (ICC)
g
50 mA
Storage Temperature Range (T
STG
)
b
65§Ctoa150§C
Power Dissipation (PD)
(Note 3) 600 mW
S.O. Package only 500 mW
Lead Temperature (T
L
)
(Soldering 10 seconds) 260
§
C
Operating Conditions
Min Max Units
Supply Voltage (V
CC
)26V
DC Input or Output Voltage 0 V
CC
V
(V
IN,VOUT
)
Operating Temp. Range (TA)
MM74HC
b
40
a
85
§
C
MM54HC
b
55
a
125
§
C
Input Rise or Fall Times
(Clear Input)
V
CC
e
2.0V(tr,tf) 1000 ns
V
CC
e
4.5V 500 ns
V
CC
e
6.0V 400 ns
DC Electrical Characteristics (Note 4)
T
A
e
25§C
74HC 54HC
Symbol Parameter Conditions V
CC
T
A
eb
40 to 85§CT
A
eb
55 to 125§C
Units
Typ Guaranteed Limits
V
IH
Minimum High Level Input 2.0V 1.5 1.5 1.5 V
Voltage 4.5V 3.15 3.15 3.15 V
6.0V 4.2 4.2 4.2 V
V
IL
Maximum Low Level Input 2.0V 0.3 0.3 0.3 V
Voltage 4.5V 0.9 0.9 0.9 V
6.0V 1.2 1.2 1.2 V
V
OH
Minimum High Level V
IN
e
VIHor V
IL
Output Voltage
l
I
OUT
l
s
20 mA 2.0V 2.0 1.9 1.9 1.9 V
4.5V 4.5 4.4 4.4 4.4 V
6.0V 6.0 5.9 5.9 5.9 V
V
IN
e
VIHor V
IL
V
l
I
OUT
l
s
4.0 mA 4.5V 4.2 3.98 3.84 3.7 V
l
I
OUT
l
s
5.2 mA 6.0V 5.7 5.48 5.34 5.2 V
V
OL
Maximum Low Level V
IN
e
VIHor V
IL
Output Voltage
l
I
OUT
l
s
20 mA 2.0V 0 0.1 0.1 0.1 V
4.5V 0 0.1 0.1 0.1 V
6.0V 0 0.1 0.1 0.1 V
V
IN
e
VIHor V
IL
V
l
I
OUT
l
s
4 mA 4.5V 0.2 0.26 0.33 0.4 V
l
I
OUT
l
s
5.2 mA 6.0V 0.2 0.26 0.33 0.4 V
I
IN
Maximum Input Current V
IN
e
VCCor GND 6.0V
g
0.5
g
5.0
g
5.0 mA
(Pins 7, 15)
I
IN
Maximum Input Current V
IN
e
VCCor GND 6.0V
g
0.1
g
1.0
g
1.0 mA
(all other pins)
I
CC
Maximum Quiescent Supply V
IN
e
VCCor GND 6.0V 8.0 80 160 mA
Current (standby) I
OUT
e
0 mA
I
CC
Maximum Active Supply V
IN
e
VCCor GND 2.0V 36 80 110 130 mA
Current (per R/C
EXT
e
0.5VCC4.5V 0.33 1.0 1.3 1.6 mA
monostable) 6.0V 0.7 2.0 2.6 3.2 mA
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation Temperature Derating:
Plastic ‘‘N’’ Package:
b
12mW/§C from 65§Cto85§C
Ceramic ‘‘J’’ Package:
b
12mW/§C from 100§Cto125§C.
Note 4: For a power supply of 5V
g
10% the worst-case output voltages (VOH,VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst-case V
IH
and VILoccur at V
CC
e
5.5V and 4.5V respectively. (The VIHvalue at 5.5V is 3.85V.) The worst-case leakage current (IIN,ICC, and
I
OZ
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
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AC Electrical Characteristics V
CC
e
5V, T
A
e
25§C, C
L
e
15 pF, t
r
e
t
f
e
6ns
Symbol Parameter Conditions Typ Limit Units
t
PLH
Maximum Trigger Propagation Delay 22 33 ns
A, B or Clear to Q
t
PHL
Maximum Trigger Propagation Delay 25 42 ns
A, B or Clear to Q
t
PHL
Maximum Propagation Delay, Clear to Q 20 27 ns
t
PLH
Maximum Propagation Delay, Clear to Q 22 33 ns
t
W
Minimum Pulse Width, A, B or Clear 14 26 ns
t
REM
Minimum Clear Removal Time 0 ns
t
WQ(MIN)
Minimum Output Pulse Width C
EXT
e
28 pF 400 ns
R
EXT
e
2kX
t
WQ
Output Pulse Width C
EXT
e
1000 pF 10 ms
R
EXT
e
10 kX
AC Electrical Characteristics C
L
e
50 pF t
r
e
t
f
e
6 ns (unless otherwise specified)
T
A
e
25§C
74HC 54HC
Symbol Parameter Conditions V
CC
T
A
eb
40 to 85§CT
A
eb
55 to 125§C
Units
Typ Guaranteed Limits
t
PLH
Maximum Trigger Propagation 2.0V 77 169 194 210 ns
Delay, A, B or Clear to Q 4.5V 26 42 51 57 ns
6.0V 21 32 39 44 ns
t
PHL
Maximum Trigger Propagation 2.0V 88 197 229 250 ns
Delay, A, B or Clear to Q
4.5V 29 48 60 67 ns
6.0V 24 38 46 51 ns
t
PHL
Maximum Propagation Delay 2.0V 54 114 132 143 ns
Clear to Q 4.5V 23 34 41 45 ns
6.0V 19 28 33 36 ns
t
PLH
Maximum Propagation Delay 2.0V 56 116 135 147 ns
Clear to Q
4.5V 25 36 42 46 ns
6.0V 20 29 34 37 ns
t
W
Minimum Pulse Width 2.0V 57 123 144 157 ns
A, B, Clear 4.5V 17 30 37 42 ns
6.0V 12 21 27 30 ns
t
REM
Minimum Clear 2.0V 0 0 0 ns
Removal Time 4.5V 0 0 0 ns
6.0V 0 0 0 ns
t
TLH,tTHL
Maximum Output 2.0V 30 75 95 110 ns
Rise and Fall Time 4.5V 8 15 19 22 ns
6.0V 7 13 16 19 ns
t
WQ(MIN)
Minimum Output C
EXT
e
28 pF 2.0V 1.5 ms
Pulse Width R
EXT
e
2kX 4.5V 450 ns
R
EXT
e
6kX(V
CC
e
2V) 6.0V 380 ns
t
WQ
Output Pulse Width C
EXT
e
0.1 mF Min 5.0V 1 0.9 0.86 0.85 ms
R
EXT
e
10 kX
Max 5.0V 1 1.1 1.14 1.15 ms
C
IN
Maximum Input 12 20 20 20 pF
Capacitance (Pins7&15)
C
IN
Maximum Input 6 10 10 10 pF
Capacitance (other inputs)
C
PD
Power Dissipation (Note 5) 70 pF
Capacitance
Note 5: CPDdetermines the no load dynamic power consumption, P
D
e
CPDV
CC
2
faICCVCC, and the no load dynamic current consumption, I
S
e
C
PD
VCCfaICC.
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Logic Diagram
TL/F/5206– 5
Theory of Operation
TL/F/5206– 6
j POSITIVE EDGE TRIGGER m POSITIVE EDGE RE-TRIGGER (PULSE LENGTHENING)
k NEGATIVE EDGE TRIGGER n RESET PULSE SHORTENING
l POSITIVE EDGE TRIGGER o CLEAR TRIGGER
FIGURE 1
TRIGGER OPERATION
As shown in
Figure 1
and the logic diagram before an input
trigger occurs, the one shot is in the quiescent state with the
Q output low, and the timing capacitor C
EXT
completely
charged to V
CC
. When the trigger input A goes from VCCto
GND (while inputs B and clear are held to V
CC
) a valid trig-
ger is recognized, which turns on comparator C1 and N-
channel transistor N1
j. At the same time the output latch
is set. With transistor N1 on, the capacitor C
EXT
rapidly dis-
charges toward GND until V
REF1
is reached. At this point
the output of comparator C1 changes state and transistor
N1 turns off. Comparator C1 then turns off while at the
same time comparator C2 turns on. With transistor N1 off,
the capacitor C
EXT
begins to charge through the timing re-
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sistor, R
EXT
, toward VCC. When the voltage across C
EXT
equals V
REF2
, comparator C2 changes state causing the
output latch to reset (Q goes low) while at the same time
disabling comparator C2. This ends the timing cycle with the
monostable in the quiescent state, waiting for the next trigger.
A valid trigger is also recognized when trigger input B goes
from GND to V
CC
(while input A is at GND and input clear is
at V
CC
k). The ’HC123A can also be triggered when clear
goes from GND to V
CC
(while A is at GND and B is at
V
CC
o).
It should be noted that in the quiescent state C
EXT
is fully
charged to V
CC
causing the current through resistor R
EXT
to
be zero. Both comparators are ‘‘off’’ with the total device
current due only to reverse junction leakages. An added
feature of the ’HC123A is that the output latch is set via the input trigger without regard to the capacitor voltage. Thus, propagation delay from trigger to Q is independent of the value
of C
EXT,REXT
, or the duty cycle of the input waveform.
RETRIGGER OPERATION
The ’HC123A is retriggered if a valid trigger occurs
l fol-
lowed by another trigger
m before the Q output has re-
turned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at the R/C
EXT
pin has begun to rise
from V
REF1
, but has not yet reached V
REF2
, will cause an
increase in output pulse width T. When a valid retrigger is
initiated
m, the voltage at the R/C
EXT
pin will again drop to
V
REF1
before progressing along the RC charging curve
toward V
CC
. The Q output will remain high until time T, after
the last valid retrigger.
Because the trigger-control circuit flip-flop resets shortly after C
X
has discharged to the reference voltage of the lower
reference circuit, the minimum retrigger time, t
rr
is a function
of internal propagation delays and the discharge time of C
X
:
t
rr
&
20
a
187
V
CC
b
0.7
a
565a(0.256 VCC)C
X
[
V
CC
b
0.7
]
2
Another removal/retrigger time occurs when a short clear
pulse is used. Upon receipt of a clear, the one shot must
charge the capacitor up to the upper trip point before the
one shot is ready to receive the next trigger. This time is
dependent on the capacitor used and is approximately:
t
rr
e
196
a
640
V
CC
b
0.7
a
522a(0.3 VCC)C
X
(V
CC
b
0.7)
2
ns
RESET OPERATION
These one shots may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on clear sets the reset latch and causes the capacitor to be
fast charged to V
CC
by turning on transistor Q1 n . When
the voltage on the capacitor reaches V
REF2
, the reset latch
will clear and then be ready to accept another pulse. If the
clear input is held low, any trigger inputs that occur will be
inhibited and the Q and Q
outputs of the output latch will
not change. Since the Q output is reset when an input low
level is detected on the Clear input, the output pulse T can
be made significantly shorter than the minimum pulse width
specification.
Typical Output Pulse Width vs.
Timing Components
TL/F/5206– 7
Typical Distribution of Output
Pulse Width, Part to Part
TL/F/5206– 8
Typical 1ms Pulse Width
Variation vs. Supply
TL/F/5206– 9
Minimum R
EXT
vs.
Supply Voltage
TL/F/5206– 10
Typical 1ms Pulse Width
Variation vs. Temperature
TL/F/5206– 11
Note: R and C are not subjected to temperature. The C is polypropylene.
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MM54HC123A/MM74HC123A Dual Retriggerable Monostable Multivibrator
Physical Dimensions inches (millimeters)
Dual-In-Line Package (J)
Order Number MM54HC123AJ or MM74HC123AJ
NS Package Number J16A
Dual-In-Line Package (N)
Order Number MM74HC123AN
NS Package Number N16E
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant support device or system whose failure to perform can
into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life
failure to perform, when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can effectiveness.
be reasonably expected to result in a significant injury
to the user.
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Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
a
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