Datasheet MM54C902J-883 Datasheet (NSC)

Page 1
TL/F/5909
MM54C901/MM74C901 (TTL), MM54C903/MM74C903 (CMOS) Hex Inverting Buffer
MM54C902/MM74C902 (TTL), MM54C904/MM74C904 (CMOS) Hex Non-Inverting Buffer
February 1988
MM54C901/MM74C901 Hex Inverting TTL Buffer MM54C902/MM74C902 Hex Non-Inverting TTL Buffer MM54C903/MM74C903 Hex Inverting CMOS Buffer MM54C904/MM74C904 Hex Non-Inverting CMOS Buffer
General Description
CC
supply.
Features
Y
Wide supply voltage range 3.0V to 15V
Y
Guaranteed noise margin 1.0V
Y
High noise immunity 0.45 VCC(typ.)
Y
TTL compatibility Fan out of 2
driving standard TTL
Connection Diagrams
Dual-In-Line Package MM54C901/MM74C901 MM54C903/MM74C903
TL/F/5909– 1
Top View
Order Number MM54C901,
MM74C901, MM54C903 or MM74C903
Dual-In-Line Package MM54C902/MM74C902 MM54C904/MM74C904
TL/F/5909– 2
Top View
Order Number MM54C902,
MM74C902, MM54C904 or MM74C904
C
1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
Page 2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Voltage at Any Pin
b
0.3V to V
CC
a
0.3V
Voltage at Any Input Pin
MM54C901/MM74C901
b
0.3V toa15V
MM54C902/MM74C902
b
0.3V toa15V
MM54C903/MM74C903 V
CC
b
17V to V
CC
a
0.3V
MM54C904/MM74C904 V
CC
b
17V to V
CC
a
0.3V
Storage Temperature Range (T
S
)
b
65§Ctoa150§C
Power Dissipation (PD)
Dual-In-Line 700 mW Small Outline 500 mW
Operating Temperature Range (T
A
) MM54C901, MM54C902, MM54C903, MM54C904
b
55§Ctoa125§C MM74C901, MM74C902, MM74C903, MM74C904
b
40§Ctoa85§C
Operating VCCRange 3.0V to 15V
Absolute Maximum V
CC
18V
Lead Temperature (TL)
(Soldering, 10 seconds) 260
§
C
DC Electrical Characteristics Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
CMOS TO CMOS
V
IN(1)
Logical ‘‘1’’ Input Voltage V
CC
e
5.0V 3.5 V
V
CC
e
10V 8.0 V
V
IN(0)
Logical ‘‘0’’ Input Voltage V
CC
e
5.0V 1.5 V
V
CC
e
10V 2.0 V
V
OUT(1)
Logical ‘‘1’’ Output Voltage V
CC
e
5.0V, I
O
eb
10 mA 4.5 V
V
CC
e
10V, I
O
eb
10 mA 9.0 V
V
OUT(0)
Logical ‘‘0’’ Output Voltage V
CC
e
5.0V 0.5 V
V
CC
e
10V 1.0 V
I
IN(1)
Logical ‘‘1’’ Input Current V
CC
e
15V, V
IN
e
15V 0.005 1.0 m A
I
IN(0)
Logical ‘‘0’’ Input Current V
CC
e
15V, V
IN
e
0V
b
1.0
b
0.005 mA
I
CC
Supply Current V
CC
e
15V 0.05 15 mA
TTL TO CMOS
V
IN(1)
Logical ‘‘1’’ Input Voltage 54C V
CC
e
4.5V V
CC
b
1.5 V
74C V
CC
e
4.75V V
CC
b
1.5 V
V
IN(0)
Logical ‘‘0’’ Input Voltage 54C V
CC
e
4.5V 0.8 V
74C V
CC
e
4.75V 0.8 V
CMOS TO TTL
V
IN(1)
Logical ‘‘1’’ Input Voltage
MM54C901, MM54C903 V
CC
e
4.5V 4.0 V
MM54C902, MM54C904 V
CC
e
4.5V V
CC
b
1.5 V
MM74C901, MM74C903 V
CC
e
4.75V 4.25 V
MM74C902, MM74C904 V
CC
e
4.75V V
CC
b
1.5 V
V
IN(0)
Logical ‘‘0’’ Input Voltage
MM54C901, MM54C903 V
CC
e
4.5V 1.0 V
MM54C902, MM54C904 V
CC
e
4.5V 1.5 V
MM74C901, MM74C903 V
CC
e
4.75V 1.0 V
MM74C902, MM74C904 V
CC
e
4.75V 1.5 V
V
OUT(1)
Logical ‘‘1’’ Output Voltage 54C V
CC
e
4.5V, I
O
eb
800 mA 2.4 V
74C V
CC
e
4.75V, I
O
eb
800 mA 2.4 V
V
OUT(0)
Logical ‘‘0’’ Output Voltage
MM54C901, MM54C903 V
CC
e
4.5V, I
O
e
2.6 mA 0.4 V
MM54C902, MM54C904 V
CC
e
4.5V, I
O
e
3.2 mA 0.4 V
MM74C901, MM74C903 V
CC
e
4.75V, I
O
e
2.6 mA 0.4 V
MM74C902, MM74C904 V
CC
e
4.75V, I
O
e
3.2 mA 0.4 V
2
Page 3
DC Electrical Characteristics (Continued)
Min/Max limits apply across temperature range unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
OUTPUT DRIVE (See 54C/74C Family Characteristics Data Sheet) (Short Circuit Current)
(MM54C901/MM74C901, MM54C903/MM74C903)
I
SOURCE
Output Source Current V
CC
e
5.0V, V
OUT
e
0V
b
5.0 mA
(P-Channel) T
A
e
25§C, V
IN
e
0V
I
SOURCE
Output Source Current V
CC
e
10V, V
OUT
e
0V
b
20 mA
(P-Channel) T
A
e
25§C, V
IN
e
0V
I
SINK
Output Sink Current V
CC
e
5.0V, V
OUT
e
V
CC
9.0 mA
(N-Channel) T
A
e
25§C, V
IN
e
V
CC
I
SINK
Output Sink Current V
CC
e
5.0V, V
OUT
e
0.4V
3.8 mA
(N-Channel) T
A
e
25§C, V
IN
e
V
CC
(MM54C902/MM74C902, MM54C904/MM74C904)
I
SOURCE
Output Source Current V
CC
e
5.0V, V
OUT
e
0V
b
5.0 mA
(P-Channel) T
A
e
25§C, V
IN
e
V
CC
I
SOURCE
Output Source Current V
CC
e
10V, V
OUT
e
0V
b
20 mA
(P-Channel) T
A
e
25§C, V
IN
e
V
CC
I
SINK
Output Sink Current V
CC
e
5.0V, V
OUT
e
V
CC
9.0 mA
(N-Channel) T
A
e
25§C, V
IN
e
0V
I
SINK
Output Sink Current V
CC
e
5.0V, V
OUT
e
0.4V
3.8 mA
(N-Channel) T
A
e
25§C, V
IN
e
0V
AC Electrical Characteristics* T
A
e
25§C, C
L
e
50 pF, unless otherwise noted
Symbol Parameter Conditions Min Typ Max Units
MM54C901/MM74C901, MM54C903/MM74C903
t
pd1
Propagation Delay Time V
CC
e
5.0V 38 70 ns
to a Logical ‘‘1’’ V
CC
e
10V 22 30 ns
t
pd0
Propagation Delay Time V
CC
e
5.0V 21 35 ns
to a Logical ‘‘0’’ V
CC
e
10V 13 20 ns
C
IN
Input Capacitance Any Input (Note 2) 14 pF
C
PD
Power Dissipation Capacity (Note 3) Per Buffer 30 pF
MM54C902/MM74C902, MM54C904/MM74C904
t
pd1
Propagation Delay Time V
CC
e
5.0V 57 90 ns
to a Logical ‘‘1’’ V
CC
e
10V 27 40 ns
t
pd0
Propagation Delay Time V
CC
e
5.0V 54 90 ns
to a Logical ‘‘0’’ V
CC
e
10V 25 40 ns
C
IN
Input Capacitance Any Input (Note 2) 5.0 pF
C
PD
Power Dissipation Capacity (Note 3) Per Buffer 50 pF
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’ they are not meant to imply that the devices should be operated at these limits. The table of ‘‘Electrical Characteristics’’ provides conditions for actual device operation.
Note 2: Capacitance is guaranteed by periodic testing.
Note 3: C
PD
determines the no load AC power consumption of any CMOS device. For complete explanation see 54C/74C Family Characteristics application note
AN-90.
3
Page 4
Logic Diagrams
MM54C901/MM74C901
CMOS to TTL Inverting Buffer
TL/F/5909– 3
MM54C903/MM74C903
PMOS to TTL or CMOS Inverting Buffer
TL/F/5909– 4
MM54C902/MM74C902
CMOS to TTL Buffer
TL/F/5909– 5
MM54C904/MM74C904
PMOS to TTL or CMOS Buffer
TL/F/5909– 6
Typical Applications
PMOS to CMOS or TTL Interface
Note: V
CC
a
V
DD
s
17V
V
CC
s
15V
TL/F/5909– 7
CMOS to TTL or CMOS at a Lower V
CC
Note: V
CC1
e
V
CC2
TL/F/5909– 8
4
Page 5
AC Test Circuit and Switching Time Waveforms
TL/F/5909– 9
Note: Delays measured with input tr,t
f
e
20 ns.
CMOS to CMOS
TL/F/5909– 10
Typical Performance Characteristics
to a Logical ‘‘0’’ for the
Typical Propagation Delay
MM54C903/MM74C903
MM54C901/MM74C901 and
TL/F/5909– 11
MM54C901/MM74C901 and
to a Logical ‘‘1’’ for the
Typical Propagation Delay
M54C903/MM74C903
TL/F/5909– 13
to a Logical ‘‘0’’ for the
Typical Propagation Delay
MM54C904/MM74C904
MM54C902/MM74C902 and
TL/F/5909– 14
to a Logical ‘‘1’’ for the
Typical Propagation Delay
MM54C904/MM74C904
MM54C902/MM74C902 and
TL/F/5909– 12
5
Page 6
MM54C901/MM74C901 (TTL), MM54C903/MM74C903 (CMOS) Hex Inverting Buffer
MM54C902/MM74C902 (TTL), MM54C904/MM74C904 (CMOS) Hex Non-Inverting Buffer
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MM54C901J, MM74C901J, MM54C902J,
MM74C902J, MM54C903J, MM74C903J, MM54C904J or MM74C904J
NS Package Number J14A
Molded Dual-In-Line Package (N)
Order Number MM54C901N, MM74C901N, MM54C902N,
MM74C902N, MM54C903N, MM74C903N, MM54C904N or MM74C904N
NS Package Number N14A
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