MITSUMI
System Reset (with built-in watchdog timer) MM1135, MM1136
VCC input pulse width 8TPI µS
CK input pulse width T
CKW 3µS
CK input cycle T
CK 20 µS
Watchdog timer monitoring time *1
TWD CT=0.02µF 50 100 150 mS
Watchdog timer
reset time
*
2
T
WR CT=0.02µF 1 2 3 mS
Reset hold time for
power supply rise *3
TPR CT=0.02µF 50 100 150 mS
RESET
------------------------------------------
delay time tPDR
VCC: High Low, R
LR
=10kΩ, C
LR
=15pF
10 µS
BC delay time t
PDB
VCC: High Low, R
LB
=4.7kΩ, C
LB
=15pF
10 µS
RESET
------------------------------------------
rise time tRR RLR=10kΩ, CLR=15pF 10 µS
RESET
------------------------------------------
fall time tFR RLR=10kΩ, CLR=15pF 2 µS
BC rise time t
RB RLB=4.7kΩ, CLB=15pF 10 µS
BC fall time t
FB RLB=4.7kΩ, CLB=15pF 2 µS
VCC
3.8V
2.8V T
PI
CK
T
CKW
or
CK
T
CK
Notes:
*
1 Monitoring time is the time from the last pulse (negative edge) of the timer clear clock pulse until reset
pulse output.
In other words, reset output is output if a clock pulse is not input during this time.
*
2 Reset time means reset pulse width. However, this does not apply to power ON reset.
*
3 Reset hold time is the time from when VCC exceeds detection voltage (VSHR) during power ON reset until
reset release (RESET
-----------------------------------------------------
output high).
*
4 Watchdog timer monitoring time (TWD), watchdog timer reset time (TWR) and reset hold time (TPR) during
power supply rise can be changed by varying C
T capacitance. The times are expressed by the following
formulae.
T
PR (mS)
.
=.5000 CT (µF)
T
WD (mS)
.
=.5000 CT (µF)
T
WR (mS)
.
=.100 CT (µF)
Example : When C
T=0.02µF
T
PR
.
=.100mS
T
WD
.
=.100mS
T
WR
.
=.2mS
*
5TWD can be varied by placing a resistor (1MEGΩ or more) between the RCT pin and VCC.
*
6 The voltage range when measuring output rise and fall time is 10~90%.
*
7VCC rise time should be 100µS or more, and fall time should be 50µS or more.