Page 1
E2C0045-19-83
Preliminary
¡ Semiconductor
This version: Aug. 1999
ML9211
¡ Semiconductor
ML9211
56-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming
GENERAL DESCRIPTION
The ML9211 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty)
vacuum fluorescent display tube. It consists of a 56-segment driver multiplexed to drive up to
168 segments, and 10-bit digital dimming circuit.
ML9211 features a selection of a master mode and a slave mode, and therefore it can be used to
expand segments for the VFD driver with keyscan and A/D converter function.
ML9211 provides an interface with a microcontroller only by three signal lines: DATA IN,
CLOCK and CS.
FEATURES
• Logic supply voltage (VDD) : 4.5 to 5.5V
• Driver supply voltage (V
• Duplex/Triplex (1/2 duty / 1/3 duty) selectable
DUP/TRI=1/2 duty selectable at "H" level
DUP/TRI=1/3 duty selectable at "L" level
• Number of display segments
Max. 112-segment display (during 1/2 duty mode)
Max. 168-segment display (during 1/3 duty mode)
• Master/Slave selectable
M/S=Master mode selectable at "H" level
M/S=Slave mode selectable at "L" level
• Interface with a microcontroller
Three lines: CS, CLOCK, and DATA IN
• 56-segment driver outputs : IOH=–5mA at VOH=V
(can be directly connected to VFD tube : IOH=–10mA at VOH=V
and require no external resistors) : IOL=500mA at VOL=2V (SEG1 to 56)
• 3-grid pre-driver outputs : IOH=–5.0mA at VOH=V
(require external drivers) IOL=10mA at VOL=2V
• Logic outputs : IOH=–200mA at VOH=VDD–0.8V
• Built-in digital dimming circuit (10-bit resolution)
• Built-in oscillation circuit (external R and C)
• Built-in Power-On-Reset circuit
• Package options:
80-pin plastic QFP (QFP80-P-1420-0.80-BK) Product name: ML9211GA
80-pin plastic QFP (QFP80-P-1414-0.65-K) Product name: ML9211GP
) : 8 to 18V
DISP
IOL=200mA at VOL=0.8V
–0.8V (SEG1 to 37)
DISP
–0.8V (SEG38 to 56)
DISP
–0.8V
DISP
1/19
Page 2
¡ Semiconductor
BLOCK DIAGRAM
V
DISP
D-GND
56 Segment Driver
ML9211
GRID2 GRID3GRID1SEG56SEG1
3 Grid pre Driver
V
DD
L-GND
CS
CLOCK
DATA IN
OSC0
DIM IN
SYNC IN1
SYNC IN2
M/S
DUP/TRI
POR
Power
On
Reset
0H 4H
Mode Select
in1-3
Control
OSC
POR
1H
0H
POR
Out1-56
Segment Latch
1
in1-56
Out1-3
3bit Shift Register
POR
Out1-56
168 to 56 Segment Control
in1-56 in1-56in1-56
2H
0H
POR
Out1-56
Segment Latch
2
in1-56
Out1-56
56bit Shift Register
POR
POR
POR
Timing Generator
3H
0H
POR
4H
Out1-56
Segment Latch
3
in1-56
in1-10
Dimming Latch
Out1-10
10bit Digital
Dimming
DIM OUT
SYNC OUT1
SYNC OUT2
2/19
Page 3
¡ Semiconductor
INPUT AND OUTPUT CONFIGURATION
Schematic Diagram of Driver Output Circuit
ML9211
V
D-GND
DISP
V
DISP
OUTPUT
D-GND
3/19
Page 4
¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
ML9211
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
GRID1
GRID2
GRID3
NC
D-GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DISP
V
80
1
2
3
4
5
6
7
8
9
SEG36
SEG37
78
79
SEG34
SEG35
76
77
SEG33
75
SEG31
SEG32
73
74
SEG30
72
SEG28
SEG29
70
71
SEG26
SEG27
68
69
SEG25
67
DISP
V
SEG24
65
66
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
NC
25
V
DD
32
31
30
29
28
27
26
DIM IN
SYNC IN 1
CS
SYNC IN 2
CLOCK
DATA IN
NC
NC: No connection
80-pin Plastic QFP
(QFP80-P-1420-0.80-BK)
34
33
OSC0
L-GND
35
DUP/TRI
38
37
36
M/S
SYNC OUT 2
40
39
D-GND
DIM OUT
SYNC OUT 1
4/19
Page 5
¡ Semiconductor
ML9211
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
SEG48
SEG49
SEG50
SEG51
SEG52
SEG53
SEG54
SEG55
SEG56
GRID1
GRID2
GRID3
10
11
12
13
14
15
16
17
18
19
20
DISP
SEG39
SEG38
V
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
80797877767574737271706968676665646362
1
2
3
4
5
6
7
8
9
SEG25
SEG24
DISP
V
SEG23
SEG22
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
21222324252627282930313233343536373839
NC
DD
V
D-GND
DIM IN
CS
SYNC IN 1
SYNC IN 2
CLOCK
DATA IN
NC
OSC0
L-GND
M/S
DUP/TRI
D-GND
DIM OUT
SYNC OUT 2
SYNC OUT 1
NC
NC: No connection
80-pin Plastic QFP
(QFP80-P-1414-0.65-K)
40
SEG1
5/19
Page 6
¡ Semiconductor
PIN DESCRIPTIONS
ML9211
Symbol
QFP-1*
V
DISP
V
DD
65, 80 —
D-GND 24, 40 —
QFP-2*
63 78
25 —
22, 38
L-GND 33 —
SEG1 to 37
42 to 64,
66 to 79
40 to 62,
64 to 77
Type Description
23
31
79, 80,
Pin
SEG38 to 56 1 to 19 O
GRID1
GRID2 21 O
GRID3
CS 29 I
CLOCK 30 I
DATA IN 31 I
DUP/TRI 35 I
1 to 17
20 18
19
22 20
27
28
29
33
Power supply pins for VFD driver circuit.
These should be connected externally.
Power supply pin for logic drive.
D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the
logic circuit. These should be connected externally.
Segment (anode) signal output pins for a VFD tube. These pins can be directly
O
connected to the VFD tube. External circuit is not required.
£–5 mA
I
OH
Segment (anode) signal output pins for a VFD tube.These pins can be directly
connected to the VFD tube. External circuit is not required.
£–10 mA
I
OH
Inverted Grid signal output pins. For pre-driver, the external circuit is required.
£10 mA
I
OL
Chip select input pin.
Data is not transferred when CS is set to a Low level.
Shift clock input pin.
Serial data shifts at the rising edge of the CLOCK.
Serial data input pin (positive logic).
Data is input to the shift register at the rising edge of the CLOCK signal.
Duplex/Triplex operation select input pin.
Duplex (1/2 duty) operation is selected when this pin is set to V
DD
.
Triplex (1/3 duty) operation is selected when this pin is set to L-GND.
M/S 36 I
DIM IN 26 I
34
24
SYNC IN 1 27 25
SYNC IN 2 28
DIM OUT 39 O
26
37
Master/Slave mode select input pin.
Master mode is selected when this pin is set to V
DD
.
Slave mode is selected when this pin is set to L-GND.
Dimming pulse input.
When the slave mode is selected, connect this pin to the master side DIM
OUT pin at the slave mode. The pulse width of the all segment output are
controlled by a input pulse width of DIM IN.
When the master mode is selected, the input level of this pin is ignored.
Connect this pin to V
or L-GND at the master mode. The pulse width of the
DD
all grids and segment outputs are controlled by a built-in 10-bit dimming circuit.
Synchronous signal input.
When the slave mode is selected, connect these pins to the master side SYNC
I
OUT 1 and 2 pins.
When the master mode is selected, the input level of these pins are ignored.
Connect these pins to V
or L-GND at the master mode.
DD
Dimming pulse output.
Connect this pin to the slave side DIM IN pin.
6/19
Page 7
¡ Semiconductor
ML9211
Symbol
QFP-1*
SYNC OUT 1 38
SYNC OUT 2 37
QFP-2*
Type Description
36
35
Synchronous signal output.
O
Connect these pins to the slave side SYNC IN 1 and 2 pins.
RC oscillator connecting pins.
Pin
OSC0 34 I/O
32
Oscillation frequency depends on display tubes
to be used. For details, refer to ELECTRICAL
CHARACTERISTICS.
* QFP-1: QFP80-P-1420-0.80-BK
QFP-2: QFP80-P-1414-0.65-K
ABSOLUTE MAXIMUM RATING
Parameter Symbol Condition Ratings Unit
V
DISP
V
DD
V
IN
P
D
T
STG
I
O1
I
Output Current
O2
I
O3
I
O4
V
DD
OSC0
R
C
— –0.3 to +20 VDriver Supply Voltage
—VLogic Supply Voltage
—VInput Voltage
QFP80-P-1420-0.80-BK
Ta≥25°C
–0.3 to +6.5
–0.3 to V
760
DD
+0.3
mWPower Dissipation
QFP80-P-1414-0.65-K 630
—°CStorage Temperature
SEG1 to 37 mA
SEG38 to 56 mA
GRID1 to 3 mA
DIM OUT, SYNC OUT1, SYNC OUT2 mA
–55 to +150
–10.0 to +2.0
–20.0 to +2.0
–10.0 to +20.0
–2.0 to +2.0
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol
Driver Supply Voltage
Logic Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Clock Frequency
Oscillation Frequency R=10KW±5%, C=27pF±5% 2.6 3.3 4.0 MHz
V
DISP
V
V
V
f
f
OSC
DD
IH
IL
C
R=10KW±5%,
Frame Frequency
Operating Temperature
f
FR
T
OP
Condition Min. Typ. Max. Unit
— 8.0 13.0 18.0 V
— 4.5 5.0 5.5 V
All inputs except OSC0 0.8V
DD
—— V
All inputs except OSC0 — — 0.2V
— — — 2.0 MHz
211 269 325 Hz1/3 Duty
C=27pF±5%
1/2 Duty 317 403 488 Hz
— –40 — +85 °C
DD
V
7/19
Page 8
¡ Semiconductor
ELECTRICAL CHARACTERISTICS
DC Characteristics
V
IH
V
IL
I
IH
I
IL
OH1
OH2
OH3
OH4
OL1
OL2
OL3
OL4
DISP
DD
Applied pin
SEG1-37
SEG38-56
GRID1-3
SEG1-37
SEG38-56
GRID1-3
V
Parameter Symbol
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
V
V
High Level Output Voltage
V
V
V
V
Low Level Output Voltage
V
V
Supply Current
*1)
*1)
*1)
*1)
*2)
*2)
DISP
V
DD
Ta=–40 to +85°C,V
DISP
Condition Min. Max. Unit
— 0.8V
— — 0.2V
V
IH=VDD
=GND –1.0 +1.0 mA
V
IL
=–5mA
I
OH1
V
V
V
V
DISP
DD
DISP
DD
=9.5V
=4.5V
=9.5V
=4.5V
I
I
I
I
I
I
I
OH2
OH3
OH4
OL1
OL2
OL3
OL4
=–10mA
=–5mA
=–200mA
=500mA
=500mA
=10mA
=200mA
R=10KW±5%, C=27pF±5%,
no load
ML9211
=8.0 to 18.0V, VDD=4.5 to 5.5V
DD
–1.0 +1.0 mA
–0.8 — V
V
DISP
–0.8 — V
V
DISP
–0.8 — V
V
DISP
–0.8 — V
V
DD
— 2.0 V
— 2.0 V
— 2.0 V
— 0.8 V
— 100 mAI
— 5.0 mAI
—V
DD
V
*1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI
*2) DIM OUT, SYNC OUT 1, SYNC OUT 2
8/19
Page 9
¡ Semiconductor
AC Characteristics
ML9211
Parameter Symbol
Clock Frequency
Clock Pulse Width
Data Setup Time
Data Hold Time
CS Off Time
t
t
f
CW
t
DS
t
DH
CSL
Ta=–40 to +85°C,V
Condition Min. Max. Unit
C
— — 2.0 MHz
— 200 — ns
— 200 — ns
— 200 — ns
—20—ms
=8.0 to 18.0V, VDD=4.5 to 5.5V
DISP
CS Setup Time
(CS-Clock)
t
CSS
— 200 — ns
CS Hold Time
t
(Clock-CS)
CS Wait Time — 400 — ms
Output Slew Rate Time
Rise Time
V
DD
V
Off Time Mounted in a unit, VDD=0.0V 5.0 — ms
DD
CSH
t
RSOFF
t
t
t
PRZ
t
POF
R
F
=100pF
C
L
Mounted in a unit — 100 ms
— 200 — ns
=20% to 80% — 2.0 ms
t
R
=80% to 20% — 2.0 ms
t
F
TIMING DIAGRAM
l Data Input Timing
t
CS
CLOCK
DATA IN
l Reset Timing
V
DD
CS
CSS
t
DS
VALID VALID VALID VALID
t
PRZ
t
RSOFF
–0.8V
–0.2V
–0.8V
–0.2V
–0.8V
–0.2V
–0.8V
DD
DD
DD
DD
DD
DD
DD
t
CSL
1/f
C
t
t
DH
t
POF
CW
t
CW
t
CSH
–0.0V
–0.8V
DD
–0.0V
l Driver Output Timing
t
SEG1-56, GRID1-3
R
–0.8V
–0.2V
DISP
DISP
t
F
t
R
9/19
Page 10
¡ Semiconductor
ML9211
l Output Timing (Duplex Operation) *1bit time=4/f
(The dimming data is 1016/1024 in the master mode)
2048bit times (1 display cycle)
GRID1
GRID2
GRID3
SEG1-56
DIM OUT
SYNC OUT1
SYNC OUT2
1016bit times 1016bit times
1016bit times
1019bit times1019bit times 1019bit times
1019bit times1019bit times 1019bit times
1029bit times1019bit times 1019bit times
1019bit times1029bit times 1029bit times
OSC
V
DISP
8bit times8bit times8bit times
D-GND
V
DISP
D-GND
V
DISP
5bit times5bit times5bit times3bit times
5bit times5bit times5bit times
5bit times5bit times5bit times
5bit times5bit times5bit times
D-GND
V
DISP
D-GND
V
DD
L-GND
V
DD
L-GND
V
DD
L-GND
l Output Timing (Triplex Operation) *1bit time=4/f
(The dimming data is 1016/1024 in the master mode)
3072bit times (1 display cycle)
GRID1
GRID2
GRID3
SEG1-56
DIM OUT
SYNC OUT1
SYNC OUT2
1016bit times
1016bit times
1019bit times1019bit times 1019bit times
1019bit times1019bit times 1019bit times
1029bit times1019bit times 1019bit times
1019bit times1029bit times
OSC
8bit times
1016bit times
1019bit times
V
DISP
8bit times8bit times
D-GND
V
DISP
D-GND
V
DISP
5bit times5bit times5bit times3bit times
5bit times5bit times5bit times
5bit times5bit times5bit times
5bit times5bit times5bit times
D-GND
V
DISP
D-GND
V
DD
L-GND
V
DD
L-GND
V
DD
L-GND
10/19
Page 11
¡ Semiconductor
ML9211
l Output Timing (Duplex Operation) *1bit time=4/f
(The dimming data is 64/1024 in the master mode)
2048bit times (1 display cycle)
GRID1
GRID2
GRID3
SEG1-56
DIM OUT
SYNC OUT1
SYNC OUT2
64bit times 64bit times
960bit times960bit times
64bit times
67bit times
957bit times3bit times
67bit times
957bit times 957bit times
957bit times 957bit times 957bit times
67bit times
67bit times
957bit times 957bit times 957bit times
67bit times
1981bit times
957bit times 957bit times 957bit times
67bit times1981bit times
1981bit times
OSC
67bit times
67bit times
67bit times
960bit times
V
DISP
D-GND
V
DISP
D-GND
V
DISP
D-GND
V
DISP
D-GND
V
DD
L-GND
V
DD
L-GND
V
DD
L-GND
l Output Timing (Triplex Operation) *1bit time=4/f
(The dimming data is 64/1024 in the master mode)
3072bit times (1 display cycle)
GRID1
GRID2
GRID3
SEG1-56
DIM OUT
SYNC OUT1
SYNC OUT2
64bit times
67bit times
67bit times
67bit times
960bit times
64bit times
960bit times
957bit times3bit times
957bit times 957bit times
67bit times
957bit times 957bit times 957bit times
67bit times
957bit times 957bit times 957bit times
1981bit times
957bit times 957bit times 957bit times
67bit times1981bit times
OSC
64bit times
67bit times
67bit times
67bit times
67bit times
960bit times
V
DISP
D-GND
V
DISP
D-GND
V
DISP
D-GND
V
DISP
D-GND
V
DD
L-GND
V
DD
L-GND
V
DD
L-GND
11/19
Page 12
¡ Semiconductor
(
)
ML9211
FUNCTIONAL DESCRIPTION
Power-on Reset
When power is turned on, the ML9211 is initialized by the internal power-on reset circuit.
The status of the internal circuit after initialization is as follows:
• The contents of the shift registers and latches are set to "0".
• The digital dimming duty cycle is set to "0".
• All segment outputs are set to Low level.
• All grid outputs are set to High level.
Data Transfer Method
Data can be transferred between the rising edge and the next falling edge of chip select input.
The mode data, segment data and dimming data are written by a serial transfer method. The
serial data is input to the shift register at the rising edge of a shift clock pulse.
The mode data (M0 to M2) must be transferred after the segment data and dimming data
succeedingly.
When the chip select input falls, an internal LOAD signal is automatically generated and data is
loaded to the latches.
Function Mode
Function mode is selected by the mode data (M0 to M2). The relation between function mode and
mode data is as follows:
FUNCTION MODE OPERATING MODE
FUNCTION DATA
M0 M1 M2
0000 Segment Data for GRID1-3 Input
1001 Segment Data for GRID1 Input
0102 Segment Data for GRID2 Input
1103 Segment Data for GRID3 Input
0014 Digital Dimming Data Input
Segment Data Input [Function Mode: 0 to 3]
• ML9211 receives the segment data when function mode 0 to 3 are selected.
• The same segment data is transferred to the 3 segment data latches corresponding to GRID 1
to 3 at the same time when the function mode 0 is selected.
• The segment data is transferred to only one segment data latch corresponding to the specified
GRID when the function mode is 1, 2 or 3 is selected.
• Segment output (SEG1 to 56) becomes High level (lighting) when the segment data (S1 to S56)
is set to "1".
[Data Format]
Input Data : 59 bits
Segment Data : 56 bits
Mode Data : 3 bits
Bit
Input Data
1
S12S23S34S4
Segment Data (56bits) Mode Data
53
S5354S5455S5556S5657M058M159M2
3bits
12/19
Page 13
¡ Semiconductor
ML9211
[Bit correspondence between segment output and segment data]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S15
35
S35
16
S16
36
S36
17
S17
37
S37
18
S18
38
S38
19
S19
39
S39
20
S20
40
S40
SEG n
Segment data
SEG n
Segment data
SEG n
Segment data
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
21
22
23
24
25
26
27
28
29
30
31
32
33
34
S21
S22
S23
S24
S25
S26
S27
S28
S29
S30
S31
S32
S33
S34
41
S4142S4243S4344S4445S4546S4647S4748S4849S4950S5051S5152S5253S5354S5455S5556S56
Digital Dimming Data Input [Function Mode: 4]
• ML9211 receives the digital dimming data when function mode 4 is selected.
• The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid.
• The 10-bit digital dimming data is input from LSB.
[Data Format]
Input Data : 13 bits
Digital Dimming Data: 10 bits
Mode Data : 3 bits
Bit
Input Data
1
D12D23D34D4
5
D56D6
7
D78D89D910D1011M012M113M2
LSB MSB
Digital Dimming Data (10bits) Mode Data
(3bits)
Dimming Data (MSB)(LSB)
Duty Cycle
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
0/1024
1/1024
1015/1024
1016/1024
1016/1024
1016/1024
Master Mode
Master Mode is selected when M/S pin is set at High level. The master mode operation is as
follows:
• The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be
connected to L-GND or VDD.
• Brightness is adjusted by the internal digital dimming circuit.
• The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing
generator.
13/19
Page 14
¡ Semiconductor
ML9211
Slave Mode
Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows:
• The internal dimming circuit is ignored.
• The pulse width of SEG1 to 56 are controlled by the pulse width of DIM IN signal.
• The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2
signals.
• The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC
OUT1 and SYNC OUT2 are set at Low level.
[Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] [Correspondence between DIM IN and SEG1 to 56]
SYNC IN 1 SYNC IN 2 Segment Latch GRID
0 0 No No
1 0 Latch1 GRID1
0 1 Latch2 GRID2
1 1 Latch3 GRID3
DIM IN SEG1 to 56
0 Low
1 High
Note: Low: Lights OFF
High: Lights ON
14/19
Page 15
¡ Semiconductor
ML9211
15/19
APPLICATION CIRCUITS
1. Circuit for the duplex VFD tube with 128 segments (2 Grid ¥ 112 Anode)
ML9211
(MASTER)
V
DISP
V
DD
D-GNDL-GND
OSC 0
CLOCK
DATA IN
CS
DIM IN
SYNC IN 1
SYNC IN 2
M/S
DUP/TRI
DIM OUT
SYNC OUT 1
SYNC OUT 2
GRID2
GRID1
GRID3
SEG1
SEG56
ML9211
(SLAVE)
V
DISP
V
DD
D-GNDL-GND
OSC 0
CLOCK
DATA IN
CS
DIM IN
SYNC IN 1
SYNC IN 2
DIM OUT
SYNC OUT 1
SYNC OUT 2
GRID2
GRID1
GRID3
SEG1
SEG56
V
DD
Duplex VFD Tube
S110 S111 S112
S1 S2 S3
G1
G2
Microcontroller
V
DISP
V
DD
M/S
GND
DUP/TRI
V
DD
Ef
GND
GND
GND
R
C
V
DD
GND
R
C
V
DD
Page 16
¡ Semiconductor
ML9211
16/19
2. Circuit for the triplex VFD tube with 192 segments (3 Grid ¥ 112 Anode)
ML9211
(MASTER)
V
DISP
V
DD
D-GNDL-GND
OSC 0
CLOCK
DATA IN
CS
DIM IN
SYNC IN 1
SYNC IN 2
DUP/TRI
M/S
DIM OUT
SYNC OUT 1
SYNC OUT 2
GRID2
GRID1
GRID3
SEG1
SEG56
ML9211
(SLAVE)
V
DISP
V
DD
D-GNDL-GND
CLOCK
DATA IN
CS
DIM IN
SYNC IN 1
SYNC IN 2
DUP/TRI
M/S
DIM OUT
SYNC OUT 1
SYNC OUT 2
GRID2
GRID1
GRID3
SEG1
SEG56
V
DD
Triplex VFD Tube
S110 S111 S112S1 S2 S3
G1
G2
Microcontroller
V
DISP
V
DD
GND
Ef
GND
GND
GND
R
C
V
DD
OSC 0
GND
R
C
V
DD
G3
Page 17
¡ Semiconductor
[
]
ML9211
NOTES ON TURNING POWER ON/OFF
• Connect L-GND and D-GND externally to be an equal potential voltage.
• To avoid wrong operations, turn on the driver power supply after turning on the logic power
supply. Conversely, turn off the logic power supply after tuning off the driver power supply.
[Voltage]
V
DISP
V
DD
Time
17/19
Page 18
¡ Semiconductor
PACKAGE DIMENSIONS
QFP80-P-1420-0.80-BK
Mirror finish
ML9211
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.27 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
18/19
Page 19
¡ Semiconductor
QFP80-P-1414-0.65-K
Mirror finish
ML9211
(Unit : mm)
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.85 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
19/19
Page 20
E2Y0002-29-62
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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