5 ¥ 7 Dot Character ¥ 16-Digit ¥ 2-Line Display Controller/Driver with Character RAM
GENERAL DESCRIPTION
The ML9203-xx is a 5 ¥ 7 dot matrix type vacuum fluorescent display tube controller driver IC
which displays characters, numerics and symbols of a maximum of 16 digits ¥ 2 lines.
Dot matrix vacuum fluorescent display tube drive signals are generated by serial data sent from
a micro-controller. A display system is easily realized by internal ROM and RAM for character
display.
The ML9203-xx has low power consumption since it is made by CMOS process technology.
-01 is available as a general-purpose code.
Custom codes are provided on customer's request.
FEATURES
• Logic power supply (V
• VFD tube drive power supply (V
• VFD driver output current
(VFD driver output can be connected directly to the VFD tube. No pull-down resistor is
required.)
- Segment driver (SEGA1 to A35, SEGB1 to B35)
Only one driver output is high: –5 mA (V
All the driver outputs are high: –350 mA (V
- Segment driver (ADA, ADB): –20 mA (V
- Grid driver (COM1 to 16): –50 mA (V
• Content of display
SEGA1 to SEGA35 and ADA
- CGROM_A 5¥7 dots: 240 types (character data)
- CGRAM_A 5¥7 dots: 16 types (character data)
- ADRAM_A 16 (display digit) ¥ 1 bit (symbol data; can be used for a cursor.)
- DCRAM_A 16 (display digit) ¥ 8 bits(register for character data display)
SEGB1 to SEGB35 and ADB
- CGROM_B 5¥7 dots: 240 types (character data)
- CGRAM_B 5¥7 dots: 16 types (character data)
- ADRAM_B 16 (display digit) ¥ 1 bit (symbol data; can be used for a cursor.)
- DCRAM_B 16 (display digit) ¥ 8 bits(register for character data display)
• Display control function
- Display digit: 1 to 16 digits
- Display duty (brightness adjustment): 0 to 1024 stages
- All lights ON/OFF
• 3 interfaces with microcontroller: DA, CS, CP (4 interfaces when RESET is added)
When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously,
addresses are internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data
for the 2nd and later bytes.
Note: The test mode is used for inspection before shipment.
It is not a user function.
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¡ SemiconductorML9203-xx
Positional Relationship Between SEGn and ADn (one digit)
C0
SEGA1
C5
SEGA6
C10
SEGA11
C15
SEGA16
C20
SEGA21
C25
SEGA26
C30
SEGA31
C0
SEGB1
C5
SEGB6
C10
SEGB11
C15
SEGB16
C20
SEGB21
C25
SEGB26
C30
SEGB31
C1
SEGA2
C6
SEGA7
C11
SEGA12
C16
SEGA17
C21
SEGA22
C26
SEGA27
C31
SEGA32
C1
SEGB2
C6
SEGB7
C11
SEGB12
C16
SEGB17
C21
SEGB22
C26
SEGB27
C31
SEGB32
C0
C2
SEGA3
C7
SEGA8
C12
SEGA13
C17
SEGA18
C22
SEGA23
C27
SEGA28
C32
SEGA33
C0
C2
SEGB3
C7
SEGB8
C12
SEGB13
C17
SEGB18
C22
SEGB23
C27
SEGB28
C32
SEGB33
ADA
C3
SEGA4
C8
SEGA9
C13
SEGA14
C18
SEGA19
C23
SEGA24
C28
SEGA29
C33
SEGA34
ADB
C3
SEGB4
C8
SEGB9
C13
SEGB14
C18
SEGB19
C23
SEGB24
C28
SEGB29
C33
SEGB34
Corresponds to the 2nd byte of the ADRAM_A data write command.
C4
SEGA5
C9
SEGA10
C14
SEGA15
C19
SEGA20
C24
SEGA25
C29
SEGA30
C34
SEGA35
Corresponds to the 6th byte of the CGRAM_A data write command.
Corresponds to the 5th byte of the CGRAM_A data write command.
Corresponds to the 4th byte of the CGRAM_A data write command.
Corresponds to the 3rd byte of the CGRAM_A data write command.
Corresponds to the 2nd byte of the CGRAM_A data write command.
Corresponds to the 2nd byte of the ADRAM_B data write command.
C4
SEGB5
C9
SEGB10
C14
SEGB15
C19
SEGB20
C24
SEGB25
C29
SEGB30
C34
SEGB35
COMn
Corresponds to the 6th byte of the CGRAM_B data write command.
Corresponds to the 5th byte of the CGRAM_B data write command.
Corresponds to the 4th byte of the CGRAM_B data write command.
Corresponds to the 3rd byte of the CGRAM_B data write command.
Corresponds to the 2nd byte of the CGRAM_B data write command.
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Data Transfer Method and Command Write Method
Display control command and data are written by an 8-bit serial transfer.
Write timing is shown in the figure below.
Setting the CS pin to "Low" level enables a data transfer.
Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first).
As shown in the figure below, data is read by the shift register at the rising edge of the shift clock,
which is input into the CP pin. If 8-bit data is input, internal load signals are automatically
generated and data is written to each register and RAM.
Therefore it is not necessary to input load signals from the outside.
Setting the CS pin to "High" disables data transfer. Data input from the point when the CS pin
changes from "High" to "Low" is recognized in 8-bit units.
CS
CP
DA
When data is written to DCRAM*
B0
LSB
Command and address data
t
DOFF
B1 B2 B3 B4 B5 B6 B7B0 B1 B2 B3 B4 B5 B6 B7
1st byte
MSB
LSBMSB
2nd byte
B0 B1 B2 B3 B4 B5 B6 B7
LSBMSB
2nd byte
Character code data of the
next addressCharacter code data
t
CSH
*When data is written to RAM (DCRAM, ADRAM, CGRAM) continuously, addresses are
internally incremented automatically.
Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and later
bytes.
Reset Function
Reset is executed when the RESET pin is set to "L", (when turning power on, for example) and
initializes all functions.
Initial status is as follows.
• Address of each RAM.................. address "00"H
• Data of each RAM ........................ All contents are undefined
• Segment output ............................ All segment outputs go "Low"
• AD output ..................................... All AD outputs go "Low"
Please set again according to "Setting Flowchart" after reset.
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)
Description of Commands and Functions
1. DCRAM data write
(Specifies the address of DCRAM and writes the character code of CGROM and CGRAM.)
DCRAM (Data Control RAM) has a 4-bit address to store character code of CGROM and
CGRAM.
The character code specified by DCRAM is converted to a 5¥7 dot matrix character pattern via
CGROM or CGRAM.
(The DCRAM can store 16 characters.)
[Command format]
0: Select DCRAM_A
1: Select DCRAM_B
: selects DCRAM data write mode and specifies DCRAM
address
(Ex: Specifies DCRAM address 0H)
: specifies character code of CGROM and CGRAM
written into DCRAM address 0H
1st byte
(1st)
2nd byte
(2nd)
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
X0 X1 X2 X3100 0/1
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C1 C2 C3 C4 C5 C6 C7
To specify the character code of CGROM and CGRAM continuously to the next address, specify
only character code as follows.
The addresses of DCRAM are automatically incremented. Specification of an address is
unnecessary.
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LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(3rd)
C0 C1 C2 C3 C4 C5 C6 C7
LSBMSB
: specifies character code of CGROM and CGRAM
(written into DCRAM address 1H)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(4th)
C0 C1 C2 C3 C4 C5 C6 C7
LSBMSB
: specifies character code of CGROM and CGRAM
(written into DCRAM address 2H)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(17th)
C0 C1 C2 C3 C4 C5 C6 C7
LSBMSB
: specifies character code of CGROM and CGRAM
(written into DCRAM address FH)
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(18th)
C0 C1 C2 C3 C4 C5 C6 C7
: specifies character code of CGROM and CGRAM
(DCRAM address 0H is rewritten)
X0 (LSB) to X3 (MSB): DCRAM addresses (4 bits: 16 characters)
C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters)
2. CGRAM data write
(Specifies the addresses of CGRAM and writes character pattern data.)
CGRAM (Character Generator RAM) has a 4-bit address to store 5¥7 dot matrix character
patterns.
A character pattern stored in CGRAM can be displayed by specifying the character code
(address) by DCROM.
The address of CGRAM is assigned to 00H to 0FH. (All the other addresses are the CGROM
addresses.)
(The CGRAM can store 16 types of character patterns.)
[Command format]
1st byte
(1st)
2nd byte
(2nd)
3rd byte
(3rd)
4th byte
(4th)
5th byte
(5th)
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
X0 X1 X2 X3010 0/1
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
C0 C5 C10 C15 C20 C25 C30
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
C1 C6 C11 C16 C21 C26 C31
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
C2 C7 C12 C17 C22 C27 C32
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
C3 C8 C13 C18 C23 C28 C33
*
*
*
*
0: Select CGRAM_A
1: Select CGRAM_B
: selects CGRAM data write mode and specifies
CGRAM address.
(Ex: specifies CGRAM address 00H)
: specifies 1st column data
(rewritten into CGRAM address 00H)
: specifies 2nd column data
(rewritten into CGRAM address 00H)
: specifies 3rd column data
(rewritten into CGRAM address 00H)
: specifies 4th column data
(rewritten into CGRAM address 00H)
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
6th byte
(6th)
C4 C9 C14 C19 C24 C29 C34
: specifies 5th column data
*
rewritten into CGRAM address 00H)
To specify character pattern data continuously to the next address, specify only character pattern
data as follows.
The addresses of CGRAM are automatically incremented. Specification of an address is
unnecessary.
The 2nd to 6th byte (character pattern data) are regarded as one data item, so 300 ns is sufficient
for t
time between bytes.
DOFF
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¡ SemiconductorML9203-xx
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
2nd byte
(7th)
6th byte
(11th)
C0 C5 C10 C15 C20 C25 C30
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
C4 C9 C14 C19 C24 C29 C34
: specifies 1st column data
*
(rewritten into CGRAM address 01H)
: specifies 5th column data
*
(rewritten into CGRAM address 01H)
X0 (LSB) to X3 (MSB): CGRAM addresses (3 bits: 8 characters)
C0 (LSB) to C34 (MSB): Character pattern data (35 bits: 35 outputs per digit)
* : Don't care
[CGROM addresses and set CGRAM addresses]
Refer to ROM code tables.
HEX
0
1
2
3
4
5
6
7
X0
X1 X2
000
100
010
110
001
101
011
111
X3
CGROM address
RAM00(00000000B)
0
RAM01(00000001B)
0
RAM02(00000010B)
0
RAM30(00000011B)
0
RAM04(00000100B)
0
RAM05(00000101B)
0
RAM06(00000110B)
0
RAM70(00000111B)
0
HEX
8
9
A
B
C
D
E
F
X0
X1 X2
000
100
010
110
001
101
011
111
X3
CGROM address
RAM08(00001000B)
1
RAM09(00001001B)
1
RAM0A(00001010B)
1
RAM0B(00001011B)
1
RAM0C(00001100B)
1
RAM0D(00001101B)
1
RAM0E(00001110B)
1
RAM0F(00001111B)
1
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Positional relationship between the output area of CGRAM
C0
C1
C2
C3
C8
C4
SEGn5
C9
SEGn10
C14
SEGn15
C19
SEGn20
C24
SEGn25
C29
SEGn30
C34
SEGn35
area that corresponds to 2nd byte (1st column)
(Input 1000001*B)
area that corresponds to 3rd byte (2nd column)
(Input 1100011*B)
area that corresponds to 4th byte (3rd column)
(Input 1010101*B)
area that corresponds to 5th byte (4th column)
(Input 1001001*B)
area that corresponds to 6th byte (5th column)
(Input 1100011*B)
C5
SEGn6
C10
SEGn11
C15
SEGn16
C20
SEGn21
C25
SEGn26
C11
SEGn12
C16
SEGn17
C21
SEGn22
C7
SEGn8
C17
SEGn18
C27
SEGn28
C8
SEGn9
C13
SEGn14
C23
SEGn24
C28
SEGn29
C14
SEGn15
C19
SEGn20
C24
SEGn25
SEGn1
C5
SEGn6
C10
SEGn11
C15
SEGn16
C20
SEGn21
C25
SEGn26
C30
SEGn31
SEGn2
C6
SEGn7
C11
SEGn12
C16
SEGn17
C21
SEGn22
C26
SEGn27
C31
SEGn32
SEGn3
C7
SEGn8
C12
SEGn13
C17
SEGn18
C22
SEGn23
C27
SEGn28
C32
SEGn33
SEGn4
SEGn9
C13
SEGn14
C18
SEGn19
C23
SEGn24
C28
SEGn29
C33
SEGn34
Note:CGROM_A and CGROM_B (Character Generator ROM A, B) have an 8-bit address to
generate 5¥7 dot matrix character patterns.
Each of CGROM_A and CGROM_B can store 240 types of character patterns.
The contents of CGROM_A and CGROM_B can be set separately.
General-purpose code -01 is available (see ROM code tables) and custom codes are
provided on customer's request.
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¡ SemiconductorML9203-xx
(
)
(
)
3. ADRAM data write
(specifies address of ADRAM and writes symbol data)
ADRAM (Additional Data RAM) has a 1-bit address to store symbol data.
Symbol data specified by ADRAM is directly output without CGROM and CGRAM.
(The ADRAM can store 1 type of symbol patterns for each digit.)
The terminal to which the contents of ADRAM are output can be used as a cursor.
[Command format]
0: Select ADRAM_A
1: Select ADRAM_B
: selects ADRAM data write mode and specifies ADRAM
address
(Ex: specifies ADRAM address 0H)
: sets symbol data
written into ADRAM address 0H
1st byte
(1st)
2nd byte
(2nd)
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
X0 X1 X2 X3110 0/1
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
C0*******
To specify symbol data continuously to the next address, specify only character data as follows.
The address of ADRAM is automatically incremented. Specification of addresses is unnecessary.
5. Display duty set
(writes display duty value to duty cycle register)
Display duty adjusts brightness in 1024 stages using 10-bit data.
When power is turned on or when the RESET signal is input, the duty cycle register value is
"0". Always execute this instruction before turning the display on, then set a desired duty
value.
[Command format]
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
2nd byte
2nd
D0D1**1010
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
D2 D3 D4 D5 D6 D7 D8 D9
: selects display duty set mode and sets duty value (lower 2 bits)
: sets duty value (upper 8 bits)
D0 (LSB) to D9 (MSB) : Display duty data (10 bits: 1024 stages)
* : Don't care
[Relation between setup data and controlled COM duty]
The state when power is turned on or when RESET signal is input.
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6. Number of digits set
(writes the number of display digits to the display digit register)
The number of digits set can display 1 to 16 digits using 4-bit data.
When power is turned on or when a RESET signal is input, the number of digit register value
is "0". Always execute this instruction to change the number of digits before turning the
dispaly on.
[Command format]
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
K0K1K2K30110
: selects the number of digit set mode and specifies
the number of digit value
K0 (LSB) to K3 (MSB) : Number of digit data (4 bits: 16 digits)
* : Don't care
[Relation between setup data and controlled COM]
HEXK0K1K2
0000COM1 to 16
1100COM1
2010COM1 to 2
3110COM1 to 3
4001COM1 to 4
5101COM1 to 5
6011COM1 to 6
7111COM1 to 7
The state when power is turned on or when RESET signal is input.
Number of
K3
digits of COM
0
0
0
0
0
0
0
0
HEXK0K1K2
0000COM1 to 8
1100COM1 to 9
2010COM1 to 10
3110COM1 to 11
4001COM1 to 12
5101COM1 to 13
6011COM1 to 14
7111COM1 to 15
Number of
K3
digits of COM
1
1
1
1
1
1
1
1
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¡ SemiconductorML9203-xx
7. All display lights ON/OFF set
(turns all dispaly lights ON or OFF)
All display lights ON is used primarily for display testing.
All display lights OFF is primarily used for display blink and to prevent malfunction when
power is turned on.
[Command format]
LSBMSB
B0 B1 B2 B3 B4 B5 B6 B7
1st byte
LH**1110
L, H: display operation data
*: Don't care
: selects all display lights ON or OFF mode
[Set data and display state of SEG and AD]
H
0
0
0
1
1
0
1
1
Display state of SEG and ADL
Normal display
Sets all outputs to Low
Sets all outputs to High
Sets all outputs to High
(The state when power is applied or when RESET is input.)
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¡ SemiconductorML9203-xx
Setting Flowchart
(Power applying included)
Apply V
Apply V
DD
DISP
All display lights OFF
Number of digits setting
Display duty setting
Select a RAM to be used
Status of all outputs by RESET
signal input
DCRAM_A or B
Data write mode
(with address setting)
Address is automatically
incremented
Address is automatically
incremented
DCRAM_A or B
Character code
DCRAM
NONONO
Is character code
write ended?
YESYESYES
YES
CGRAM_A or B
Data write mode
(with address setting)
CGRAM_A or B
Character code
CGRAM
Is character code
write ended?
Another RAM to
be set?
NO
Releases all display lights
OFF mode
ADRAM_A or B
Data write mode
(with address setting)
Address is automatically
incremented
ADRAM_A or B
Character code
ADRAM
Is character code
write ended?
End of setting
Display operation mode
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¡ SemiconductorML9203-xx
Power-off Flowchart
Display operation mode
Turn off V
Turn off V
DISP
DD
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¡ SemiconductorML9203-xx
APPLICATION CIRCUIT
5¥7-dot matrix fluorescent display tube
ANODE
(SEGMENT)
2
ADA,ADBV
V
DD
Output Ports
V
DD
MCU
GND
R
C
Crystal oscillator or ceraloc oscillator
DD
CS
CP
DA
RESET
ANODE
(SEGMENT)
MSM9203-xx
OSC0 OSC1L-GNDD-GND
ANODE
(SEGMENT)
GRID
(DIGIT)
163535
COM1-16SEGA1-A35SEGB1-B35V
DISP
ZD
R
2
V
DISP
Notes: 1. The VDD value depends on the power supply voltage of the microcontroller used.
Adjust the values of the constants and C input to RESET to the power supply voltage
used.
2. The V
value depends on the fluorescent display tube used. Adjust the values of
DISP
the constants R2 and ZD to the power supply voltage used.
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¡ SemiconductorML9203-xx
Reference data
The figure below shows the relationship between the V
voltage and the output current of
DISP
each driver.
Take care that the total power consumption to be used does not exceed the power dissipation.
(mA)
–60
–50
–40
–30
[Output Current]
–20
–10
[V
Voltage-Output Current of Each Driver]
DISP
T.B.D
0
0 1020304050
[V
Voltage]
DISP
(V)
7060
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¡ SemiconductorML9203-xx
ML9203-01 CGROM_A Code
00000000B (00H) to 00000111B (0FH) are the CGRAM_A addresses.
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
1.29 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type
packages, which are very susceptible to heat in reflow mounting and humidity absorbed in
storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person
on the product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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Page 31
E2Y0002-29-11
NOTICE
1.The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2.The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3.When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4.Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5.Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6.The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7.Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8.No part of the contents cotained herein may be reprinted or reproduced without our prior
permission.
9.MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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