Page 1
E2B0055-19-61
Preliminary
¡ Semiconductor ML9044
This version: Jun. 1999
¡ Semiconductor
ML9044
DOT MATRIX LCD CONTROLLER DRIVER
GENERAL DESCRIPTION
The ML9044 used in combination with an 8–bit or 4–bit microcontroller controls the operation
of a character type dot matrix LCD.
FEATURES
• Easy interfacing with 8–bit or 4–bit microcontroller
• Switchable between serial and parallel interfaces
• Dot–matrix LCD controller/driver for a small (5 ¥ 7 dots) or large (5 ¥ 10 dots) font
• Built–in circuit allowing automatic resetting at power–on
• Built–in 17 common signal drivers and 120 segment signal drivers
• Built–in character generation ROM capable of generating 160 small characters (5 ¥ 7 dots) or
32 large characters (5 ¥ 10 dots)
• Creation of character patterns by programming: up to 8 small character patterns (5 ¥ 8 dots) or
up to 4 large character patterns (5 ¥ 11 dots)
• Built–in RC oscillation circuit using external or internal resistors
• Program–selectable duties: 1/9 duty (1 line: 5 ¥ 7 dots + cursor + arbitrator), 1/12 duty (1 line:
5 ¥ 10 dots + cursor + arbitrator), or 1/17 duty (2 lines: 5 ¥ 7 dots + cursor + arbitrator)
• Built–in bias dividing resistors to drive the LCD
• Bi–directional transfer of segment outputs
• Bi–directional transfer of common outputs
• Equipped with a 120–dot arbitrator
• Display shifting on each line
• Built–in contrast control circuit
• Built–in voltage multiplier circuit
• Chip (Gold Bump) Product name : ML9044CVWA
1/54
Page 2
¡ Semiconductor ML9044
2/54
BLOCK DIAGRAM
V
DD
GND
OSC
1
OSC
R
OSC
2
RS1
RS0
R/W
E
CS
P/S
SHT
SI
SO
DB
0
to
DB
3
4
DB
4
to
DB
7
4
T
1
T
2
T
3
V
1
V
2
V
3B
V
3A
V
4
V
5
V
5IN
Timing
generator
8
I/O
buffer
8
Instruction
register
(IR)
Instruction
decoder
(ID)
7
8
8
8
Data
register
(DR)
5
COM
1
SEG
1
COM
17
Test
circuit
LCD
bias
voltage
dividing
circuit
5
8
Busy flag
(BF)
Expansion
Instruction
register (ER)
Voltage
multiplier
circuit
Address
counter
(ADC)
Expansion
Instruction
decoder (ED)
Character
generator
ROM
(CGROM)
8
8
Display
data RAM
(DDRAM)
Arbitrator
RAM
(ABRAM)
Character
generator
RAM
(CGRAM)
Cursor
blink
controller
5
5
CSR
17-bit
shift
register
Common
signal
driver
Rarallel-
serial
converter
120-bit shift register
120-bit latch
Segment Signa - driver
SEG
120
SSR
BEB
VCCVCV
IN
Page 3
¡ Semiconductor ML9044
I/O CIRCUITS
V
DD
P
N
Applied to pins E, SSR, CSR, BEB, CS
P/S, SHT, and SI
V
DD
V
DD
P
V
DD
P
N
Applied to pins T1, T2, and T
3
V
DD
V
DD
P
N
Applied to pins R/W, RS1, and RS
0
P
V
DD
N
P
V
DD
Applied to pins DB0 to DB7
V
DD
PP
N
Applied to pins SO
N
Output Enable signal
Output Enable signal
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Page 4
¡ Semiconductor ML9044
PIN DESCRIPTIONS
Symbol Description
R/W
RS0, RS
1
E
DB0 to DB
DB4 to DB
OSC
1
OSC
2
OSC
R
COM1 to COM
SEG1 to SEG
3
7
17
120
The input pin with a pull–up resistor to select Read (“H”) or Write (“L”) in the Parallel
I/F Mode.
This pin should be open in the Serial I/F Mode.
The input pins with a pull–up resistor– to select a register in the Parallel I/F Mode.
RS
1
RS
0
Name of register
H H Data register
H L Instruction register
L L Expansion Instruction register
This pin should be open in the Serial I/F Mode.
The input pin for data input/output between the CPU and the ML9044 and for activating
instructions in the Parallel I/F Mode.
This pin should be open in the Serial I/F Mode.
The input/output pins to transfer data of lower–order 4 bits between the CPU and the
ML9044 in the Parallel I/F Mode. Each pin is equipped with a pull–up resistor. These 4
lines are not used for the 4–bit interface.
This pin should be open in the Serial I/F Mode.
The input/output pins to transfer data of upper 4 bits between the CPU and the ML9044
in the Parallel I/F Mode. Each pin is equipped with a pull–up resistor.
This pin should be open in the Serial I/F Mode.
The clock oscillation pins required for LCD drive signals and the operation of the
ML9044 by instructions sent from the CPU.
To input external clock, the OSC
pin should be used. The OSCR and the OSC2 pins
1
should be open.
To start oscillation with an external resistor, the resistor should be connected between
the OSC
To start oscillation with an internal resistor, the OSC
short–circuited outside the ML9044. The OSC
and OSC2 pins. The OSCR pin should be open.
1
2
pin should be open.
1
and OSCR pins should be
The LCD common signal output pins.
For 1/9 duty, non–selectable voltage waveforms are output via COM
1/12 duty, non–selectable voltage waveforms are output via COM
to COM17. For
10
to COM17.
13
The LCD segment signal output pins.
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Page 5
¡ Semiconductor ML9044
Symbol Description
CSR
The input pin to select the transfer direction of the common signal output data.
Refer to the Expansion Instruction Codes section about the AS bit.
CSR duty AS bit shift direction arbitrator's common pin
L 1/9 L COM1 Æ COM9 COM9
L 1/9 H COM2 Æ COM9, COM1 COM1
L 1/12 L COM1 Æ COM12 COM12
L 1/12 H COM2 Æ COM12, COM1 COM1
L 1/17 L COM1 Æ COM17 COM17
L 1/17 H COM2 Æ COM17, COM1 COM1
H 1/9 L COM9 Æ COM1 COM1
H 1/9 H COM8 Æ COM1, COM9 COM9
H 1/12 L COM12 Æ COM1 COM1
H 1/12 H COM11 Æ COM1, COM12 COM12
H 1/17 L COM17 Æ COM1 COM1
H 1/17 H COM16 Æ COM1, COM17 COM17
SSR
V1, V2, V3A, V3B, V
BEB
V
IN
V5, V
5IN
The input pin to select the transfer direction of the segment signal output data.
“L”: Data transfer from SEG
“H”: Data transfer from SEG
The pins to output bias voltages to the LCD.
4
For 1/4 bias : The V
For 1/5 bias : The V
and V3B pins are shorted.
2
3A
to SEG
1
120
120
to SEG
1
and V3B pins are shorted.
The input pin to enable or disable the voltage multiplier circuit.
“L” disables the voltage multiplier circuit. “H” enables the voltage multiplier circuit.
The voltage multiplier circuit doubles the input voltage V
and outputs it to the V
IN
The voltage multiplier circuit can be used only when generating a level lower than GND.
The pin to input voltage to the voltage multiplier.
The pins to supply the LCD drive voltage.
The LCD drive voltage is supplied to the V
pin when the voltage multiplier is not used
5
(BEB = 0) and the internal contrast adjusting circuit is also not used. At this time, the
V
pin should be open.
5IN
The LCD drive voltage is supplied to the V
pin when the voltage multiplier is not used
5IN
(BEB = 0) but the internal contrast adjusting circuit is used. At this time, the V
should be open.
When the voltage multiplier is used (BEB = 1), the V
multiplied voltage is output to the V
pin). In this case, the internal contrast adjusting
5IN
and V5 pins should be open (the
5IN
circuit is used automatically.
pin
5
5IN
pin.
V
C
V
CC
The pin to connect the positive pin of the capacitor for the voltage multiplier.
The pin to connect the negative pin of the capacitor used for the voltage multiplier.
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Page 6
¡ Semiconductor ML9044
Symbol Description
T1, T2, T
V
DD
GND
P/S
CS
SHT
3
The input pins for test circuits (normally open). Equipped with a pull–down resistor.
The power supply pin.
The ground level input pin.
The input pin to select the parallel or serial interface.
“L” selects the parallel interface.
“H” selects the serial interface.
The pin to enable this IC in the serial I/F mode.
“L” enables this IC.
“H” disables this IC.
This pin should be open in the parallel I/F mode.
The pin to input shift clock in the serial I/F mode.
Data inputting to the SI pin is carried out synchronizing with the rising edge of this
clock signal.
Data outputting from the SO pin is carried out synchronizing with the falling edge of this
clock signal.
This pin should be open in the parallel I/F mode.
SI
SO
The pin to input DATA in the serial I/F mode.
Data inputting to this pin is carried out synchronizing with the rising edge of the SHT
signal.
This pin should be open in the parallel I/F mode.
The pin to output DATA in the serial I/F mode.
Data inputting to this pin is carried out synchronizing with the falling edge of the SHT
signal.
This pin should be open in the parallel I/F mode.
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Page 7
¡ Semiconductor ML9044
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Condition Rating Unit Applicable pins
Supply Voltage V
, V2, V3,
V
LCD Driving Voltage
1
V
4
Input Voltage V
Storage Temperature T
DD
, V
STG
5
I
Ta = 25°C –0.3 to +6.5 V VDD – GND
Ta = 25°C VDD – 7.5 to VDD+0.3 V
Ta = 25°C –0.3 to VDD+0.3 V
— –55 to +125 °C —
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Condition Range Unit Applicable pins
Supply Voltage V
VDD–V
LCD Driving Voltage
(See Note)
Input Voltage V
Operating Temperature T
DD
5
IN
op
— 2.5 to 5.5 V VDD–GND
— 2.8 to 7.0 V
BEB = 1
— –40 to +85 °C —
V
DD
V
–1.40 to
–3.5
DD
(GND = 0V)
V
, V4, V5, V
1
, V3A, V
V
2
3B
5IN
,
R/W, E, SHT, CSR,
P/S, SSR, SI, RS
, BEB, CS,
RS
1
to T3, DB0 to DB7,
T
1
V
IN
0
(GND = 0V)
V
DD–V5
(V
)
5
IN
VV
DD–VIN
,
Note: This voltage should be applied across VDD and V5. The following voltages are output
to the V1, V2, V3A (V3B) and V4 pins:
• 1/4 bias
V1 = {VDD–(VDD–V
V2 = V3B= {VDD–(VDD–V
V4 = {VDD–3 ¥ (VDD–V
)/4} ±0.15V
5
)/2} ±0.15V
5
)/4 } ±0.15V
5
• 1/5 bias
V1 = {VDD–(VDD–V
V2 = {VDD–2 ¥ (VDD–V
V3A = V3B= {VDD–3 ¥ (VDD–V
V4 = {VDD–4 ¥ (VDD–V
)/5} ±0.15V
5
)/5} ±0.15V
5
)/5} ±0.15V
5
)/5} ±0.15V
5
The voltages at the V1, V2, V3A (V3B), V4 and V5 pins should satisfy
VDD>V1>V2>V3A(V3B)>V4>V5.
(Higher ¨Æ Lower)
* Do not apply short–circuiting across output pins and across an output pin and an
input/output pin or the power supply pin in the output mode.
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Page 8
¡ Semiconductor ML9044
ELECTRICAL CHARACTERISTICS
DC Characteristics
(GND = 0V, VDD = 2.5V to 5.5V, Ta = –40 to +85°C)
Parameter Symbol Condition Min Typ Max Unit Applicable pin
“H” Input Voltage 1
“L” Input Voltage 1
V
IH1
V
IL1
— 0.8V
–0.3 — 0.2V
—VDDV
DD
DD
R/W, RS0, RS1,
E, DB
to DB
0
SHT, P/S, SI, CS
“H” Input Voltage 2
“L” Input Voltage 2
“H” Output Voltage 1
“L” Output Voltage 1
“H” Output Voltage 2
“L” Output Voltage 2
COM Voltage
Drop
SEG Voltage
Drop
Input Leakage
V
IH2
V
IL2
V
OH1IOH
V
OL1IOL
V
OH2IOH
V
OL2IOL
V
CHIOCH
V
CMHIOCMH
V
CMLIOCML
V
CLIOCL
V
SHIOSH
V
SMHIOSMH
V
SMLIOSML
V
SLIOSL
| IIL |
VDD = 5V, VIN = 5V or 0V
= –0.1mA 0.75V
= +0.1mA — — 0.2V
= –13mA 0.9V
= +13mA — — 0.1V
= –4mAV
= +4mAV
= –4mAV
= +4mA
Current
Input Current 1 | II1| VDD =
VDD =
— 0.8V
VDD –V5 = 5V
= ±4mA
= ±4mA
V
– V5 = 5V
DD
= ±4mA
= ±4mA
5V, V
=
GND 10 25 61 mA
I
N
5V, V
=
VDD,
I
N
Note 1
Note 1
—VDDV
DD
–0.3 — 0.2V
—— V
DD
—— V
DD
– 0.3 V
DD
DD
DD
DD
DD
V1 – 0.3 V1 + 0.3
V4 – 0.3 V4 + 0.3
5
– 0.3 V
DD
V5 + 0.3
DD
V2 – 0.3 V2 + 0.3
V3 – 0.3 V3 + 0.3
V
5
V5 + 0.3
— — 1.0 mA
— — 2.0
OSC
SSR, CSR, BEB
DB
0
OSC
V
COM1 to COM
V
SEG1 to SEG
E, SSR, CSR, BEB,
SHT, P/S, CS, SI
R/W, RS0, RS
DB0 to DB7, SO
,
1
to DB7, SO
2
Excluding current flowing
through the pull-up resistor
and the output driving MOS
Input Current 2 | II2| VDD =
VDD =
5V, V
5V, V
=
V
I
N
DD
=
VDD,
I
N
15 45 105 mA
— — 2.0
T
1
, T2, T
Excluding current flowing
through the pull-down resistor
Supply Current I
LCD Bias Resistor
VDD = 5V Note 2
DD
R
LB
— — 1.2 mA
4.0 kW
VDD – GND
V
, V1, V
DD
V3A, V3B, V4, V
Oscillation Frequency of
External Resistor Rf
Oscillation Frequency of
Internal Resistor Rf
Clock Input
Frequency
Input Clock Duty
Input Clock Rise Time
External Clock
Input Clock Fall Time
f
f
f
Rf = 120kW±2% Note 3
osc1
OSC1: Open
osc2
OSC2 and OSCR: Short-circuited
OSC2, OSCR: Open
f
in
Input from OSC
duty
f
rf
f
ff
175 270 350 kHz
Note 4
140 270 480 kHz
125 480 kHz
1
Note 5 45 50 55 %
Note 6 — — 0.2 mS
Note 6 — — 0.2 mS
OSC1, OSC
OSC1, OSC2,
OSC
R
OSC
1
7
17
120
1
3
2
5
2
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Page 9
¡ Semiconductor ML9044
(GND = 0V, VDD = 2.5V to 5.5V, Ta = –40 to +85°C)
Parameter Symbol Condition Min Typ Max Unit Applicable pin
Control Range of
LCD Driving
Voltage (by internal
variable resistor)
Bias Voltage for Driving
LCD by External Input
Voltage Multiplier
Output Voltage
Voltage Multipler
Input Voltage
V
LCD
MAX
V
LCD
MIN
V
LCD1VDD
V
LCD2
V5OUT VDD = 3V, VIN = 0V
V
IN
= 5V, 1/5 bias
V
DD
V
= 0V
5IN
V
= 5V, 1/5 bias
DD
= 0V
V
5IN
– V5 2.8 — 7.0 V
Note 7
1/5
bias
1/4
bias 2.8 — 7.0
BEB = H
TBD —
VDD –
2VIN—
— TBD
VDD –2V
+1.2V
VDD/2 V
– V
V
DD
5
V
5
V
IN
V5, V
V
IN
5IN
9/54
Page 10
¡ Semiconductor ML9044
Note 1: Applied to the voltage drop occurring between any of the VDD, V1, V4 and V5 pins and
any of the common pins (COM1 to COM17) when the current of 4mA flows in or flows
out at one common pin.
Also applied to the voltage drop occurring between any of the VDD, V2, V3A (V3B) and
V5 pins and any of the segment pins (SEG1 to SEG
) when the current of 4mA flows
120
in or flows out at one common pin.
The current of 4mA flows out when the output level is VDD or flows in when the output
level is V5.
Note 2: Applied to the current flowing into the VDD pin when the external clock (f
270 kHz) is fed to the internal Rf oscillation or OSC1 under the following conditions:
VDD = 5V
GND = V5 = 0V,
V1, V2, V3A (V3B) and V4: Open
E, SSR, CSR, and BEB: “L” (fixed)
Other input pins: “L” or “H” (fixed)
Other output pins: No load
Note 3: Note 4:
OSC
1
OSC
OSC
OSC
1
R
= 120kW±2%
R
2
f
OSC
OSC
R
2
osc2
= fin =
The wire between OSC1 and Rf and the wire between
and Rf should be as short as possible.
OSC
2
Keep OSC
open.
R
Note 5:
V
DD
2
f
IN
waveform
The wire between OSC2 and OSCR should be as short
as possible. Keep OSC
t
HW
V
DD
2
t
LW
open.
1
V
DD
2
Applied to the pulses entering from the OSC1 pin
f
= tHW/ (tHW + tLW) ¥ 100 (%)
duty
10/54
Page 11
¡ Semiconductor ML9044
Note 6:
0.3V
0.7V
DD
DD
t
rf
t
0.7V
ff
DD
0.3V
DD
Applied to the pulses entering from the OSC1 pin
Note 7: For 1/4 bias, V2 and V3B pins are short–circuited. V3A pin is open.
For 1/5 bias, V3A and V3B pins are short–circuited. V2 pin is open.
11/54
Page 12
¡ Semiconductor ML9044
Switching Characteristics (The following ratings are subject to change after ES evaluation.)
• Parallel Interface Mode
The timing for the input from the CPU (see 1) and the timing for the output to the CPU (see 2)
are as shown below:
1) WRITE MODE (Timing for input from the CPU)
(VDD = 2.5 to 5.5V, Ta = –40 to +85°C)
Parameter Symbol UnitMin Typ Max
R/W, RS
, RS1 Setup time 40 — —t
0
E Pulse Width 450 — —t
R/W, RS
, RS1 Hold time 10 — —t
0
E Rise Time — — 25t
E Fall Time — — 25t
E Pulse Width 430 — —t
E Cycle Time 1000 — —t
to DB7 Input Data Hold time 195 — —t
DB
0
to DB7 Input Data Setup time 10 — —t
DB
0
B
W
A
r
f
L
C
I
H
ns
ns
ns
ns
ns
ns
ns
ns
ns
DB
RS1, RS
R/W
to DB
0
V
0
E
7
V
IL
IH
V
IL
V
IL
t
t
B
t
L
V
IL
r
V
IH
t
c
t
W
t
I
V
V
Input
IH
Data
IL
V
IH
V
IL
V
IL
t
f
V
IH
t
A
V
IL
t
H
V
IH
V
IL
12/54
Page 13
¡ Semiconductor ML9044
2) READ MODE (Timing for output to the CPU)
(VDD = 2.5 to 5.5V, Ta = –40 to +85°C)
Parameter Symbol UnitMin Typ Max
R/W, RS
, RS0 Setup Time 40 — —t
1
E Pulse Width 450 — —t
R/W, RS
, RS0 Hold Time 10 — —t
1
E Rise Time — — 25t
E Fall Time — — 25t
E Pulse Width 430 — —t
E Cycle Time 1000 — —t
to DB7 Output Data Delay Time — — 350t
DB
0
to DB7 Output Data Hold Time 20 — —t
DB
0
B
W
A
r
f
L
C
D
O
ns
ns
ns
ns
ns
ns
ns
ns
ns
DB
0
RS
to
1, 0
R/W
E
DB
V
IH
V
IL
V
IH
t
t
B
t
L
V
IL
7
V
IL
r
V
IH
t
D
t
c
t
W
V
V
OH
OL
Output
Data
V
IH
V
IL
V
IH
t
f
V
IH
t
A
V
IL
t
O
V
OH
V
OL
13/54
Page 14
¡ Semiconductor ML9044
• Serial Interface Mode
(VDD = 2.5 to 5.5V, Ta = –40 to +85°C)
Parameter Symbol UnitMin Typ Max
SHT Cycle Time 500 — —t
CS Setup Time 100 — —t
CS Hold Time 100 — —t
SHT Setup Time 60 — —t
SHT Hold Time 200 — —t
SHT "H" Pulse Width 200 — —t
SHT "L" Pulse Width 200 — —t
SHT Rise Time — — 50t
SHT Fall Time — — 50t
SI Setup Time 100 — —t
SI Hold Time 100 — —t
Data Output Delay Time — — 160t
Data Output Hold Time 0 — —t
SCY
CSU
CH
SSU
SH
SWH
SWL
SR
SF
DISU
DIH
DOD
CDH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS
SHT
SI
SO
t
CSU
t
SCY
V
IL
t
SSU
V
IH
t
DOD
t
SWL
V
IH
V
IL
V
V
IL
t
DISUtDIH
OL
t
SR
t
SWH
V
IH
V
IH
V
IL
t
SF
V
V
IH
t
DOD
IL
V
OH
t
SH
V
IH
t
CDH
t
CH
V
OH
14/54
Page 15
¡ Semiconductor ML9044
FUNCTIONAL DESCRIPTION
Instruction Register (IR), Data Register (DR), and Expansion Instruction Register (ER)
These registers are selected by setting the level of the Register Selection input pins RS0 and RS1.
The DR is selected when both RS0 and RS1 are “H”. The IR is selected when RS0 is “L” and RS
is “H”. The ER is selected when both RS0 and RS1 are “L”. (When RS0 is “H” and RS1 is “L”, the
ML9044 is not selected.)
The IR stores an instruction code and the address code of the display data RAM (DDRAM) or the
character generator RAM (CGRAM).
The microcontroller (CPU) can write to the IR but cannot read from the IR.
The ER stores a contrast adjusting code and the address code of the arbitrator RAM (ABRAM).
The CPU can write to or read from the ER.
The DR stores data to be written in the DDRAM, ABRAM and CGRAM and also stores data read
from the DDRAM, AMRAM and CGRAM.
The data written in the DR by the CPU is automatically written in the DDRAM, ABRAM or
CGRAM.
When an address code is written in the IR or ER, the data of the specified address is automatically
transferred from the DDRAM, ABRAM or CGRAM to the DR. The data of the DDRAM, ABRAM
and CGRAM can be checked by allowing the CPU to read the data stored in the DR.
After the CPU writes data in the DR, the data of the next address in the DDRAM, ABRAM or
CGRAM is selected to be ready for the next writing by the CPU. Similarly, after the CPU reads
the data in the DR, the data of the next address in the DDRAM, ABRAM or CGRAM is set in the
DR to be ready for the next reading by the CPU.
Writing in or reading from these 3 registers is controlled by changing the status of the R/
W(Read/Write) pin.
1
Table 1 R/W pin status and register operation
R/W RS
LLH
HLH
LHH
HHH
LLL
HLL
RS
0
1
Writing in the IR
Reading the Busy flag (BF) and the address counter (ADC)
Writing in the DR
Reading from the DR
Writing in the ER
Reading the contrast code
Operation
Busy Flag (BF)
The status “1” of the Busy Flag (BF) indicates that the ML9044 is carrying out internal operation.
When the BF is “1”, any new instruction is ignored.
When R/W = “H”, RS0 = “L” and RS1 = “H”, the data in the BF is output to the DB7.
New instructions should be input when the BF is “0”.
When the BF is “1”, the output code of the address counter (ADC) is undefined.
15/54
Page 16
¡ Semiconductor ML9044
Address Counter (ADC)
The address counter provides a read/write address for the DDRAM, ABRAM or CGRAM and
also provides a cursor display address.
When an instruction code specifying DDRAM, ABRAM or CGRAM address setting is input to
the pre–defined register, the register selects the specified DDRAM, ABRAM or CGRAM and
transfers the address code to the ADC. The address data in the ADC is automatically incremented
(or decremented) by 1 after the display data is written in or read from the DDRAM, ABRAM or
CGRAM.
The data in the ADC is output to DB0 to DB6 when R/W = “H”, RS0 = “L”, RS1 = “H” and BF =
“0”.
Timing Generator
The timing generator generates timing signals for the internal operation of the ML9044 activated
by the instruction sent from the CPU or for the operation of the internal circuits of the ML9041
such as DDRAM, ABRAM, CGRAM and CGROM. Timing signals are generated so that the
internal operation carried out for LCD displaying will not be interfered by the internal operation
initiated by accessing from the CPU. For example, when the CPU writes data in the DDRAM,
the display of the LCD not corresponding to the written data is not affected.
16/54
Page 17
¡ Semiconductor ML9044
Display Data RAM (DDRAM)
This RAM stores the display data represented in 8–bit character coding (see Table 2).
The DDRAM addresses correspond to the display positions (digits) of the LCD as shown below.
The DDRAM addresses (to be set in the ADC) are represented in hexadecimal.
DB6DB5DB4DB3DB2DB1DB
ADC
(Example) Representation of DDRAM address = 12
MSB LSB
Hexadecimal Hexadecimal
0ADC 0 1 0 0 1 0
1
2
0
1) Relationship between DDRAM addresses and display positions (1–line display mode)
Digit
1
2 3 4 5 23 24
00 01 02 03 04 16 17
Left
end
Right
end
Display position
DD RAM address (hexadecimal)
In the 1–line display mode, the ML9044 can display up to 24 characters from digit 1 to digit 24.
While the DDRAM has addresses “00” to “4F” for up to 80 character codes, the area not used for
display can be used as a RAM area for general data. When the display is shifted by instruction,
the relationship between the LCD display and the DDRAM address changes as shown below:
(Display shifted to the right)
(Display shifted to the left)
Digit
234 2324
1
4F 00 01 02 15 16
Digit
1
234
01 02 03 04 17 18
52324
05
17/54
Page 18
¡ Semiconductor ML9044
2) Relationship between DDRAM addresses and display positions (2–line display mode)
In the 2–line mode, the ML9044 can display up to 48 characters (24 characters per line) from digit
1 to digit 24.
Digit
Line 1
Line 2
2345
1
00 01 02 03 04
40 41 42 43 44 56 57
23 24
16 17
Display position
DD RAM
address (hexadecimal)
Note:
The DDRAM address at digit 24 in the first line is not consecutive to the DDRAM address at digit
1 in the second line.
When the display is shifted by instruction, the relationship between the LCD display and the
DDRAM address changes as shown below:
(Display shifted to the right)
(Display shifted to the left)
Line 1
Line 2
Line 1
Line 2
Digit
1234
27 00 01 02
67 40 41 42 55 56
Digit
1234
01 02 03 04
41 42 43 44
5
03
43
5
05
45 57 58
23 24
15 16
23 24
17 18
18/54
Page 19
¡ Semiconductor ML9044
Character Generator ROM (CGROM)
The CGROM generates small character patterns (5 ¥ 7 dots, 160 patterns) or large character
patterns (5 ¥ 10 dots, 32 patterns) from the 8–bit character code signals in the DDRAM. See Table
2 for the relationship between the 8–bit character codes and the character patterns.
When the 8–bit character code corresponding to a character pattern in the CGROM is written
in the DDRAM, the character pattern is displayed in the display position specified by the
DDRAM address.
19/54
Page 20
¡ Semiconductor ML9044
Character Generator RAM (CGRAM)
The CGRAM is used to generate user–specific character patterns that are not in the CGROM.
CGRAM (64 bytes = 512 bits) can store up to 8 small character patterns (5 ¥ 8 dots) or up to 4 large
character patterns (5 ¥ 11 dots).
When displaying a character pattern stored in the CGRAM, write an 8–bit character code (00 to
07 or 08 to 0F; hex.) assigned in Table 2 to the DDRAM. This enables outputting the character
pattern to the LCD display position corresponding to the DDRAM address.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC.
Therefore, the cursor or blink display should be inhibited while the ADC is holding a CGRAM
or ABRAM address.
The following describes how character patterns are written in and read from the CGRAM.
1) Small character patterns (5 ¥ 8 dots) (See Table 3–1.)
(1) A method of writing character patterns to the CGRAM from the CPU
The three CGRAM address bits 0 to 2 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB0 to DB7.
The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3.1).
Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status. Since
the ADC is automatically incremented or decremented by 1 after the data is written to the
CGRAM, it is not necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 2 are all “1”, which means
7 in hexadecimal) is the cursor line. The ON/OFF pattern of this line is ORed with the cursor
pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be
all zeros to display the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 is output to the LCD as display data, the
data given by the CGRAM data bits 5 to 7 is not. Therefore, the CGRAM data bits 5 to 7 can be
used as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher–order 4 bits of a character code are all zeros. Since bit
3 of a character code is not used, the character pattern “0” in Table 3–1 can be selected using the
character code “00” or “08” in hexadecimal.
When the 8–bit character code corresponding to a character pattern in the CGRAM is written to
the DDRAM, the character pattern is displayed in the display position specified by the DDRAM
address. (The DDRAM data bits 0 to 2 correspond to the CGRAM address bits 3 to 5,
respectively.)
20/54
Page 21
¡ Semiconductor ML9044
2) Large character patterns (5 ¥ 11 dots) (See Table 3–2.)
(1) A method of writing character patterns to the CGRAM from the CPU
The four CGRAM address bits 0 to 3 select one of the lines constituting a character pattern.
First, set the mode to increment or decrement from the CPU, and then input the CGRAM address.
Write each line of the character pattern code in the CGRAM through DB0 to DB7.
The data lines DB0 to DB7 correspond to the CGRAM data bits 0 to 7, respectively (see Table 3–
2). Input data “1” represents the ON status of an LCD dot and “0” represents the OFF status.
Since the ADC is automatically incremented or decremented by 1 after the data is written to the
CGRAM, it is not necessary to set the CGRAM address again.
The bottom line of a character pattern (the CGRAM address bits 0 to 3 are all “1”, which means
A in hexadecimal) is a cursor line. The ON/OFF pattern of this line is ORed with the cursor
pattern for displaying on the LCD. Therefore, the pattern data for the cursor position should be
all zeros to display the cursor.
Whereas the data given by the CGRAM data bits 0 to 4 with the CGRAM addresses 0 to A in
hexadecimal (set by the CGRAM address bits 0 to 3) is output as display data to the LCD, the data
given by the CGRAM data bits 5 to 7 or the CGRAM addresses B to F in hexadecimal is not. These
bits can be written and read as a RAM area.
(2) A method of displaying CGRAM character patterns on the LCD
The CGRAM is selected when the higher–order 4 bits of a character code are all zeros. Since bits
0 and 3 of a character code are not used, the character pattern “b” in Table 3–2 can be selected with
a character code “00”, “01”, “08” or “09” in hexadecimal.
When the 8–bit character code corresponding to a character pattern in the CGRAM is written to
the DDRAM, the character pattern is displayed in the display position specified by the DDRAM
address. (The DDRAM data bits 1 and 2 correspond to the CGRAM address bits 4 and 5,
respectively.)
21/54
Page 22
¡ Semiconductor ML9044
(
)
Arbitrator RAM (ABRAM)
The arbitrator RAM(ABRAM) stores arbitrator display data.
The ABRAM address is set at the ADC with the relationship illustrated below. Its valid address
area is 00 to 23 (00H to 17H).
Although an address exceeding 23 (17H) can be set or the address already set may exceed it due
to automatic increment or decrement processing, any address out of the valid address area is
ignored.
The cursor or blink is also displayed even when a CGRAM or ABRAM address is set in the ADC.
Therefore, the cursor or blink display should be inhibited while the ADC is hoding a CGRAM
or ABRAM address.
ADC
DB6DB5DB4DB3DB2DB1DB
MSB LSB
Hexadecimal Hexadecimal
0
The arbitrator RAM can store a maximum of 120 dots of the arbitrator Display–ON data in units
of 5 dots.
The arbitrator display is not shifted by any instructions and has the following relationship with
the LCD display positions:.
Configuration of input display data
Input data
DB
DB
7
*
*
Don't Care
DB5DB4DB3DB2DB1DB
6
* * E4 E3 E2 E1 E0
Display - ON data
0
Relationship between display-ON
data and segment pins
5XSn+1 5XSn+5
E4 E4
Sn = ABRAM address
0 to 23
22/54
Page 23
¡ Semiconductor ML9044
23/54
Table 2 Relationship between character codes and character patterns of the ML9044
Lower
4 bits
Upper
4 bits
0000
LSB
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MSB
0000 0010 0011 0100 0101 0110 0111 1010 1011 1100 1101 1110 1111
0001
CG
RAM (1)
(3)
(4)
(5)
(6)
(7)
(8)
(1)
(2)
(3)
(4)
(5)
(9)
(7)
(8)
(2)
#
$
%
&
(
)
*
+
–
.
/
!
2
3
4
5
6
7
8
9
:
;
<
=
>
?
1
0
B
C
D
E
F
G
H
I
J
K
L
M
N
O
A
@
R
S
T
U
V
W
X
Y
Z
[
¥
]
^
_
Q
P
b
c
d
e
f
n
h
i
j
k
l
m
n
o
a
/
r
s
t
u
v
w
x
y
z
{
Ù
}
Æ
¨
q
p
°
b
e
m
s
r
g
–1
j
x
¢
£
n
ö
ä
a
Q
•
W
ü
S
p
X
÷
q
R
√
Page 24
¡ Semiconductor ML9044
Table 3–1 Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 ¥ 7 dot character mode. (Examples)
CG RAM CG RAM
address (Character pattern) (Character code)
543210
MSB
000000
001000
111000
76543210 76543210
LSB
MSB LSB MSB LSB
¥¥¥
001
010
011
100
101
110
111
¥¥¥
001
010
011
100
101
110
111
¥¥¥
001
010
011
100
101
110
111
data
01110
10001
10001
10001
10001
10001
01110
00000
10001
10010
10100
11000
10100
10010
10001
00000
01110
00100
00100
00100
00100
00100
01110
00000
DD RAM
0000¥ 000
0000¥ 001
0000¥ 111
¥: Don't Care
data
24/54
Page 25
¡ Semiconductor ML9044
Table 3–2 Relationship between CGRAM address bits, CGRAM data bits (character pattern)
and DDRAM data bits (character code) in 5 ¥ 10 dot character mode (Examples)
CG RAM CG RAM
address (Character pattern) (Character code)
543210 76543210 76543210
000000
LSBMSB MSB LSB MSB LSB
¥¥¥
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
¥¥¥000000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
data
01000
01111
10010
01111
01
0
11111
00010
00000
00000
00000
00000
¥¥¥¥¥
00000
00000
01111
10001
10001
10001
01111
00001
00001
01110
00000
¥¥¥¥¥
DD RAM
01
0000¥ 00¥
0000¥ 00¥
data
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
¥: Don't Care
¥¥¥000000
00000
00000
11011
01010
10001
10001
01110
00000
00000
00000
00000
¥¥¥¥¥
0000¥ 11¥
25/54
Page 26
¡ Semiconductor ML9044
p
Cursor/Blink Control Circuit
This circuit generates the cursor and blink of the LCD.
The operation of this circuit is controlled by the program of the CPU.
The cursor/blink display is carried out in the position corresponding to the DDRAM address set
in the ADC (Address Counter).
For example, when the ADC stores a value of “07” (hexadecimal), the cursor or blink is displayed
as follows:
ADC
In 1-line display mode
In 2-line display mode
First line
Second line
DB6
0
000111
Digit
1234 5 89
01 02 03 04 07 08
00
Digit
1234 5 89
00 01 02 03 04 07 08
40 41 42 43 44 47 48 56 5745 46
DB0
70
05 06
05 06
23 2467
16 17
Cursor/blink position
23 2467
16 17
Cursor/blink
osition
Note: The cursor or blink is also displayed even when a CGRAM or ABRAM address is set
in the ADC. Therefore, the cursor or blink display should be inhibited while the ADC
is holding a CGRAM or ABRAM address.
26/54
Page 27
¡ Semiconductor ML9044
LCD Display Circuit (COM1 to COM17, SEG1 to SEG120, SSR and CSR)
The ML9044 has 17 common signal outputs and 120 segment signal outputs to display 24
characters (in the 1–line display mode) or 48 characters (in the 2–line display mode).
The character pattern is converted into serial data and transferred in series through the shift
register.
The transfer direction of serial data is determined by the SSR pin. The shift direction of common
signals is determined by the CSR pin. The following tables show the transfer and shift directions:
SSR Transfer direction
L SEG
H SEG
CSR duty AS bit Shift direction arbitrator's common pin
L 1/9 L COM1 Æ COM9 COM9
L 1/9 H COM2 Æ COM9, COM1 COM1
L 1/12 L COM1 Æ COM12 COM12
L 1/12 H COM2 Æ COM12, COM1 COM1
L 1/17 L COM1 Æ COM17 COM17
L 1/17 H COM2 Æ COM17, COM1 COM1
H 1/9 L COM9 Æ COM1 COM1
H 1/9 H COM8 Æ COM1, COM9 COM9
H 1/12 L COM12 Æ COM1 COM1
H 1/12 H
H 1/17 L COM17 Æ COM1 COM1
H 1/17 H
Æ SEG
1
Æ SEG
120
COM11
COM16
120
1
Æ
COM1, COM12
Æ
COM1, COM17
COM12
COM17
* Refer to the Expansion Instruction Codes section about the AS bit.
Signals to be input to the SSR and CSR pins should be determined at power–on and be kept
unchanged.
27/54
Page 28
¡ Semiconductor ML9044
Built–in Reset Circuit
The ML9044 is automatically initialized when the power is turned on.
During initialization, the Busy Flag (BF) is “1” and the ML9041 does not accept any instruction
from the CPU (other than the Read BF instruction).
The Busy Flag is “1” for about 15 ms after the VDD becomes 2.5 V or higher.
During this initialization, the ML9044 performs the following instructions:
1) Display clearing
2) CPU interface data length = 8 bits (DL = “1”)
3) 1–line LCD display (N = “0”)
4) Font size = 5 ¥ 7 dots (F = “0”)
5) ADC counting = Increment (I/D = “1”)
6) Display shifting = None (S = “0”)
7) Display = Off (D = “0”)
8) Cursor = Off (C = “0”)
9) Blinking = Off (B = “0”)
10) Arbitrator = Displayed in the lower line (AS = “0”)
11) Setting 1FH (hexadecimal) to the Contrast Data
To use the built–in reset circuit, the power supply conditions shown below should be satisfied.
Otherwise, the built–in reset circuit may not work properly. In such a case, initialize the ML9044
with the instructions from the CPU. The use of a battery always requires such initialization from
the CPU. (See “Initial Setting of Instructions”)
2.5V
0.2V 0.2V 0.2V
t
ON
0.1ms£ t
£ 100ms
ON
1ms£ t
OFF
t
OFF
Figure 1 Power–on and Power–off Waveform
28/54
Page 29
¡ Semiconductor ML9044
I/F with CPU
Parallel interface mode
The ML9044 can transfer either 8 bits once or 4 bits twice on the data bus for interfacing with any
8–bit or 4–bit microcontroller (CPU).
1) 8–bit interface data length
The ML9044 uses all of the 8 data bus lines DB0 to DB7 at a time to transfer data to and from the
CPU.
2) 4–bit interface data length
The ML9044 uses only the higher–order 4 data bus lines DB4 to DB7 twice to transfer 8–bit data
to and from the CPU.
The ML9044 first transfers the higher–order 4 bits of 8–bit data (DB4 to DB7 in the case of 8–bit
interface data length) and then the lower–order 4 bits of the data (DB0 to DB3 in the case of 8–bit
interface data length).
The lower–order 4 bits of data should always be transferred even when only the transfer of the
higher–order 4 bits of data is required. (Example: Reading the Busy Flag)
Two transfers of 4 bits of data complete the transfer of a set of 8–bit data. Therefore, when only
one access is made, the following data transfer cannot be completed properly.
29/54
Page 30
¡ Semiconductor ML9044
RS
1
RS
0
R/W
E
Busy
(Internal operation)
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
IR
IR
IR
IR
IR
IR
7
6
5
4
3
2
Busy
No
Busy
ADC
ADC
ADC
ADC
ADC
DR
7
DR
DR
DR
DR
DR
6
5
4
3
2
6
5
4
3
2
RS
1
RS
0
R/W
E
Busy
(Internal operation)
DB
7
DB
DB
1
0
IR
1
IR
0
Writing In IR
(Instruction
ADC
1
ADC
0
Reading BF (Busy Flag)
and ADC (Address Counter)
DR
1
DR
0
Writing In DR
(Data Register)
Register)
Figure 2 8-Bit Data Transfer
No
IR
7
IR
3
Busy
Busy
ADC
3
DR7DR
3
DB
DB
DB
6
5
4
IR
6
IR
5
IR
4
Writing In IR
(Instruction
IR
2
IR
1
IR
0
Reading BF (Busy Flag)
and ADC (Address Counter)
ADC
ADC
ADC
ADC
ADC
ADC
2
1
0
6
5
4
DR6DR
DR5DR
DR4DR
Writing In DR
(Data Register)
2
1
0
Register)
Figure 3 4-Bit Data Transfer
30/54
Page 31
¡ Semiconductor ML9044
Serial Interface Mode
In the Serial I/F Mode, the ML9044 interfaces with the CPU via the CS, SHT, SI and SO pins.
Writing and reading operations are executed in units of 16 bits after the CS signal falls down. If
the CS signal rises up before the completion of 16–bit unit access, this access is ignored.
When the BF bit is “1”, the ML9044 cannot accept any other instructions. Before inputting a new
instruction, check that the BF bit is “0”. Any access when the BF bit is “1” is ignored.
Data format is LSB–first.
Examples of Access in the Serial I/F Mode
1) WRITE MODE
CS
12345
SHT
SI
11111
SO
2) READ MODE
CS
12345
SHT
SI
11111
6 7 8 9 10 11 12 13 14 15 16
R/W
4
3
2
1
0
1
0
6
5
D
D
D
D
D
D
D
RS
RS
6 7 8 9 10 11 12 13 14 15 16
RS
R/W
RS
1
0
D
7
SO
D
1
0
3
2
5
4
7
6
D
D
D
D
D
D
D
31/54
Page 32
¡ Semiconductor ML9044
Instruction Codes
Table of Instruction Codes
Instruction Function
Code
DB0DB1DB2DB3DB4DB5DB6DB7R/WRS0RS1
Clears all the displayed digits of the LCD and
Display Clear
10000000001
sets the DDRAM address 0 in the address
counter. The arbitrator data is cleared.
Sets the DDRAM address 0 in the address
Cursor Home
1000000001
original. The content of the DDRAM
counter and shifts the display back to the
*
remains unchanged.
Determines the direction of movement of
Entry Mode Setting
I/D
100000001
the cursor and whether or not to shift the
S
display. This instruction is executed when
data is written or read.
Sets LCD display ON/OFF (D), cursor
ON/OFF or cursor-position character
Displya ON/OFF Control
BCD10000001
blinking ON/OFF.
Moves the cursor or shifts the display
Cursor/Display Shift
1000001
**R/LS/C
without changing the content of the DDRAM.
Sets the interface data length (DL), the
number of display lines (N) or the type of
Function Setting
DL
100001
FN
**
character font (F).
Sets on CGRAM address. After that,
CGRAM Address Setting
10001
ACG
CGRAM data is transferred to and from
the CPU.
Sets a DDRAM address. After that DDRAM
DDRAM Address Setting
1001
ADD
data is transferred to and from the CPU.
Execution
Time
f = 270kHz
1.52 ms
1.52 ms
37 ms
37 ms
37 ms
37 ms
37 ms
37 ms
Busy Flag/Address Read
RAM Data Write
RAM Data Read
Arbitrator Display Line Set
Contrast Control Data Write
Contrast Control Data Read
ABRAM address setting
—
BF101
011
111
000
100
I/D = "1"
(Increment)
S = "1"
(Shifts the display.)
S/C = "1"
(Shifts display.)
R/L = "1"
(Right shift)
D/L = "1"
(8-bit data)
N = "1"
(2 lines)
F = "1"
(5 ¥ 10 dots)
BF = "1"
(Busy)
B = "1"
(Enables blinking.)
C = "1"
(Displyas the corsor.)
D = "1"
(Displays a character pattern.)
AS = "1"
(Arbitrator Displays arbitrator
on the upper line)
ADC
WRITE DATA
READ DATA
WRITE (Contrast Data) DATA
100
READ (Contrast Data) DATA
000
AAB
(Decrement)
I/D = "0"
(Moves the cursor.)
S/C = "0"
(Left shift)
R/L = "0"
(4-bit data)
DL = "0"
(1 line)
N = "0"
(5 ¥ 7 dots)
F = "0"
(Ready to accept
BF = "0"
an instruction)
AS = "0"
(Arbitrator Displays
arbitrator on the lower line)
Reads the Busy Flag (indicating that the
ML9044 is operating) and the content of
0 ms
the address counter.
Writes data in DDRAM, ABRAM or CGRAM.
Reads data from DDRAM, ABRAM or CGRAM.
Sets the arbitrator display line.
Writes data to control the contrast of the LCD.
Reads data to control the contrast of the LCD.
37 ms
37 ms
37 ms00000001AS00
37 ms
37 ms
Sets an ABRAM address. After that
ABRAM data is transferred to and from
37 ms000110
the CPU.
DD RAM
: Display data RAM
CG RAM
: Character generator RAM
ABRAM
: Arbitrator data RAM
ACG
: CGRAM address
ADD
: DDRAM address (Corresponds to
the cursor address)
AAB
: ABRAM address
ADC
: Address counter (Used by DDRAM,
ABRAM and CGRAM)
The
execution
time is
dependent
upon
frequencies
¥: Don't Care
32/54
Page 33
¡ Semiconductor ML9044
Instruction Codes
An instruction code is a signal sent from the CPU to access the ML9044. The ML9044 starts
operation as instructed by the code received. The busy status of the ML9044 is rather longer than
the cycle time of the CPU, since the internal processing of the ML9044 starts at a timing which
does not affect the display on the LCD. In the busy status (Busy Flag is “1”), the ML9044 executes
the Busy Flag Read instruction only. Therefore, the CPU should ensure that the Busy Flag is “0”
before sending an instruction code to the ML9044.
1) Display Clear
Instruction Code :
RS
RS
1
1
0
0
R/W0DB
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
0
DB
2
DB
1
0
0
1
When this instruction is executed, the LCD display including arbitrator display is cleared and the
I/D entry mode is set to “Increment”. The value of “S” (Display shifting) remains unchanged.
The position of the cursor or blink being displayed moves to the left end of the LCD (or the left
end of the line 1 in the 2–line display mode).
Note: All DDRAM and ABRAM data turn to “20” and “00” in hexadecimal, respectively. The
value of the address counter (ADC) turns to the one corresponding to the address “00”
(hexadecimal) of the DDRAM.
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency
of 270 kHz.
2) Cursor Home
Instruction code:
RS
RS
1
1
0
0
R/W0DB
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
1
0
¥
¥: Don't Care
When this instruction is executed, the cursor or blink position moves to the left end of the LCD
(or the left end of line 1 in the 2–line display mode). If the display has been shifted, the display
returns to the original display position before shifting.
Note: The value of the address counter (ADC) goes to the one corresponding to the address
“00” (hexadecimal) of the DDRAM).
The execution time of this instruction is 1.52 ms (maximum) at an oscillation frequency
of 270 kHz.
33/54
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¡ Semiconductor ML9044
3) Entry Mode Setting
Instruction code:
RS
RS
1
1
0
0
R/W0DB
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
1
I/D
DB
1
0
S
(1) When the I/D is set, the cursor or blink shifts to the right by 1 character position (ID= “1”;
increment) or to the left by 1 character position (I/D= “0”; decrement) after an 8–bit character
code is written to or read from the DDRAM. At the same time, the address counter (ADC) is also
incremented by 1 (when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).
After a character pattern code is written to or read from the CGRAM, the address counter (ADC)
is incremented by 1 (when I/D = “1”; increment) or decremented by 1 (when I/D = “0”;
decrement).
Also after data is written to or read from the ABRAM, the address counter (ADC) is incremented
by 1 (when I/D = “1”; increment) or decremented by 1 (when I/D = “0”; decrement).
(2) When S = “1”, the cursor or blink stops and the entire display shifts to the left (I/D = “1”) or
to the right (I/D = “0”) by 1 character position after a character code is written to the DDRAM.
In the case of S = “1”,when a character code is read from the DDRAM, when a character pattern
data is written to or read from the CGRAM or when data is written to or read from the ABRAM,
normal read/write is carried out without shifting of the entire display. (The entire display does
not shift, but the cursor or blink shifts to the right (I/D = “1”) or to the left (I/D = “0”) by 1
character position.)
When S = “0”, the display does not shift, but normal write/read is performed.
Note: The execution time of this instruction is 37 ms (maximum) at an oscillation frequency
of 270 kHz.
4) Display Mode Setting
Instruction code:
RS
RS
1
1
0
0
R/W0DB
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
1
DB
2
D
DB
1
C
0
B
(1) The “D” bit (DB2) of this instruction determines whether or not to display character patterns
on the LCD.
When the “D” bit is “1”, character patterns are displayed on the LCD.
When the “D” bit is “0”, character patterns are not displayed on the LCD and the cursor/blink
setting is also canceled.
Note: Unlike the Display Clear instruction, this instruction does not change the character
code in the DDRAM and ABRAM.
(2 ) When the “C” bit (DB1) is “0”, the cursor turns off. When both the “C” and “D” bits are “1”,
the cursor turns on.
(3) When the “B” bit (DB0) is “0”, blinking is canceled. When both the “B” and “D” bits are “1”,
blinking is performed.
In the Blinking mode, all dots including those of the cursor, the character pattern and the cursor
are alternately displayed.
Note: The execution time of this instruction is 37 ms (maximum) at an oscillation frequency
of 270kHz.
34/54
Page 35
¡ Semiconductor ML9044
5) Cursor/Display Shift
RS
RS
1
0
R/W0DB
DB
7
DB
6
DB
5
DB
4
DB
3
DB
2
DB
1
0
Instruction code:
1
¥: FDon't Care
0
0
0
0
1
S/C
R/L
¥
¥
S/C = “0”, R/L = “0” This instruction shifts left the cursor and blink positions by 1 (decrements
the content of the ADC by 1).
S/C = “0”, R/L = “1” This instruction shifts right the cursor and blink positions by 1 (increments
the content of the ADC by 1).
S/C = “1”, R/L = “0”
This instruction shifts left the entire display by 1 character position. The
cursor and blink positions move to the left together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
S/C = “1”, R/L = “1”
This instruction shifts right the entire display by 1 character position. The
cursor and blink positions move to the right together with the entire display.
The Arbitrator display is not shifted.
(The content of the ADC remains unchanged.)
In the 2–line mode, the cursor or blink moves from the first line to the second line when the cursor
at digit 40 (27; hex) of the first line is shifted right.
When the entire display is shifted, the character pattern, cursor or blink will not move between
the lines (from line 1 to line 2 or vice versa).
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
6) Function Setting
Instruction code:
RS
1
1
¥: Don't Care
RS
0
0
R/W0DB
DB
7
0
DB
6
0
DB
5
1
DL
DB
4
DB
3
N
DB
2
F
DB
1
¥
0
¥
(1) When the “DL” bit (DB4) of this instruction is “1”, the data transfer to and from the CPU is
performed once by the use of 8 bits DB7 to DB0.
When the “DL” bit (DB4) of this instruction is “0”, the data transfer to and from the CPU is
performed twice by the use of 4 bits DB7 to DB4.
(2) The 2–line display mode is selected when the “N” bit (DB3) of this instruction is “1”. The 1–
line display mode is selected when the “N” bit is “0”.
(3) The character font represented by 5 ¥ 7 dots is selected when the “F” bit (DB2) of this
instruction is “1”. The character font represented by 5 ¥ 10 dots is selected when the “F” bit is “1”
and the “N” bit is “0”.
After the ML9044 is powered on, this initial setting should be carried out before execution of any
instruction except the Busy Flag Read. After this initial setting, no instructions other than the DL
Set instruction can be executed. In the Serial I/F Mode, DL setting is ignored.
NF
display lines
Font size Duty
00 1 5¥7 1/9 4 9
01 1 5¥10 1/12 4 12
10 2 5¥7 1/17 5 17
11 2 5¥7 1/17 5 17
Number of
Number of
biases
Number of
common signals
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
35/54
Page 36
¡ Semiconductor ML9044
7) CGRAM Address Setting
Instruction code:
RS
RS
1
1
0
0
R/W0DB
DB
7
0
DB
6
1
C
DB
5
C
5
DB
4
4
C
DB
3
3
C
DB
2
2
C
DB
1
1
0
C
0
This instruction sets the character data corresponding to the CGRAM address represented by the
bits C5 to C0 (binary).
The CGRAM addresses are valid until DDRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the CGRAM
address bits C5 to C0 set in the instruction code at that time.
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
8) DDRAM Address Setting
Instruction code:
RS
RS
1
1
0
0
R/W0DB
DB
7
1
D
DB
6
D
6
DB
5
D
5
DB
4
4
D
DB
3
D
3
DB
2
D
2
DB
1
1
0
D
0
This instruction sets the character data corresponding to the DDRAM address represented by the
bits D6 to D0 (binary).
The DDRAM addresses are valid until CGRAM or ABRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the DDRAM
address bits D6 to D0 set in the instruction code at that time.
In the 1–line mode (the “N” bit is “1”), the DDRAM address represented by bits D6 to D0 (binary)
should be in the range “00” to “4F” in hexadecimal.
In the 2–line mode (the “N” bit is “2”), the DDRAM address represented by bits D6 to D0 (binary)
should be in the range “00” to “27” or “40” to “67” in hexadecimal.
If an address other than above is input, the ML9044 cannot properly write a character code in or
read it from the DDRAM.
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
9) DDRAM/ABRAM/CGRAM Data Write
Instruction code:
RS
RS
1
1
0
1
R/W0DB
DB
7
E
7
E
DB
6
6
E
DB
5
5
E
DB
4
4
E
DB
3
3
E
DB
2
2
E
DB
1
1
0
E
0
This instruction writes data represented by bits E7 to E0 (binary) to DDRAM, ABRAM or
CGRAM.
After data is written, the cursor, blink or display shifts according to the Cursor/Display Shift
instruction (see 5)).
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
36/54
Page 37
¡ Semiconductor ML9044
10) Busy Flag/Address Counter Read (Execution time: 1 ms)
Instruction code:
RS
RS
1
1
0
0
R/W1DB
BF
DB
7
O
DB
6
O
6
DB
5
O
5
DB
4
4
O
DB
3
O
3
DB
2
O
2
DB
1
1
0
O
0
The “BF” bit (DB7) of this instruction tells whether the ML9044 is busy in internal operation (BF
= “1”) or not (BF = “0”).
When the “BF” bit is “1”, the ML9044 cannot accept any other instructions. Before inputting a
new instruction, check that the “BF” bit is “0”.
When the “BF” bit is “0”, the ML9044 outputs the correct value of the address counter. The value
of the address counter is equal to the DDRAM, ABRAM or CGRAM address. Which of the
DDRAM, ABRAM and CGRAM addresses is set in the counter is determined by the preceding
address setting.
When the “BF” bit is “1”, the value of the address counter is not always correct because it may
have been incremented or decremented by 1 during internal operation.
11) DDRAM/ABRAM/CGRAM Data Read
Instruction code:
RS
RS
1
1
0
1
R/W1DB
DB
7
P
7
P
DB
6
6
P
DB
5
P
5
DB
4
4
P
DB
3
3
P
DB
2
P
2
DB
1
1
0
P
0
A character code (P7 to P0) is read from the DDRAM, Display–ON data (P7 to P0) from the
ABRAM or a character pattern (P7 to P0) from the CGRAM.
The DDRAM, ABRAM or CGRAM is selected at the preceding address setting.
After data is read, the address counter (ADC) is incremented or decremented as set by the
Transfer Mode Setting instruction (see 3).
Note: Conditions for reading correct data
(1) The DDRAM, ABRAM or CGRAM Setting instruction is input before this data read
instruction is input.
(2) When reading a character code from the DDRAM, the Cursor/Display Shift instruction (see
5) is input before this Data Read instruction is input.
(3) When two or more consecutive RAM Data Read instructions are executed, the following read
data is correct.
Correct data is not output under conditions other than the cases (1), (2) and (3) above.
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
37/54
Page 38
¡ Semiconductor ML9044
Expansion Instruction Codes
The busy status of the ML9044 is rather longer than the cycle time of the CPU, since the internal
processing of the ML9044 starts at a timing which does not affect the display on the LCD. In the
busy status (Busy Flag is “1”), the ML9041 executes the Busy Flag Read instruction only.
Therefore, the CPU should ensure that the Busy Flag is “0” before sending an expansion
instruction code to the ML9044.
1) Arbitrator Display Line Set
RS
Exparsion Instruction codes:
RS
1
0
0
0
R/W0DB
DB
7
0
DB
6
0
DB
5
0
DB
4
0
DB
3
0
DB
2
0
DB
1
1
0
AS
This expansion instruction code sets the Arbitrator display line. The relationship between the
status of this bit and the common outputs is as follows:
CSR duty AS bit Shift direction Arbitrator's comon pin
L 1/9 L COM1 Æ COM9 COM9
L 1/9 H COM2 Æ COM9, COM1 COM1
L 1/12 L COM1 Æ COM12 COM12
L 1/12 H COM2 Æ COM12, COM1 COM1
L 1/17 L COM1 Æ COM17 COM17
L 1/17 H COM2 Æ COM17, COM1 COM1
H 1/9 L COM9 Æ COM1 COM1
H 1/9 H COM8 Æ COM1, COM9 COM9
H 1/12 L COM12 Æ COM1 COM1
H 1/12 H
H 1/17 L COM17 Æ COM1 COM1
H 1/17 H
COM11 Æ COM1, COM12
COM16 Æ COM1, COM17
COM12
COM17
2) Contrast Adjusting Data Write
Exparsion Instraction codes:
RS
RS
1
0
0
0
R/W0DB
DB
7
0
DB
6
0
DB
5
1
DB
4
F
4
DB
3
F
3
DB
2
F
2
DB
1
F
1
0
F
0
This instruction writes contrast adjusting data (F4 to F0) to the contrast register.
After contrast adjusting data is written in the register, the potential (VLCD) output to the V5 pin
varies according to the data written.
The VLCD becomes maximum when the content of the contrast register is “1F” (hexadecimal)
and becomes minimum when it is “00” (hexadecimal).
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
38/54
Page 39
¡ Semiconductor ML9044
3) Contrast Adjusting Data Read
Exparsion Instruction code:
RS
RS
1
0
0
0
R/W1DB
DB
7
0
DB
6
0
DB
5
0
DB
4
G
4
DB
3
G
3
DB
2
G
2
DB
1
G
1
0
G
0
This instruction reads contrast adjusting data (G4 to G0) from the contrast register.
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
4) ABRAM Address Setting
Exparsion Instruction code:
RS
RS
1
0
0
0
R/W1DB
DB
7
0
DB
6
1
DB
5
1
DB
4
H
4
DB
3
H
H
3
DB
2
2
DB
1
H
1
0
H
0
This instruction sets the character data corresponding to the ABRAM address represented by the
bits H4 to H0 (binary).
The ABRAM addresses are valid until CGRAM or DDRAM addresses are set.
The CPU writes or reads character patterns starting from the one represented by the ABRAM
address bits H4 to H0 set in the instruction code at that time.
The ABRAM address represented by bits H4 to H0 (binary) should be in the range “00” to “13”
in hexadecimal.
If an address other than above is input, the ML9044 cannot properly write a character code in or
read it from the DDRAM.
Note: The execution time of this instruction is 37 ms at an oscillation frequency (OSC) of 270
kHz.
39/54
Page 40
¡ Semiconductor ML9044
LCD Drive Waveforms
The COM and SEG waveforms (AC signal waveforms for display) vary according to the duty (1/
9, 1/12 and 1/17 duties). See 1) to 3) below.
The relationship between the duty ratio and the frame frequency is as follows:
Duty ratio Frame Frequency
1/9 75.0Hz
1/12 56.3Hz
1/17 79.4Hz
Note: At an oscillation frequency (OSC) of 270 kHz
(1) Driving the LCD of one 24–character line (1/9 duty, CSR = L, AS = 0) under the conditions
of the 1–line display mode and the character font of 5 ¥ 7 dots
COM
1
COM
8
COM
9
SEG
ML9044
1
SEG
• COM10 to COM17 output Display–OFF common signals.
Character
Cursor
Arbitrator
120
40/54
Page 41
¡ Semiconductor ML9044
COM
1
COM
11
COM
12
SEG
1
SEG
120
MSM9044
Character
Cursor
Arbitrator
(2) Driving the LCD of one 24–character line (1/12 duty, CSR = L, AS = 0) under the conditions
of the 1–line display mode and the character font of 5 ¥ 10 dots
• COM13 to COM17 output Display–OFF common signals.
(3) Driving the LCD of two 24–character line (1/17 duty, CSR = L, AS = 0) under the conditions
of the 2–line display mode and the character font of 5 ¥ 7 dots
COM
1
Character
COM
COM
COM
COM
8
9
16
17
SEG
1
SEG
120
Cursor
Character
Cursor
Arbitrator
MSM9044
41/54
Page 42
¡ Semiconductor ML9044
EXAMPLES OF VLCD GENERATION CIRCUITS
• With 1/4bias, a built–in contrast adjusting circuit and a voltage multiplier
V
DD
V
1
V
2
V
3A
V
3B
V
4
ML9044
V
V
5IN
V
V
CC
V
BEB
5
C
IN
Reference potential for
voltage multiplien
• With 1/5 bias, a built–in contrast adjusting circuit and the V5 level input from an external
circuit
V
DD
V
1
V
2
V
3A
V
3B
V
4
ML9044
V
V
5IN
V
V
V
BEB
5
V5 level
C
CC
IN
42/54
Page 43
¡ Semiconductor ML9044
1) COM and SEG Waveforms on 1/9 Duty
8
9 1 2 3 4 7 8 9 1 2 3 4 7 8 9 1 2
V2, V
V
DD
V
1
3B
V
4
V
5
1 frame
COM1 (CSR = L, AS = L)
(CSR = L, AS = H)
COM
2
COM
(CSR = H, AS = L)
9
COM
(CSR = H, AS = H)
8
(first character line)
COM
(CSR = L, AS = L)
2
(CSR = L, AS = H)
COM
3
COM
(CSR = H, AS = L)
8
COM
(CSR = H, AS = H)
7
(second character line)
COM
(CSR = L, AS = L)
8
(CSR = L, AS = H)
COM
9
COM
(CSR = H, AS = L)
2
COM
(CSR = H, AS = H)
1
(cursor line)
COM
(CSR = L, AS = L)
9
(CSR = L, AS = H)
COM
1
COM
(CSR = H, AS = L)
1
COM
(CSR = H, AS = H)
9
(arbitrator line)
COM10 to
COM
SEG
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
17
3B
V
4
V
5
Display
turning-off
waveform
V2, V
V
DD
V
1
3B
V
4
V
5
Display
turning-on
waveform
43/54
Page 44
¡ Semiconductor ML9044
2) COM and SEG Waveforms on 1/12 Duty
11
12 1 2 3 4 5 6 9 10 11 12 1 2 3 4 5 6
V2, V
V
DD
V
1
3B
V
4
V
5
1 frame
COM1 (CSR = L, AS = L)
(CSR = L, AS = H)
COM
2
COM
(CSR = H, AS = L)
12
COM
(CSR = H, AS = H)
11
(first character line)
COM
(CSR = L, AS = L)
2
(CSR = L, AS = H)
COM
3
COM
(CSR = H, AS = L)
11
COM
(CSR = H, AS = H)
10
(second character line)
COM
(CSR = L, AS = L)
11
(CSR = L, AS = H)
COM
12
COM
(CSR = H, AS = L)
2
COM
(CSR = H, AS = H)
1
(cursor line)
COM
(CSR = L, AS = L)
12
(CSR = L, AS = H)
COM
1
COM
(CSR = H, AS = L)
1
COM
(CSR = H, AS = H)
12
(arbitrator line)
COM13 to
COM
SEG
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
3B
V
4
V
5
V
DD
V
1
V2, V
17
3B
V
4
V
5
Display
turning-off
waveform
V2, V
V
DD
V
1
3B
V
4
V
5
Display
turning-on
waveform
44/54
Page 45
¡ Semiconductor ML9044
3) COM and SEG Waveforms on 1/17 Duty
16
COM1 (CSR = L, AS = L)
(CSR = L, AS = H)
COM
2
COM
(CSR = H, AS = L)
17
COM
(CSR = H, AS = H)
16
(first character line)
17 1 2 3 4 5 6 7 8 9 10 11 12 13 16 17 1 2
V
DD
V
1
V
V
2
(
V
)
3A
3B
V
4
V
5
1 frame
3 4
COM
(CSR = L, AS = L)
2
(CSR = L, AS = H)
COM
3
COM
(CSR = H, AS = L)
16
COM
(CSR = H, AS = H)
15
(second character line)
COM
(CSR = L, AS = L)
16
COM
(CSR = L, AS = H)
17
COM
(CSR = H, AS = L)
2
(CSR = H, AS = H)
COM
1
(corsor line)
COM
(CSR = L, AS = L)
17
COM
(CSR = L, AS = H)
1
COM
(CSR = H, AS = L)
1
COM
(CSR = H, AS = H)
17
(arbitrator line)
SEG
V
DD
V
1
V
V
V
V
2
(
V
)
3A
3B
V
4
V
5
V
DD
V
1
V
2
(
V
)
3A
3B
V
4
V
5
V
DD
V
1
V
2
(
V
)
3A
3B
V
4
V
5
Display
turning-off
V
DD
V
1
V
V
2
(
V
)
3A
3B
V
4
V
5
waveform
Display
turning-on
waveform
45/54
Page 46
¡ Semiconductor ML9044
Initial Setting of Instructions
(a) Data transfer from and to the CPU using 8 bits of DB0 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.5V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 ms or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 ms or more).
9) Set “8 bits”, “Number of LCD lines” and “Font size” with the Function Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
10) Check the Busy Flag for No Busy.
11) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode
Setting instruction and Arbitrator Display Line Setting Instruction.
12) Check the Busy Flag for No Busy.
13) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS
¥ : Don't Care
RS
1
1
0
0
R/W0DB
DB
7
0
0
DB
6
1
DB
5
1
DB
4
¥
DB
3
¥
DB
2
DB
1
¥
0
¥
(b) Data transfer from and to the CPU using 8 bits of DB4 to DB7
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.5V or higher.
3) Set “8 bits” with the Function Setting instruction.
4) Wait for 4.1 ms or more.
5) Set “8 bits” with the Function Setting instruction.
6) Wait for 100 ms or more.
7) Set “8 bits” with the Function Setting instruction.
8) Check the Busy Flag for No Busy (or wait for 100 ms or longer).
9) Set “4 bits” with the Function Setting instruction.
10) Wait for 100 ms or longer.
11) Set “4 bits”, “Number of LCD lines” and “Font size” with the Initial Setting instruction.
(After this, the number of LCD lines and the font size cannot be changed.)
12) Check the Busy Flag for No Busy.
13) Execute the Display Mode Setting Instruction, Display Clear Instruction, Entry Mode
Setting instruction and Arbitrator Display Line Setting Instruction
14) Check the Busy Flag for No Busy.
15) Initialization is completed.
An example of instruction code for 3), 5) and 7)
RS
1
RS
1
0
R/W
0
DB
0
DB
7
0
0
DB
6
1
DB
5
4
1
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Page 47
¡ Semiconductor ML9044
An example of instruction code for 9)
RS
RS
1
1
0
R/W
0
DB
0
0
DB
7
0
DB
6
1
DB
5
4
0
*: In 13), check the Busy Flag for No Busy before executing each instruction.
(c) Data transfer from and to the CPU using the serial I/F
1) Turn on the power.
2) Wait for 15 ms or more after VDD has reached 2.5V or higher.
3) Set “Number of LCD lines” and “Font size” with the Function Setting Instruction.
4) Execute the Display Mode Setting Instruction, the Display Clear Instruction, the Entry Mode
Instruction and the Arbitrator Display Line Setting Instruction.
5) Check the busy flag for No Busy.
6) Initialization is completed.
*: In 3) and 4), check the Busy Flag for No Busy before executing each instruction.
47/54
Page 48
¡ Semiconductor ML9044
Relationship Between Character Codes and Character patterns
00H 08H 10H 18H 20H 28H 30H 38H
01H 09H 11H 19H 21H 29H 31H 39H
02H 0AH 12H 1AH 22H 2AH 32H 3AH
03H 0BH 13H 1BH 23H 2BH 33H 3BH
04H 0CH 14H 1CH 24H 2CH 34H 3CH
05H 0DH 15H 1DH 25H 2DH 35H 3DH
06H 0EH 16H 1EH 26H 2EH 36H 3EH
07H 0FH 17H 1FH 27H 2FH 37H 3FH
48/54
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¡ Semiconductor ML9044
40H 48H 50H 58H 60H 68H 70H 78H
41H 49H 51H 59H 61H 69H 71H 79H
42H 4AH 52H 5AH 62H 6AH 72H 7AH
43H 4BH 53H 5BH 63H 6BH 73H 7BH
44H 4CH 54H 5CH 64H 6CH 74H 7CH
45H 4DH 55H 5DH 65H 6DH 75H 7DH
46H 4EH 56H 5EH 66H 6EH 76H 7EH
47H 4FH 57H 5FH 67H 6FH 77H 7FH
49/54
Page 50
¡ Semiconductor ML9044
80H 88H 90H 98H A0H A8H B0H B8H
81H 89H 91H 99H A1H A9H B1H B9H
82H 8AH 92H 9AH A2H AAH B2H BAH
83H 8BH 93H 9BH A3H ABH B3H BBH
84H 8CH 94H 9CH A4H ACH B4H BCH
85H 8DH 95H 9DH A5H ADH B5H BDH
86H 8EH 96H 9EH A6H AEH B6H BEH
87H 8FH 97H 9FH A7H AFH B7H BFH
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Page 51
¡ Semiconductor ML9044
C0H C8H D0H D8H E0H E8H F0H F8H
C1H C9H D1H D9H E1H E9H F1H F9H
C2H CAH D2H DAH E2H EAH F2H FAH
C3H CBH D3H DBH E3H EBH F3H FBH
C4H CCH D4H DCH E4H ECH F4H FCH
C5H CDH D5H DDH E5H EDH F5H FDH
C6H CEH D6H DEH E6H EEH F6H FEH
C7H CFH D7H DFH E7H EFH F7H FFH
51/54
Page 52
¡ Semiconductor ML9044
PAD CONFIGURATION
Pad Layout
Chip Size : 10.62 ¥ 2.55mm
Chip Thickness : 625±20mm
Bump Size (1) : 72 ¥ 72mm
Bump Size (2) : 54 ¥ 96mm
182
183
189
1
Y
63
62
X
56
55
Pad Coordinates
Pad Symbol X (mm) Y (mm)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
1
V
2
V
3A
V
3B
V
4
V
5
V
5IN
V
CC
V
C
V
IN
BEB
V
DD
CSR
SSR
P/S
V
SS
DB
DB
DB
DB
–5103
–4914
–4725
–4536
–4347
–4158
–3969
–3780
–3591
–3402
–3213
–3024
–2835
–2646
–2457
–2268
7
6
5
4
–2079
–1890
–1701
–1512
Pad Symbol X (mm) Y (mm)
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
–1099.8 –1099.8
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DB
3
DB
2
DB
1
DB
0
E
R/W
RS
0
RS
1
SO
SI
SHT
CS
OSC
OSC
OSC
T
3
T
2
T
1
COM
COM
–1323
–1134
–945
–756
–567
–378
–189
0
189
378
567
756
2
R
1
945
1134
1323
1512
1701
1890
1
2
2079
2268
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Page 53
¡ Semiconductor ML9044
Pad Symbol X (mm) Y (mm)
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
COM
3
COM
4
COM
5
COM
6
COM
7
COM
8
COM
9
COM
10
COM
11
COM
12
COM
13
COM
14
COM
15
COM
16
COM
17
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY
DUMMY 5184 180661 101
DUMMY 5184 172262 102
SEG
120
SEG
119
SEG
118
SEG
117
SEG
116
SEG
115
SEG
114
SEG
113
SEG
112
SEG
111
SEG
110
SEG
109
SEG
108
SEG
107
SEG
106
SEG
105
SEG
104
SEG
103
2457
2646
2835
3024
3213
3402
3591
3780
3969
4158
4347
4536
4725
4914
5103
5184
5184
5184
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–1099.8
–720
–480
–240
5184
5184
240
480
720
4998 163863 103
4914 155464 104
4830 147065 105
4746 138666 106
4662 130267 107
4578 121868 108
4494 113469 109
4410 105070 110
4326 96671 111
4242 88272 112
4158 79873 113
4074 71474 114
3990 63075 115
3906 54676 116
3822 46277 117
3738 37878 118
3654 29479 119
3570
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
Pad Symbol X (mm) Y (mm)
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
0
99
100
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
3486
3402
3318
3234
3150
3066
2982
2898
2814
2730
2646
2562
2478
2394
2310
2226
2142
2058
1974
1890
21080 120
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
53/54
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¡ Semiconductor ML9044
Pad Symbol X (mm) Y (mm)
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150 –2310 DUMMY185 240–5184
151 –2394 DUMMY186 0–5184
152 –2478 DUMMY187 –240–5184
153 –2562 DUMMY188 –480–5184
154 –2646 DUMMY189 –720–5184
155 –2730
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
126
42
–42
–126
–210
–294
–378
–462
–546
–630
–714
–798
–882
–966
–1050
–1134
–1218
–1302
–1386
–1470
–1554
–1638
–1722
–1806
–1890
–1974
–2058
–2142
–2226
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
Pad Symbol X (mm) Y (mm)
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
SEG
DUMMY183
DUMMY184
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
–2814
–2898
–2982
–3066
–3150
–3234
–3318
–3402
–3486
–3570
–3654
–3738
–3822
–3906
–3990
–4074
–4158
–4242
–4326
–4410
–4494
–4578
–4662
–4746
–4830
–4914
–4998
–5184
–5184
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
1087.8
720
480
54/54
Page 55
E2Y0002-29-62
NOTICE
1. The information contained herein can change without notice owing to product and/or
technical improvements. Before using the product, please make sure that the information
being referred to is up-to-date.
2. The outline of action and examples for application circuits described herein have been
chosen as an explanation for the standard action and performance of the product. When
planning to use the product, please ensure that the external conditions are reflected in the
actual circuit, assembly, and program designs.
3. When designing your product, please use our product below the specified maximum
ratings and within the specified operating ranges including, but not limited to, operating
voltage, power dissipation, and operating temperature.
4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or
unexpected operation resulting from misuse, neglect, improper installation, repair, alteration
or accident, improper handling, or unusual physical or electrical stress including, but not
limited to, exposure to parameters beyond the specified maximum ratings or operation
outside the specified operating range.
5. Neither indemnity against nor license of a third party’s industrial and intellectual property
right, etc. is granted by us in connection with the use of the product and/or the information
and drawings contained herein. No responsibility is assumed by us for any infringement
of a third party’s right which may result from the use thereof.
6. The products listed in this document are intended for use in general electronics equipment
for commercial applications (e.g., office automation, communication equipment,
measurement equipment, consumer electronics, etc.). These products are not authorized
for use in any system or application that requires special or enhanced quality and reliability
characteristics nor in any system or application where the failure of such system or
application may result in the loss or damage of property, or death or injury to humans.
Such applications include, but are not limited to, traffic and automotive equipment, safety
devices, aerospace equipment, nuclear power control, medical equipment, and life-support
systems.
7. Certain products in this document may need government approval before they can be
exported to particular countries. The purchaser assumes the responsibility of determining
the legality of export of these products and will take appropriate and necessary steps at their
own expense for these.
8. No part of the contents contained herein may be reprinted or reproduced without our prior
permission.
9. MS-DOS is a registered trademark of Microsoft Corporation.
Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan
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