Datasheet ML7000-02MA, ML7000-02MB, ML7000-01MA, ML7001-03MB, ML7001-01MA Datasheet (OKI)

E2U0062-18-84

Preliminary

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

This version: Aug. 1998

¡ Semiconductor

ML7000-01/02/03
ML7001-01/02/03

Single Rail CODEC

GENERAL DESCRIPTION

The ML7000/ML7001 are single-channel CMOS CODEC LSI devices for voice signals ranging
from 300 to 3400 Hz with filters for A/D and D/A conversion.
Designed especially for a single-power supply and low-power applications, the devices are
optimized for ISDN terminals, digital wireless systems, and digital PBXs.
The devices use the same transmission clocks as those used in the MSM7507.
With the differential analog signal outputs which can drive 60 W load, the devices can directly
drive a handset receiver.

FEATURES

• Single power supply: +5 V (ML7000-xx)
+3 V (ML7001-xx)

• Low power consumption

Operating mode: 25 mW Typ. VDD = 5.0 V (ML7000-xx)

20 mW Typ. VDD = 3.0 V (ML7001-xx)

Power-down mode: 0.05 mW Typ. VDD = 5.0 V (ML7000-xx)

0.03 mW Typ. VDD = 3.0 V (ML7001-xx)

• Conforms to ITU-T Companding law

ML7000-01/ML7001-01: m/A-law pin selectable
ML7000-02/ML7001-02: m-law
ML7000-03/ML7001-03: A-law

• Transmission characteristics conform to ITU-T G.714

• Short frame sync timing operation

• Built-in PLL eliminates a master clock

• Serial data rate: 64/96/128/192/200/256/384/512/

768/1024/1536/1544/2048 kHz

• Adjustable transmit gain

• Adjustable receive gain

• Built-in reference voltage supply

• Package options:

24-pin plastic SOP (SOP24-P-430-1.27-K) (Product name: ML7000-01MA/ML7001-01MA)

(Product name: ML7000-02MA/ML7001-02MA)
(Product name: ML7000-03MA/ML7001-03MA)

20-pin plastic SSOP (SSOP20-P-250-0.95-K) (Product name: ML7000-01MB/ML7001-01MB)

(Product name: ML7000-02MB/ML7001-02MB)
(Product name: ML7000-03MB/ML7001-03MB)

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¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

BLOCK DIAGRAM

AIN–
AIN+

GSX

SGC

SG

VFRO

PWI

AOUT–

AOUT+

–
+

SG

GEN

RC

LPF

–
+

–
+

–
+

8th

BPF

GEN

5th

LPF

VR

CONV.

AUTO
ZERO

D/A

CONV.

PWD

A/D

TCONT

PLL

RTIM

RCONT

PWD

Logic

PCMOUT

XSYNC

BCLK

RSYNC

(ALAW)

PCMIN

PDN
V

DD

AG
DG

2/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

PIN CONFIGURATION (TOP VIEW)

1

SG

AOUT+

AOUT–

RSYNC

PCMIN

2

3

4

NC

5

PWI

6

VFRO

7

NC

8

V

DD

9

DG

10

PDN

11

12 13

24-Pin Plastic SOP

24

23

22

21

20

19

18

17

16

15

14

SGC

AIN+

AIN–

GSX

NC

NC

(ALAW)*

NC

AG

BCLK

XSYNC

PCMOUT

1

SG

AOUT+

AOUT–

RSYNC

PCMIN

2

3

4

PWI

5

VFRO

V

6

DD

7

DG

8

PDN

9

10 11

20-Pin Plastic SSOP

20

19

18

17

16

15

14

13

12

SGC

AIN+

AIN–

GSX

NC

(ALAW)*

AG

BCLK

XSYNC

PCMOUT

* The ALAW pin is only supported by the ML7000-01MA/ML7000-01MB/ML7001-01MA/

ML7001-01MB.

NC : No connect pin

3/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

PIN FUNCTIONAL DESCRIPTION

AIN+, AIN–, GSX

Transmit analog input and transmit level adjustment.
AIN+ is a non-inverting input to the op-amp; AIN– is an inverting input to the op-amp; GSX is
connected to the output of the op-amp.
The level adjustment should be performed using any of the methods shown below. During
power-saving and power-down modes, the GSX output is at AG voltage.

Analog input

Analog input

AG

Analog ground.

VFRO

C1

C2

R5

R1

R3

R4

R2

GSX
AIN–
AIN+
SG

AIN+
AIN–
GSX

SG

R1 : variable

–
+

+
–

R2 > 20 kW
C1 > 1/(2 ¥ 3.14 ¥ 30 ¥ R1)

R3 > 20 kW
R4 > 20 kW
R5 > 50 kW
C2 > 1/ (2 ¥ 3.14 ¥ 30 ¥ R5)

Receive filter output.
The output signal has an amplitude of 2.4 VPP for ML7000-xx and 2.0 VPP for ML7001-xx above
and below the signal ground voltage (SG) when the digital signal of +3 dBm0 is input to PCMIN
and can drive a load of 20 kW or more.
For driving a load of less than 20 kW, connect a resistor of 20 kW or more between the pins VFRO
and PWI.
During power-saving or power-down mode, the VFRO output is at an SG level.
When adjusting the receive signal on the basis of frequency characteristics, refer to the Frequency
Characteristics Adjustment Circuit.

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¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

PWI, AOUT+, AOUT–

PWI is connected to the inverting input of the receive driver.
The receive driver output is connected to the AOUT– pin. Therefore, the receive level can be
adjusted with the pins VFRO, PWI, and AOUT–. During power-saving or power down-mode,
the outputs of AOUT+ and AOUT– are in a high impedance state. The output of AOUT+ is
inverted with respect to the output of AOUT–. Since these outputs provide differential drive of
an impedance of 1.2 kW, they can directly be connected to a handset using a piezoelectric
earphone or a line transformer. Refer to the application example.

VI

PWI

R6

R7

VO

ZL

Receive filter

–
+

SG

20 kW

–
+

SG

V

DD

VFRO

AOUT–

20 kW

AOUT+

R6 > 20 kW
ZL > 1.2 kW

Gain = VO/VI = 2 5 R7/R6 £ 2

Power supply for +5 V (ML7000-xx) or +3 V (ML7001-xx)

PCMIN

PCM data input.
A serial PCM data input to this pin is converted to an analog signal in synchronization with the
RSYNC signal and BCLK signal.
The data rate of PCM is equal to the frequency of the BCLK signal.
PCM signal is shifted in at the falling edge of the BCLK signal and latched into the internal
register when shifted by eight bits.
The start of the PCM data (MSD) is identified at the rising edge of RSYNC.

BCLK

Shift clock signal input for the PCMIN and PCMOUT signals.
The frequency, equal to the data rate, is 64, 96, 128, 192, 256, 384, 512, 768, 1024, 1536, 1544, or 2048
kHz. Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power
saving state.

5/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

RSYNC

Receive synchronizing signal input.
Eight required bits are selected from serial PCM signals on the PCMIN pin by the receive
synchronizing signal.
Signals in the receive section are synchronized by this synchronizing signal. This signal must be

synchronized in phase with the BCLK. The frequency should be 8 kHz ±50 ppm to guarantee the

AC characteristics which are mainly the frequency characteristics of the receive section.
However, if the frequency characteristic of an applied system is not specified exactly, this device
can operate in the range of 6 to 9 kHz, but the electrical characteristics in this specification are not
guaranteed.

XSYNC

Transmit synchronizing signal input.
The PCM output signal from the PCMOUT pin is output in synchronization with this signal. This
synchronizing signal triggers the PLL and synchronizes all timing signals of the transmit section.
This synchronizing signal must be synchronized in phase with BCLK.

The frequency should be 8 kHz ±50 ppm to guarantee the AC characteristics which are mainly

the frequency characteristics of the transmit section. However, if the frequency characteristic of
an applied system is not specified exactly, this device operates in the range of 6 to 9 kHz, but the
electrical characteristics in this specification are not guaranteed.
Setting this signal to logic "1" or "0" drives both transmit and receive circuits to the power saving
state.

6/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

DG

Ground for the digital signal circuits.
This ground is separate from the analog signal ground AG. The DG pin must be connected to the
AG pin on the printed circuit board to make a common analog ground AG.

PDN

Power down control signal.
A logic "0" level drives both transmit and receive circuits to a power down state.

PCMOUT

PCM signal output.
Synchronizing with the rising edge of the BCLK signal, the PCM output signal is output from
MSD in a sequential order.
MSD may be output at the rising edge of the XSYNC signal, based on the timing between BCLK
and XSYNC.
This pin is in a high impedance state except during 8-bit PCM output. It is also in a high
impedance state during power saving or power down mode.
A pull-up resistor must be connected to this pin because its output is configured as an open drain.
This device is compatible with the ITU-T recommendation on coding law and output coding
format.
The ML7000-03 (A-law) and ML7001-03 (A-law) output the character signal, inverting the even
bits.

Input/Output Level

+Full scale

+0

–0

–Full scale

PCMIN/PCMOUT

ML7000-02 (m-law)

ML7001-02 (m-law)

MSD

1000 0000

1111 1111

0111 1111

0000 0000

ML7000-03 (A-law)

ML7001-03 (A-law)

MSD

LSD LSD

1010 1010

1101 0101

0101 0101

0010 1010

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¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

SG

Signal ground voltage output.
The output voltage is 1/2 of the power supply voltage.

The output drive current capability is ±300 mA for ML7000-xx and ±200 mA for ML7001-xx.

This pin provides the SG level for CODEC peripherals.
This output voltage level is undefined during power-saving or power-down mode.

SGC

Used to generate the signal ground voltage level by connecting a bypass capacitor.
Connect a 0.1 mF capacitor with excellent high frequency characteristics between the AG pin and
the SGC pin.

ALAW

Control signal input of the companding law selection.
Only the ML7000-01MA/ML7000-01MB/ML7001-01MA/ML7001-01MB have this pin. The
CODEC will operate in the m-law when this pin is at a logic "0" level and the CODEC will operate
in the A-law when this pin is at a logic "1" level. The CODEC operates in the m-law if the pin is
left open, since the pin is internally pulled down.

8/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

ABSOLUTE MAXIMUM RATINGS

Parameter

Power Supply Voltage

Analog Input Voltage

Digital Input Voltage

Symbol

V

DD

V

AIN

V

DIN

Condition

—

—

—

Rating

–0.3 to +7

–0.3 to V

–0.3 to V

DD

DD

+ 0.3

+ 0.3

RECOMMENDED OPERATING CONDITIONS

Parameter

Power Supply Voltage

Analog Input Voltage

High Level Input Voltage

Low Level Input Voltage

Clock Frequency kHz

Sync Pulse Frequency

Clock Duty Ratio

Digital Input Rise Time

Digital Input Fall Time

Transmit Sync Pulse Setting Time

XSYNC Setup Time

XSYNC Hold Time —

Receive Sync Pulse Setting Time

RSYNC Setup Time

RSYNC Hold Time

PCMIN Setup Time

PCMIN Hold Time

Digital Output Load

Analog Input Allowable DC Offset

Symbol

V

DD

Connect AIN– and GSXV

AIN

V

IH

XSYNC, RSYNC, BCLK,

PCMIN, PDN, ALAW

V

IL

BCLKF

C

XSYNC, RSYNC (–40 to +75 °C)F

S

C

t

lr

PCMIN, PDN

lf

CX

XC

XS

XH

CR

RC

RS

RH

DS

DH

DL

DL

Transmit gain stage, Gain = 0 dB

V

off

Transmit gain stage, Gain = +20 dB

—

—

—

—

—

—

5.255.004.75

3.303.002.70

2.4——

1.2——

V

DD

V

DD

DD

—2.2

—0.45¥V

0.8—0

0.16¥V

—0

64, 96, 128, 192, 200, 256,

384, 512, 768, 1024, 1536,

1544, 2048

9.08.06.0

10.08.06.0

DD

Unit

V

V

V

UnitMax.Typ.Min.Condition

V

°C+85+25–30—TaOperating Temperature

V

PP

V

V

kHz

%605040BCLKD

ns50——XSYNC, RSYNC, BCLK,

ns50——t

ns——50BCLKÆXSYNC, See Fig. 1t

ns——50XSYNCÆBCLK, See Fig. 1t

ns——50t

ns——50t

ns——50BCLKÆRSYNC, See Fig. 1t

ns——50RSYNCÆBCLK, See Fig. 1t

ns——50t

ns——50t

ns——50t

ns——50t

kW——0.5Pull-up resistorR

pF100———C

mV+10—–10

mV+100—–100

ns1000——XSYNC, RSYNC, BCLK—Allowable Jitter Width

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

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¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

ELECTRICAL CHARACTERISTICS

DC and Digital Interface Characteristics

(ML7001-xx: V

(ML7000-xx: V

Parameter

Power Supply Current

High Level Input Voltage

Low Level Input Voltage

High Level Input Leakage Current

High Level Input Leakage Current I

Low Level Input Leakage Current

Digital Output Low Voltage

Digital Output Leakage Current

Input Capacitance

Symbol

Operating mode

I

DD1

No signal

Power-saving mode, PDN = 1,

I

DD2

XSYNC Æ OFF

Power-down mode, PDN = 0,

I

DD3

BCLK OFF

V

IH

V

IL

I

IH

IH2

I

IL

V

Pull-up resistor = 500 W

OL

I

O

C

IN

Condition

VDD = 5.0 V

VDD = 3.0 V

—

—

—

—

—

— —5—pF

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

= 2.7 V to 3.3 V, Ta = –30 to +85°C)

DD

= +5.0 V ±5%, Ta = –30 to +85°C)

DD

Min.

—

Typ.

5.0

Max.

12.0

— 6.5 10.0

—

1.5

4.0

— 2.0 8.0

—

2.2

0.45¥V

0.0

0.0

—

DD

0.01

—

—

—

—

—

0.05

V

DD

V

DD

0.8

0.16¥V

2.0

DD

— — 30.0 mAALAW

—

0.0

—

—

0.2

—

0.5

0.4

10

Unit

mA

mA

mA

V

V

mA

mA

V

mA

10/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

Transmit Analog Interface Characteristics

= 2.7 V to 3.3 V, Ta = –30 to +85°C)

DD

= +5.0 V ±5%, Ta = –30 to +85°C)

DD

10

20

—

–1.2

—

—

—

—

–0.7 — +0.7

–20

—

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

Symbol

AIN+, AIN–

R

INX

GSX with respect to SG

R

LGX

C

LGX

V

OGX

V

OSGX

(ML7001-xx: V

(ML7000-xx: V

Condition Min. Typ. Max. Unit

Gain = 1

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

Receive Analog Interface Characteristics

Parameter

Input Resistance

Output Load Resistance

Output Load Capacitance

Output Amplitude

Offset Voltage

(ML7001-xx: V

(ML7000-xx: V

Symbol

R

PWI 10

INPW

R

VFRO with respect to SG

LVF

AOUT+, AOUT– (each) with

R

LAO

respect to SG

VFRO

C

LVF

AOUT+, AOUT–

C

LAO

VFRO, RL = 20 kW with

V

OVF

respect to SG

AOUT+, AOUT–, R

V

OAO

with respect to SG

V

VFRO with respect to SG

OSVF

AOUT+, AOUT–, Gain = 1 with

V

OSAO

respect to SG

Condition Min. Typ. Max. Unit

L

= 0.6 kW

= 2.7 V to 3.3 V, Ta = –30 to +85°C)

DD

= +5.0 V ±5%, Ta = –30 to +85°C)

DD

—

20

0.6

—

—

–1.2

–1.0

–1.3

–1.0

–100

–100

—

—

—

—

—

—

—

—

—

—

—

—

30

+1.2

+20

—

—

—

30

50

+1.2

+1.0

+1.3

+1.0

+100

+100

MW

kW

pF

V0p

mV

MW

kW

kW

pF

pF

V0p

mV

mV

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

11/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

AC Characteristics

Parameter

Transmit Frequency Response

Receive Frequency Response

Symbol

Loss T1

Loss T2

Loss T3

Loss T4

Loss T5

Loss T6

Loss R1

Loss R2

Loss R3

Loss R4

Loss R5

(ML7001-xx: FS = 8 kHz, V

(ML7000-xx: F

Freq.

(Hz)

Level

(dBm0)

= 8 kHz, V

S

Condition

= 2.7 V to 3.3 V, Ta = –30 to +85°C)

DD

= +5.0 V ±5%, Ta = –30 to +85°C)

DD

Min. Typ. Max. Unit

60 20 26 —

300 –0.15 +0.07 +0.2

1020 Reference

2020 –0.15 –0.04 +0.2

3000 –0.15 +0.07 +0.2

3400 0 0.4 0.8

300 –0.15 –0.03 +0.2

1020 Reference

2020 –0.15 0.00 +0.2 dB0

3000 –0.15 +0.05 +0.2

3400 0 0.54 0.8

SD T1 35 43 —3

SD T2 35 41 —0

SD T3

Transmit Signal to Distortion Ratio 1020 dB

SD T4

SD T5

–30

*1

–40

–45

35.0 38.0 —

34.0 38.0 —

26.0 31.0 —

26.0 30.0 —

24.0 25.0 —

— 25.0 —

SD R1 36 43 —3

SD R2 36 41 —0

SD R3

Receive Signal to Distortion Ratio 1020 dB

SD R4

SD R5

GT T1 –0.3 +0.01 +0.3

GT T2 Reference

Transmit Gain Tracking

GT T3 1020 –0.3 –0.05 +0.3 dB–40

GT T4 –0.6 –0.05 +0.6

GT T5 –1.2 –0.08 +1.2

GT R1 –0.3 –0.06 +0.3

GT R2 Reference

Receive Gain Tracking

GT R3 1020 –0.3 +0.08 +0.3 dB

GT R4 –0.6 +0.12 +0.6

GT R5 –1.2 +0.15 +1.2

–30

*1

–40

–45

3

–10

–50

–55

3

–10

–40

–50

–55

36.0 40.0 —

40.035.0 —

25.0

26.0

25.0

—

32.0 —

32.0

—

27.0 —

27.0

—

dB0

*1 Psophometric filter is used.

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

12/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

AC Characteristics (Continued)

Parameter

Idle Channel Noise

Absolute Level (Initial Difference)

Absolute Level

(Deviation of Temperature and Power)

Absolute Delay

Transmit Group Delay

Receive Group Delay

Crosstalk Attenuation

Symbol

Nidle T

Nidle R

AV T

AV R

AV Tt –0.2 — 0.2

AV Rt –0.2 — 0.2

tGD T1

tGD T2

tGD T3

tGD T4

tGD T5

tGD R1

t

GD

t

GD

t

GD

t

GD

CR T — –85 –75

CR R –76

(ML7001-xx: FS = 8 kHz, V

(ML7000-xx: F

Freq.

(Hz)

Level

(dBm0)

—

—

V

= 5 V ±5%, Ta = –30 to 85°C

DD

= 2.7 to 3.3 V, Ta = –30 to 85°C

V

DD

Td 1020 — — 0.6 ms0

500

600

1000

2600

2800

500

600

R2

R3

1000

R4

2600

R5

2800

1020 dB0

—

—

0

= 8 kHz, V

S

Condition

AIN = SG

*1 *2

*1 *2

V

= 5.0 V,

DD

= 25°C

Ta

V

= 3.0 V,

DD

Ta = 25°C

*3

*3

*3

A to A

BCLK

= 64 kHz

*4

*4

TRANS Æ RECV

RECV Æ TRANS

= 2.7 V to 3.3 V, Ta = –30 to +85°C)

DD

= +5.0 V ±5%, Ta = –30 to +85°C)

DD

Min. Typ. Max. Unit

— –73.0 –66.0

— –65.0–69.5

— –71.0

–78.0

— –65.0–75.0

0.58 0.6007 0.622

0.338 0.35 0.362

0.60070.58 0.622

0.483 0.5180.5

— 0.19 0.75

— 0.11 0.35

— 0.02 0.1250

— 0.05 0.125

— 0.75

0.07

— 0.00 0.75

— 0.35

0.00

— 0.00 0.125 ms0

— 0.09 0.125

— 0.12 0.75

— –70

dBm0p

Vrms1020

dB

ms

*1 Psophometric filter is used.
*2 Input "0" code to PCMIN.
*3 AVR is defined at VFRO output.
*4 With respect to minimum value of the group delay distortion.

Values above the dotted line are for ML7000-xx; those below, for ML7001-xx.

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¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

AC Characteristics (Continued)

(ML7001-xx: FS = 8 kHz, V

(ML7000-xx: F

= 8 kHz, V

S

= 2.7 V to 3.3 V, Ta = –30 to +85°C)

DD

= +5.0 V ±5%, Ta = –30 to +85°C)

DD

Parameter

Symbol

Freq.

(Hz)

4.6 kHz to

Discrimination 0

Digital Output Delay Time

DIS

72 kHz

300 to

S

3400

fa = 470

IMD

fd = 320

PSR T

PSR R

t

XD1

t

XD2

0 to

50 kHz

CL = 100 pF + 1 LSTTL

Pull-up resistor = 500 W

Level

(dBm0)

*5 Measured under idle channel noise.

Condition

0 to

4000 Hz

4.6 kHz to

100 kHz

Measured

PP

inband *5

Min. Typ. Max. Unit

30 32 — dB

— –37.5 –35 dBm0Out-of-band Spurious 0

— –52 –35 dBm0Intermodulation Distortion –4 2fa – fb

—30—dBPower Supply Noise Rejection Ratio 50 mV

20 — 200

20 — 200

ns

14/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

TIMING DIAGRAM

PCM Data Input/Output Timing

Transmit Timing

BCLK 12345678910

tXSt

XH

XSYNC

PCMOUT

t

CX

t

t

XC

XD1

MSD

D2 D3 D4 D5 D6 D7

t

D8

XD2

Receive Timing

BCLK 12345678910

tRSt

RH

RSYNC

PCMIN

t

CR

t

RC

t

t

DS

DH

MSD

D2 D3

D4 D5 D6 D7 D8

Figure 1 Basic Timing

11 12

11 12

15/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

APPLICATION CIRCUIT

+ 5V

0 V

+5 V

600:600

600:600

0 to 20 W

300 W

300 W

10 mF

0.1 mF

600 W

+

51 kW

51 kW

0.1 mF

1 mF

ML7000-01

AIN–

GSX

AIN+

SG

AOUT+

AOUT–

PWI

VFRO

SGC
DG
AG

V

DD

PCMOUT

XSYNC

RSYNC

BCLK

PCMIN

ALAW

PDN

1 kW

PCM signal output

8 kHz SYNC signal input

PCM shift clock input
PCM signal input

Control of companding law
1: A-law
0: m-law

Power down control input
1: Normal operation
0: Power down

+3 V

0 V

+3 V

600:600

600:600

0 to 20 W

300 W

300 W

10 mF

0.1 mF

600 W

+

51 kW

51 kW

0.1 mF

1 mF

ML7001-01

AIN–

GSX

AIN+

SG

AOUT+

AOUT–

PWI

VFRO

SGC
DG
AG

V

DD

PCMOUT

XSYNC

RSYNC

BCLK

PCMIN

ALAW

PDN

1 kW

PCM signal output

8 kHz SYNC signal input

PCM shift clock input
PCM signal input

Control of companding law
1: A-law
0: m-law

Power down control input
1: Normal operation
0: Power down

16/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

NOTES ON USE

• To ensure proper electrical characteristics, use bypass capacitors with excellent high frequency

characteristics for the power supply and keep them as close as possible to the device pins.

• Connect the AG pin and the DG pin as closely as possible. Connect to the system ground with

low impedance.

• Mount the device directly on the board when mounted on PCBs. Do not use IC sockets. If the

use of IC socket is unavoidable, use the short lead type socket.

• When mounted on a frame, use electromagnetic shielding if any electromagnetic wave

sources such as power supply transformers surrounds the device.

• Keep the voltage on the VDD pin not lower than –0.3 V even instantaneously to avoid latch-

up that may otherwise occur when power is turned on.

• Use a low noise (particularly, low level type of high frequency spike noise or pulse noise)

power supply to avoid erroneous operation and the degradation of the characteristics of these
devices.

17/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

PACKAGE DIMENSIONS

(Unit : mm)

SOP24-P-430-1.27-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.58 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

18/19

¡ Semiconductor ML7000-01/02/03/ML7001-01/02/03

(Unit : mm)

SSOP20-P-250-0.95-K

Mirror finish

Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)

Epoxy resin
42 alloy
Solder plating
5 mm or more

0.18 TYP.

Notes for Mounting the Surface Mount Type Package

The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).

19/19