Datasheet ML6673CH, ML6673CQ Datasheet (Micro Linear Corporation)

December 1998

ML6673

Fast Ethernet/FDDI TP-PMD Transceiver

GENERAL DESCRIPTION

The ML6673 is a complete monolithic transceiver for 125
Mbaud MLT-3 encoded data transmission over Category 5
unshielded twisted pair and shielded twisted pair cables.
The ML6673 integrates the baseline restoration function
defined in the TP-PMD standard. The adaptive equalizer in
the ML6673 will accurately compensate for line losses
exceeding the IEEE 802.3u limit of 100m of UTP.

The ML6673 receive section consists of an equalizing filter
with a feedback loop for controlling effective line
compensation. The feedback loop contains a filter and
detection block for determining the proper control signal.
The ML6673 also contains data comparators with
precisely controlled slicing thresholds and an MLT-3 to
NRZI translator.

The ML6673 transmit section accepts ECL 100K
compatible NRZ inputs and converts them to differential
current mode MLT-3 signals. Transmit amplitude is
controlled by a single external resistor.

BLOCK DIAGRAM

FEATURES

■ Compliant with IEEE 802.3u Fast Ethernet (100BASE-TX)

standard

■ Compliant with ANSI X3T12 FDDI over copper

(TP-PMD) standard

■ Integrated baseline wander correction circuit

■ Transmitter converts NRZI ECL signals to MLT-3 current

driven outputs

■ Transmitter can be externally turned off

(high impedence) for true quiet line

■ Receiver includes adaptive equalizer and MLT-3 to

NRZI decoder

■ Operates over 100 meters of STP or category 5 UTP

Twisted Pair Cable set by the IEEE 802.3u standards

■ 32-pin PLCC and TQFP

TXIN+

TXIN–

SD+

SD–

RXOUT+

RXOUT–

LPBK TXOFF TVCCA TVCCD

NRZI

TO MLT-3

LINK

STATUS

MUX

MLT-3

TO NRZI

GNDTGNDDTGNDA

RTSET1 RTSET2

BASELINE
WANDER

CORRECTION

ADAPTIVE
CONTROL

ADAPTIVE

EQUALIZER

RRSET2RRSET1

RTSET

TPOUT+

TPOUT–

TPIN+

TPIN–

CMREFRVCCDRVCCARRSET

1

ML6673

–

PIN CONFIGURATION

ML6673

32-Pin PCC (Q32)

RVCCA

RXOUT

4 3 2 1 32 31 30

RXOUT+

RVCCD

TGNDD

LPBK

TXOFF

SD–

SD+

N/C

N/C

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20

TXIN–

TXIN+

PIN DESCRIPTION

N/C

N/C

RTSET1

TVCCD

CMREF

TPIN+

RTSET2

TPOUT+

TPIN–

29

28

27

26

25

24

23

22

21

TPOUT–

RRSET1

RRSET2

N/C

N/C

RGND

N/C

N/C

TVCCA

TGNDA

RRSET1

TPIN–

TPIN+

CMREF

N/C

N/C

RVCCA

RXOUT–

ML6673

32-Pin TQFP (H32-7)

RRSET2

N/C

N/C

RGND

N/C

N/C

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

9 10111213141516

RVCCD

RXOUT+

SD–

SD+

N/C

TGNDD

TVCCA

LPBK

TGNDA

24

23

22

21

20

19

18

17

TXOFF

TPOUT–

TPOUT+

RTSET2

RTSET1

TVCCD

TXIN–

TXIN+

N/C

NAME FUNCTION NAME FUNCTION

TXIN+, TXIN– These differential ECL100K compatible

inputs receive NRZI data from the PHY
for transmission.

TPOUT+, Outputs from the NRZI-MLT3 state
TPOUT– machine drive these differential current

outputs. The transmitter filter/transformer
module connects the media to these pins.

LPBK This TTL input enables transmitter-

receiver loopback internally when
asserted low. When LPBK is asserted,
signal detect is asserted.

TXOFF This TTL input forces the NRZI-MLT3

state machine to a high impedence state
when asserted low and shuts off transmit
bias current.

RTSET1, An external 1% resistor connected
RTSET2 between these pins controls the

transmitter output current amplitude.
I

= 64 x 1.25V/RTSET

OUT

TVCCA, Separate analog and digital transmitter
TVCCD power supply pins help to isolate

sensitive circuitry from noise generating
digital functions. Both supplies are
nominally +5 volts.

TGNDA, Analog and digital transmitter grounds
TGNDD provide separate return paths for clean

and noisy signals.

SD+, SD– These differential ECL100K compatible

outputs indicate the presence of a data
signal with an amplitude exceeding a
preset threshold.

TPIN+, TPIN– MLT-3 encoded data from the receiver

filter/transformer module enters the
receiver through these pins.

RXOUT+, Differential ECL100K compatible outputs
RXOUT– provide NRZI encoded data to the PHY.

RRSET1, Internal time constants controlling the
RRSET2 equalizer’s transfer function are set by an

external resistor connected across these
pins.

CMREF This pin provides a DC common mode

reference point for the receiver inputs.

RVCCA, Analog and digital supply pins are
RVCCD separated to isolate clean and noisy

circuit functions. Both supplies are
nominally +5 volts.

RGND Receiver ground.

2

ABSOLUTE MAXIMUM RATINGS

ML6673

Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.

VCC Supply Voltage Range ................... GND –0.3V to 6V

Input Voltage Range

Digital Inputs ........................GND –0.3V to V

CC

+0.3V

Output Current

TPOUT±, SD±, RXOUT± ................................... 50mA

All other outputs ................................................. 10mA

Junction Temperature ............................................. 150°C

Lead Temperature (Soldering, 10 sec) .....................260°C

Thermal Resistance (θ

)

JA

PLCC ............................................................... 60°C/W

TQFP ............................................................... 80°C/W

OPERATING CONDITIONS

V

Supply Voltage ............................................ 5V ± 5%

CC

T

, Ambient Temperature .............................. 0°C to 70°C

A

RTSET ............................................................... 2kΩ ±1%

RRSET .......................................................... 9.53kΩ ±1%

Receive Transformer Insertion Loss ..................... < –0.5dB

Storage Temperature................................ –65°C to 150°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, TA = T

PARAMETER CONDITIONS MIN TYP MAX UNITS

DC Characteristics

Supply Current

RVCCD 74 mA
RVCCA 65 mA
TVCCD 24 mA
TVCCA 6mA
RVCCD + RVCCA + TVCCD + TVCCA 195 mA

TTL Inputs (TXOFF, LPBK)

VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V

Differential Inputs (TPIN±, TXIN±)

TPIN+, TPIN–
Common Mode Input Voltage 2.2 V

TPIN+, TPIN–
Differential Input Voltage 1.5 V

TPIN+, TPIN–
Differential Input Resistance 10.0K Ω

TPIN+, TPIN–
Common Mode Input Current +10 µA

TXIN+, TXIN–
Input Voltage HIGH (VIH)V

TXIN+, TXIN–
Input Voltage LOW (VIL)V

TXIN+, TXIN–
Input Current LOW (IIL) 0.5 µA

TXIN+, TXIN–
Input Current HIGH (IIH) 50 µA

Differential Outputs (SD±, RXOUT±, TPOUT±)

SD+, SD–, RXOUT+, RXOUT–
Output Voltage HIGH (VOH) Note 3 VCC–1.025 VCC–0.88 V

SD+, SD–, RXOUT+, RXOUT–
Output Voltage LOW (VOL) Note 3 VCC–1.81 VCC–1.62 V

MIN

to T

MAX

, V

= 5V ±5%, RTSET = 2kΩ. (Note 1)

CC

CC

–1.165 VCC–0.88 V

CC

–1.810 VCC–1.475 V

CC

V

3

ML6673

ELECTRICAL CHARACTERISTICS (Continued)

PARAMETER CONDITIONS MIN TYP MAX UNITS

Differential Outputs (SD±, RXOUT±, TPOUT±) (Continued)

TPOUT+, TPOUT–
Output Current HIGH V

TPOUT+, TPOUT–
Output Current LOW V

TPOUT+, TPOUT–
Output Current Offset 0.5 mA

TPOUT+, TPOUT–V

OUT

= V

CC

Output Amplitude Error Note 2 –5.0 5.0 %
TPOUT+, TPOUT–V

= VCC ±1.1V

OUT

Output Voltage Compliance –2.0 +2.0 %

AC Characteristics

TPOUT+, TPOUT–
Rise/Fall Time 2.0 ns

TPOUT+, TPOUT–
Output Jitter 0.8 ns

RXOUT+, RXOUT–
Rise/Fall Time 2.0 ns

RXOUT+, RXOUT–
Output Jitter 2.0 ns

= VCC ± 0.5, Note 2 38.0 42.0 mA

OUT

= VCC ± 0.5, Note 2 0 0.5 mA

OUT

Note 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2. Output current amplitude is determined by I
Note 3. Output voltage levels are specified when terminated by 50Ω to V

= 64 x 1.25V/RTSET.

OUT

– 2V or equivalent load.

CC

4

FUNCTIONAL DESCRIPTION

ML6673

The ML6673 MLT-3 transceiver is a physical media
dependent transceiver that allows the transmission and
reception of 125 Mbaud data over shielded twisted pair
cable or category 5 unshielded twisted pair cable. It
provides a standard Physical Media Dependent (PMD)
interface compatible with many FDDI chip sets.

The transmit section accepts NRZI data, converting it to a
three level MLT-3 code and sending the information on a
two pin current driven transmitter. The transmitted output
passes through an external low pass filter and transformer
before entering the connectors to the STP or UTP cable.
The output amplitude of the transmitted signal is
programmable through the external RTSET resistor.

V

I

OUT

×64 1 25.

=

RTSET

For 100BASE-TX UTP application, the transmit amplitude
is 2VP-P differential achieved by setting RTSET = 2kΩ (1%).

The receive section accepts MLT-3 coded data after
passing through an isolation transformer and band
limiting filter. Before the data can be converted from MLT­3 back to NRZI, the adaptive equalizer is used to
compensate for the amplitude and phase distortion
incurred from the cable. The adaptive control section
determines the signal amplitude (and therefore the cable
length) and adjusts the equalizer accordingly.

The receiver also includes the Baseline Wander correction
circuitry. The circuit will compensate and track the DC
baseline wander caused by DC imbalance of the received
data. It will tolerate the test pattern as specified in the
ANSI X3T12 TP-PMD specification. A parallel 10pF
capacitor can be connected between TPIN+ and TPIN–
to improve Bit Error Rate.

The adaptive control block governs both the equalization
level as well as the signal detection status. Signal detect is
asserted when the equalizer control loop settles or when
loop back is asserted. When the input signal is small, the
equalization will be at its maximum.

After the signal has been equalized, it passes into the MLT-3
to NRZI converter where it is converted back to NRZI
and fed through the loopback multiplexer onto the
RXOUT± pins.

Figure 1 shows a timing diagram of NRZI data and the
equivalent MLT-3 data. The MLT-3 data shows the output
current I

for one side of the transmitter, either TPOUT+

OUT

or TPOUT–. The other transmit output pin will be the
complement. Whenever there is a change in level in
NRZI, MLT-3 will change levels too. The maximum
fundamental frequency of MLT-3 is half of the maximum
fundamental of NRZI.

Figure 2 shows a typical gain vs frequency plot of the
adaptive equalizer for 0, 25, 50, 75 and 100 meter
category 5 cable lengths.

ML6671 COMPATIBILITY
The ML6673 implements the Baseline Wander correction

circuit, in addition to providing the functionality of the
existing ML6671 device. The ML6673 is plug-compatible
with the ML6671 with the following note:

• In the ML6673 design, the following passive
components may be eliminated

— RSET resistor
— RTH resistor
— CAP1 capacitor
— CAP2 capacitor

IOUT

CURRENT (mA)

IOUT/2

NRZI DATA

MLT-3 DATA

20

15

10

0

8 1624324048566472808896

(nsec)

1

0

104

5

0

1 x 10

6

1 x 10

7

Figure 1. MLT-3 Encoding Figure 2. Equalization Range

1 x 10

8

1 x 10

9

5

ML6673

+5.0V

0.1µF

2.0K 1%

0.1µF

FILTER

TRANSFORMER

50

RTSET2

RTSET1

RVCCA

TO MIC

MODULE

CT

TPOUT+

50

TPIN+

TPOUT–

ML6673 TP-PMD

FROM MIC

FILTER

MODULE

TRANSFORMER

10pF

50

50

CMREF

TRANSCEIVER

FOR THE TRANSFORMER

FILTER MODULE, USE:

XFMRS INC. XF3506SIP

BEL FUSE 0558-5999-00

0.1µF

TPIN–

9.53K 1%

RGND RRSET1 RRSET2

VALOR PT4172

PULSE PE-68508

TVCCATVCCDRVCCD

+5.0V +5.0V +5.0V

0.1µF 0.1µF

+5.0V

0.1µF

Application Example of ML6673 Configured for 2.0V

Note 1. Split 100K ECL terminations are 82ý and 130ý to VCC and GND respectively.
Note 2. Recommended power supply bypass capacitors are 0.1µF with optional 10µF tantalum in parallel.
Note 3. Transformer turns ratio is 1:1.
Note 4. LPBK and TXOFF inputs are active LOW.

TXIN+

TXIN–

FROM PHY

SD+

NOTE 1

SD–

TO PHY

RXOUT+

RXOUT–

TO PHY

P-P

TGNDD TGNDA

TXOFF

LPBK

FROM PHY

Transmit Amplitude on C5 UTP.

6

PHYSICAL DIMENSIONS inches (millimeters)

Package: H32-7

32-Pin (7 x 7 x 1mm) TQFP

0.354 BSC
(9.00 BSC)

0.276 BSC
(7.00 BSC)

1

PIN 1 ID

25

ML6673

0º - 8º

0.003 - 0.008
(0.09 - 0.20)

8

0.032 BSC

(0.08 BSC)

0.012 - 0.018
(0.29 - 0.45)

0.485 - 0.495

(12.32 - 12.57)

0.450 - 0.456

(11.43 - 11.58)

1

0.276 BSC
(7.00 BSC)

17

Package: Q32

32-Pin PLCC

0.354 BSC
(9.00 BSC)

0.037 - 0.041
(0.95 - 1.05)

0.048 MAX

(1.20 MAX)

0.018 - 0.030
(0.45 - 0.75)

SEATING PLANE

0.098 - 0.112
(2.49 - 2.85)

0.042 - 0.048
(1.07 - 1.22)

9

0.050 BSC
(1.27 BSC)

PIN 1 ID

17

0.026 - 0.032
(0.66 - 0.81)

0.013 - 0.021
(0.33 - 0.53)

0.390 - 0.430

(9.90 - 10.92)

0.550 - 0.556

25

(13.97 - 14.12)

0.165 - 0.180
(4.06 - 4.57)

SEATING PLANE

0.585 - 0.595

(14.86 - 15.11)

0.148 - 0.156
(3.76 - 3.96)

0.019 - 0.021
(0.48 - 0.51)

0.490 - 0.530

(12.45 - 13.46)

0.025 - 0.045
(0.63 - 1.14)

(RADIUS)

7

ML6673

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML6673CQ 0°C to 70°C 32-Pin PLCC (Q32)
ML6673CH 0°C to 70°C 32-Pin TQFP (H32-7)

© Micro Linear 1997
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946; 2619299. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.

Micro Linear

8

is a registered trademark of Micro Linear Corporation

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San Jose, CA 95131

Tel: [phone]

Fax: [phone]

DS6673-01