Datasheet ML60851D Datasheet (OKI)

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Page 1

PEDL60851D-01

Semiconductor

ML60851D

USB Device Controller

This version: Jan. 2000

Preliminary

GENERAL DESCRIPTION

The ML60851D is a general purpose Universal Serial Bus (USB) device controller. The ML60851D provides a USB interface, control/status block, application interface, and FIFOs. The FIFO interface and two types of transfer have been optimized for BulkOut devices such as printers and BulkIn devices such as digital still cameras and image scanners. In addition, Mass Storage devices are also applicable to this device.

FEATURES

•

USB 1.1 compliant

•

Built-in USB transceiver circuit

•

Full-speed (12 Mb/sec) support

•

Supports printer device class, image device class, and Mass Storage device class

•

Supports three types of transfer; control transfer, bulk transfer, and interrupt transfer

•

Built-in FIFOs for control transfer

Two 8-byte FIFOs (one for receive FIFO and the other for transmit FIFO)

•

Built-in FIFOs for bulk transfer (available for either receive FIFO or transmit FIFO)

One 64-byte FIFO

Two 64-byte FIFOs

•

Built-in FIFO for interrupt transfer

One 8-byte FIFO

•

Supports one control endpoint, two bulk endpoint addresses, and one interrupt endpoint address

•

Two 64-byte FIFOs enable fast BulkOut transfer and BulkIn transfer

•

Supports 8 bit/16 bit DMA transfer

•

Supports protocol stall

•

is 3.0 V to 3.6 V

•

Supporting dual power supply enables 5 V application interface

•

Built-in 48 MHz oscillator circuit

•

Package options: 44-pin plastic QFP (QFP44-P-910-0.80-2K) (Product name: ML60851DGA) 44-pin plastic TQFP (TQFP44-P-1010-0.80-K) (Product name: ML60851DTB)

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BLOCK DIAGRAM

A7:A0

Application

D15:D0

Application

Module

(Local MCU)

Interface

RESET

INTR

DREQ

PEDL60851D-01

ML60851D

DACK

ML60851D

Status/Control

DPLL

Oscillator

XIN

XOUT

Protocol

Engine

USB

D+

Endpoint FIFO/ 8-byte Setup Register

Transceiver

D-

48 MHz

USB Bus

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PIN CONFIGURATION (TOP VIEW)

PEDL60851D-01

ML60851D

D+ D-

CC3

TEST1 TEST2

XIN

XOUT

RESET

CC5

GND

AD3

AD2

AD1

AD0

4443424140393837363534

1 2 3 4 5 6 7 8

9 10 11

1213141516171819202122

D15

D14

D13

D12

INTR

GND

44-Pin Plastic QFP

AD4

CC5

AD5

D11

AD6

D10

AD7

DREQ

DACK

ADSEL

ALE

D+

D-

CC3

TEST1 TEST2

XIN

XOUT

RESET

CC5

VSSV

AD3

AD2

AD1

AD0

4443424140393837363534

1 2 3 4 5 6 7 8

9 10 11

1213141516171819202122

INTR

D15

D14

D13

D12

44-Pin Plastic TQFP

AD4

CC5

AD5

D11

AD6

D10

AD7

DREQ

DACK

ADSEL

ALE

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PIN DESCRIPTION

Pin Symbol Type Description

1,2 D+, D- I/O USB data 6, 7 XIN, XOUT — Pins for external crystal oscillator 4, 5 TEST14, 2 I Test pins (normally “L”)

13 to 16,

19 to 22

35 to 38,

41 to 44 25 to 32 A7 to A0 I Address inputs

33 DACK I DMA acknowledge signal input pin 23 ALE I Address latch enable signal input pin 24 ADSEL I Address input mode select input pin. “H”: address/data multiplex

D15 to D18 I/O

AD7 to AD0 I/O

CS RD

INTR

DREQ

RESET

Data bus (MSB)

Data bus (LSB)/address inputs

Chip select signal input pin. LOW active

Read signal input pin. LOW active

Write signal input pin. LOW active

Interrupt request signal output pin

DMA request output pin

System reset signal input pin. LOW active.

ML60851D

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INTERNAL REGISTERS

Addresses and Names of Registers

Addresses Register Page

A5:A0

00h 01b —

01h 01b —

02h 01b — EP2RXFIFO Endpoint 2 Receive FIFO Data

03h 01b — Reserved

00h — 11b

01h — 11b

02h — 11b

03h — 11b

Read

A7, A6

Write

A7, A6

Symbol Register name

EP0RXFIFO Endpoint 0 Receive FIFO Data

EP1RXFIFO Endpoint 1 Receive FIFO Data

EP0TXFIFO Endpoint 0 Transmit FIFO Data

EP1TXFIFO Endpoint 1 Transmit FIFO Data

EP2TXFIFO Endpoint 2 Transmit FIFO Data

EP3TXFIFO Endpoint 3 Transmit FIFO Data

PEDL60851D-01

ML60851D

00h 11b 01b DVCADR Device Address Register

01h 11b 01b

02h 11b —

03h 11b —

04h 11b —

08h 11b 01b PKTRDY Endpoint Packet-Ready Register

09h 11b — EP0RXCNT Endpoint 0 Receive-Byte Count Register

0Ah 11b —

0Bh 11b —

0Ch 11b —

0Dh 11b —

0Eh — 01b CLRFIFO Transmit FIFO Clear Register

0Fh — 01b SYSCON System Control Register

10h 11b —

11h 11b —

12h 11b —

13h 11b —

14h 11b — WIndex LSB WIndex LSB Setup Register

15h 11b — WIndex MSB WIndex MSB Setup Register

16h 11b —

17h 11b —

1Ah 11b 01b

1Bh 11b 01b

1Ch 11b — INTSTAT Interrupt Status Register

1Dh 11b 01b DMACON DMA Control Register

1Eh 11b 01b

1Fh — —

DVCSTAT Device Status Register

PKTERR Packet Error Register

FIFOSTAT1 FIFO Status Register 1

FIFOSTAT2 FIFO Status Register 2

EP1RXCNT Endpoint 1 Receive-Byte Count Register

EP2RXCNT Endpoint 2 Receive-Byte Count Register

Reserved

REVISION Revision Register

BmRequest Type BmRequest Type Setup Register

bRequest bRequest Setup Register

WValue LSB WValue LSB Setup Register

WValue MSB WValue MSB Setup Register

WLength LSB WLength LSB Setup Register

WLength MSB WLength MSB Setup Register

POLSEL Assertion Select Register

INTENBL Interrupt Enable Register

DMAINTVL DMA Interval Register

Reserved

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ML60851D

Addresses and Names of Registers (Continued)

Addresses Symbol Register name Page

20h 11b — EP0RXCON Endpoint 0 Receive Control Register 32 21h 11b — EP0RXTGL Endpoint 0 Receive Data Toggle Register 32 22h 11b 01b EP0RXPLD Endpoint 0 Receive Payload Register 33 23h — — Reserved 24h 11b 01b EP1CON Endpoint 1 Control Register 34 25h 11b 01b EP1TGL Endpoint 1 Data Toggle Register 35 26h 11b 01b EP1PLD Endpoint 1 Payload Register 35 27h — — Reserved 28h — — Reserved

29h — — Reserved 2Ah — — Reserved 2Bh — — Reserved 2Ch — — Reserved 2Dh — — Reserved 2Eh — — Reserved 2Fh — — Reserved

30h 11b — EP0TXCON Endpoint 0 Transmit Control Register 36

31h 11b — EP0TXTGL Endpoint 0 Transmit Data Toggle Register 36

32h 11b 01b EP0TXPLD Endpoint 0 Transmit Payload Register 37

33h 11b 01b EP0STAT Endpoint 0 Status Register 38

34h 11b 01b EP2CON Endpoint 2 Control Register 40

35h 11b 01b EP2TGL Endpoint 2 Data Toggle Register 41

36h 11b 01b EP2PLD Endpoint 2 Payload Register 41

37h — — Reserved

38h 11b 01b EP3CON Endpoint 3 Control Register 42

39h 11b 01b EP3TGL Endpoint 3 Data Toggle Register 43 3Ah 11b 01b EP3PLD Endpoint 3 Payload Register 43 3Bh — — Reserved 3Ch — — Reserved 3Dh — — Reserved 3Eh — — Reserved 3Fh — — Reserved

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ML60851D

FUNCTIONS OF REGISTERS

End Point 0 Receive FIFO (EP0RXFIFO)

Read address 40h

Write address -

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware resetxxxxxxxx

After a bus reset xxxxxxxx

Definition EP0 Receive data (R)

The receive data from the host computer in the data state during a control Write transfer is stored in EP0RXFIFO. The EP0 receive data can be read out by the local MPU through reading the address 40h when the ML60851D issues an EP0 receive packet ready interrupt request. It is possible to read successively the data in the packet by reading continuously.

The EP2RXFIFO is cleared under the following conditions:

1. When the local MPU resets the EP0 receive packet ready bit (A “1” is written in PKTRDY(0)).

2. When a setup packet is received.

3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).

End Point 1 Receive FIFO (EP1RXFIFO)

Read address 41h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware resetxxxxxxxx

After a bus reset xxxxxxxx

Definition EP1 Receive data (R)

It is possible to read out the EP1 receive data by reading the address 41h. When EP1 is set for bulk reception (BULK OUT), The local MCU should read EP1RXFIFO when the ML60851D issues an EP2 packet ready interrupt request. It is possible to read successively the data in the packet by reading continuously. When the data transfer direction of EP1 is set as “Transmit”, all accesses to this address will be invalid. The EP1RXFIFO is cleared under the following conditions:

1. When an OUT token is received for EP1.

2. When the EP1 receive packet ready bit is reset. (A “1” is written in PKTRDY(1).)

3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).

Even when a DMA read with a 16-bit width is made from EP1RXFIFO, the address is A7:A0 = 41h.

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ML60851D

End Point 2 Receive FIFO (EP2RXFIFO)

Read address 42h

Write address

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware resetxxxxxxxx

After a bus reset xxxxxxxx

Definition EP2 Receive data (R)

—

It is possible to read out the EP2 receive data by reading the address 42h. When EP2 is set for bulk reception (Bulk OUT), the local MCU should read EP2RXFIFO when the ML60851D issues an EP2 packet ready interrupt request. It is possible to read successively the data in the packet by reading continuously. When the data transfer direction of EP2 is set as ‘Transmit’, all accesses to this address will be invalid. The EP2RXFIFO is cleared under the following conditions:

1. When an OUT token is received for EP2.

2. When the EP2 receive packet ready bit is reset. (A “1” is written in PKTRDY(2).)

3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).

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ML60851D

End Point 0 Transmit FIFO (EP0TXFIFO)

Read address —

Write address C0h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware resetxxxxxxxx

After a bus reset xxxxxxxx

Definition EP0 Transmit data (W)

The EP0 transmit data can be written in by writing to the address C0h. The receive data from the host in the data stage during a control read transfer is stored in EP0TXFIFO. When the ML60851D issues an EP0 transmit packet ready interrupt request, the local MCU writes the transmit data to the address C0h. It is possible to write the packet data successively by writing continuously.

The EP0 TXFIFO is cleared under the following conditions:

1. When an ACK is received from the host for the data transmission from EP0.

2. When a setup packet is received.

End Point 1 Transmit FIFO (EP1TXFIFO)

Read address

Write address C1h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware resetxxxxxxxx

After a bus reset xxxxxxxx

Definition EP1 Transmit data (W)

—

The EP1 transmit data can be written in by writing to the address C1h. When EP1 has been set for bulk transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851D issues an EP1 packet ready interrupt request. It is possible to write the packet data successively by writing continuously. When the data transfer direction of EP1 is set as ‘Receive’, all accesses to this address will be invalid.

The EP1 transmit FIFO is cleared under the following conditions:

1. When an ACK is received from the host for the data transmission from EP1.

2. When the local MCU writes a “1” in the EP1FIFO clear bit (CLRFIFO(1)).

Even when a DMA write with a 16-bit width is made in EP1TXFIFO, the address is A7:A0 = 41h.

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ML60851D

End Point 2 Transmit FIFO (EP2TXFIFO)

Read address —

Write address C2h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware resetxxxxxxxx

After a bus reset xxxxxxxx

Definition EP2 Transmit data (W)

The EP2 transmit data can be written in by writing to the address C2h. When EP2 has been set for bulk transmission (BULK IN), The local MCU should write the transmit data in EP1TXFIFO when the ML60851D issues an EP2 packet ready interrupt request. It is possible to write the packet data successively by writing continuously. When the data transfer direction of EP2 is set as “Receive”, all accesses to this address will be invalid.

The EP2 TXFIFO is cleared under the following conditions:

1. When an ACK is received from the host for the data transmission from EP2.

2. When the local MCU writes a “1” in the EP2FIFO clear bit (CLRFIFO(2)).

End Point 3 Transmit FIFO (EP3TXFIFO)

Read address —

Write address C3h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware resetxxxxxxxx

After a bus reset xxxxxxxx

Definition EP3 Transmit data (W)

The EP3 transmit data can be written in by writing to the address C3h. Make the local MCU write the transmit data in EP3TXFIFO when the ML60851D issues an EP3 packet ready interrupt request. It is possible to write the packet data successively by writing continuously.

The EP3 TXFIFO is cleared under the following conditions:

1. When an ACK is received from the host for the data transmission from EP3.

2. When the local MCU writes a “1” in the EP3FIFO clear bit (CLRFIFO(3)).

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Semiconductor

ML60851D

Device Address Register (DVCADR)

Read address C0h

Write address 40h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition Device address (R/W)

The local MCU writes in this register the device address given by the SET_ADDRESS command from the host. Thereafter, the ML60851D responds only to the token specifying this address among all the tokens from the host computer. The default value is the address D6:D0 = 00h.

Note 1: It is possible to carry out addressing using a 7-bit address because up to 127 devices can be

connected according to the USB standard.

Note 2: The bit D7 is fixed at “0”, and even if a “1” is written in the bit D7, it will be invalid.

Device State Register (DVCSTAT)

Read address C1h

Write address 41h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000001

After a bus reset 00000001

Definition 0 0

Default state (R/W) Address state (R/W) Configuration state (R/W) Suspend state (R) Remote wake-up (R/W) USB bus reset status clear (W)

This is a register for displaying the status of the device. The functions of the different bits are described below: The bits D7 and D6 are fixed at “0” and even if a “1” is written in these bits, the write operation will be invalid.

Default state:

This bit is asserted in the initial state. The default state is valid from the time the power is switched ON and the hardware resetting is complete. There is no need to write a “0” in this bit.

Address state:

When a SET_ADDRESS request arrives, the local MCU writes the device address in the device address register. If necessary, by writing a “1” in this bit also at that time, it is possible to give an indication that the ML60851D has entered the address state. Since the content of this bit does not affect the operation of the ML60851D, there is no need to write in this bit if it will not be read out.

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Configuration state:

When the local MPU asserts the configuration bits EP1CON, EP2CON, or EP3CON in response to a SET_CONFIGURATION request from the host computer when this IC is in the address state, by writing a “1” in this bit also, if necessary, at that time, it is possible to give an indication that the ML60851D has entered the configuration state. Since the content of this bit does not affect the operation of the ML60851D, there is no need to write in this bit if it will not be read out.

Remarks: When all these three states are “1”, it means that this IC is normally operating. However, since these bits do not affect the operation of the ML60851D, there is no need to write in these bits if they will not be read out.

Suspend state:

When the idle condition continues for more than 3ms in the USB bus, the ML60851D automatically asserts this bit thereby indicating that it is going into the suspend state. At the same time, bit D6 of the interrupt

status register INTSTAT is asserted and the

INTR

pin is asserted. With this, the local MCU can suppress the current consumption. This bit is deasserted when the EOP of any type of packet is received.

Remote wake-up:

The ML60851D is in the suspend state, the remote wake-up function is activated when the local MCU asserts this bit. When this bit is written while 5ms have not yet elapsed in the idle condition, the remote wake-up signal is output after waiting for the idle condition to continue for the full 5ms period. Further, when this bit is written after the idle condition has persisted for 5ms or more, the remote wake-up signal is output immediately after this bit is written. This bit is deasserted automatically when the suspend state is released by receiving the resume instruction over the USB bus.

ML60851D

USB bus reset status clear:

When the ML60851D is in the USB bus reset interrupt state (bit D5 of the interrupt status register, that is the USB bus reset interrupt status bit is “1” and the

INTR

pin is asserted), it is possible to clear the interrupt

status by writing a “1” in this bit. (This makes the USB bus reset interrupt status bit “0” and deassertes

INTR

.) Although this bit can be read out, the read out value will always be “0”.

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ML60851D

Packet Error Register (PKTERR)

Read address C2h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition 0 0

Bit stuff error (R) Data CRC error (R) Address CRC error (R) PID Error (R)

Each bit is asserted when the corresponding error occurs and is deasserted when SOP is received. This register is used to report the error information. This register is useful for the tests during development, or for preparing the error frequency measurement report. This register is not particularly required for the specification of commercial a product.

FIFO Status Register 1 (FIFOSTAT1)

Read address C3h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00001010

After a bus reset 00001010

Definition 0 0

Receive FIFO0 Full (R) Receive FIFO0 Empty (R) FIFO1 Full (R) FIFO1 Empty (R)

This register reports the statuses of the EP0RXFIFO and the FIFO for EP1. Normally, there is no need to read this register because it is sufficient to read the packet ready status before reading out or writing in a FIFO.

Receive FIFO0 Full: This bit becomes “1” when 8-bytes of data are stored in the EP0RXFIFO. This bit is

not set to “1” when a packet less than 8 bytes long (a short packet) is stored in. Receive FIFO0 Empty: This bit will be “1” when the EP0RXFIFO0 is empty. FIFO1 Full: This bit becomes “1” when 64 bytes of data is stored in the FIFO for EP1. This is true

during both transmission and reception. This bit does not become “1” in the case of a

short packet. The FIFO for EP1 has a two-layer structure and can store up to 128

bytes of data. This bit indicates the status of the FIFO in which data being written at

that time. In other words, this bit indicates the status of the FIFO into which the host

computer is writing data when EP1 is receiving data, and of the FIFO into which the

local MCU is writing data when EP1 is transmitting data. FIFO1 Empty: This bit becomes “1” when the FIFO for EP1 is empty. This is true during both

transmission and reception. The FIFO for EP1 has a two-layer structure and can store

up to 128 bytes of data. This bit indicates the status of the FIFO which is being read

out at that time.

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FIFO0 Status Register 2 (FIFOSTAT2)

Read address C4h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00101010

After a bus reset 00101010

Definition 0 0

PEDL60851D-01

ML60851D

Transmit FIFO0 Full (R) Transmit FIFO0 Empty (R) FIFO2 Full (R) FIFO2 Empty (R) FIFO3 Full (R) FIFO3 Empty (R)

This register reports the statuses of the EP0TXFIFO, the FIFO for EP2, and the FIFO for EP3. Normally, there is no need to read this register because it is sufficient to read the packet ready status before reading out or writing in a FIFO.

Transmit FIFO0 Full: This bit becomes “1” when 8-bytes of data is stored in the EP0TXFIFO. This bit is

not set to “1” when a packet less than 8 bytes (a short packet) is written in. Transmit FIFO0 Empty: This bit will be “1” when the EP0 transmit FIFO0 is empty. FIFO2 Full: This bit becomes “1” when 64 bytes of data is either stored or written in the FIFO for

EP2. This bit does not become “1” in the case of a short packet. FIFO2 Empty: This bit becomes “1” when the FIFO of EP2 is empty. FIFO3 Full: This bit becomes “1” when 64 bytes are written in the FIFO for EP3. This bit does not

become “1” in the case of a short packet. FIFO3 Empty: This bit becomes “1” when the FIFO for EP3 is empty.

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ML60851D

End Point Packet Ready Register (PKTRDY)

This register indicates whether or not the preparations for reading out or writing in a packet data have been completed. In addition, this register is also used for controlling the handshake packet (ACK/NAK)

Read address C8h

Write address 48h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition 0

EP0 Receive packet ready (R/Reset) EP1 Receive packet ready (R/Reset) EP2 Receive packet ready (R/Reset)

EP0 Transmit packet ready (R/Set) EP1 Transmit packet ready (R/Set) EP2 Transmit packet ready (R/Set) EP3 Transmit packet ready (R/Set)

This is the register for indicating that the local MCU can request a read/write of the FIFO for each EP. The logical sums (AND) of each of these bits and the corresponding bits of INTENBL become the bits of INTSTAT.

The ML60851D asserts a receive packet ready bit (set to “0”) and generates an interrupt cause. The local MCU resets the receive packet ready bit after completion of the interrupt servicing (such as taking out data from the corresponding receive FIFO, etc.,).

The ML60851D deasserts a transmit packet ready bit and generates an interrupt cause. The local MCU sets the receive packet ready bit after completion of the interrupt servicing (such as writing data in the corresponding transmit FIFO, etc.,). The bit D3 is fixed at “0”, and even if a “1” is written in this bit, that write operation will be invalid. The operations of the different bits of PKTRDY are described in detail below.

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EP0 Receive packet ready bit (D0)

This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D0 bit.

The conditions of asserting and deasserting this bit are the following.

Bit name Asserting condition Action when asserted

EP0 Receive packet ready (D0)

1. When data is received in EP0 and storing of one packet of receive data in EP0RXFIFO is completed.

2. When a setup packet is received during a control Read or a control Write transfer.

EP0 is locked (that is, an NAK is returned automatically when a data packet is received from the host computer).

(In the case of the asserting condition 1, the local MCU can read EP0RXFIFO.)

Bit name Deasserting condition Action when deasserted

EP0 Receive packet ready (D0)

1. When the local MCU resets (writes a “1” in) this bit.

2. When the local MCU resets the setup ready bit during a control Write transfer.

Reception is possible in EP0.

ML60851D

R/Reset: Reading possible/ Reset when a “1” is written R/Set: Reading possible/ Set when a “1” is written

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ML60851D

EP1 Receive Packet Ready Bit (D1)

This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D1 bit. The conditions of asserting and deasserting this bit are the following. EP1 has a two-layer FIFO, and even the packet ready bits are present independently for layer A and layer B. The switching between these two layers is done automatically by the ML60851D.

Bit name Asserting condition Action when asserted

EP1 Receive packet ready (D1)

When an error-free packet is received in either layer A or layer B.

The local MCU can read the EP1RXFIFO. EP1 is locked when both layer A and layer B have received a packet data.

Bit name Deasserting condition Action when deasserted

EP1 Receive packet ready (D1) When the local MCU resets (writes a

“1”) in the bits of both layer A and layer B.

Reception is possible in EP1 when at least one of the bits of layer A and layer B has been reset.

See the explanation of the operation of the two-layer FIFO given in the Section on ‘Functional Description’.

EP2 Receive Packet Ready Bit (D2)

This bit can be read by the local MCU. Further, this bit can be set to “0” by writing “1” to the D2 bit. The conditions of asserting and deasserting this bit are the following.

Bit name Asserting condition Action when asserted

EP2 Receive packet ready (D2) When an error-free packet is

received.

EP2 is locked.

Bit name Deasserting condition Action when deasserted

EP2 Receive packet ready (D2) When the local MCU resets (writes a

“1” in) this bit.

Data reception is possible in EP2.

EP0 Transmit Packet Ready Bit (D4)

This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D4 bit. The conditions of asserting and deasserting this bit are the following.

Bit name Asserting condition Action when asserted

EP0 Transmit packet ready (D4) When the local MCU sets this bit. Data transmission is possible from

EP0.

Bit name Deasserting condition Action when deasserted

EP0 Transmit packet ready (D4)

1. When an ACK is received from the host computer in response to the data transmission from EP0.

2. When a setup packet is received.

EP0 is locked. In other words, an NAK is returned automatically when an IN token is received from the host computer.

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ML60851D

EP1 Transmit Packet Ready Bit (D5)

This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D5 bit. The conditions of asserting and deasserting this bit are the following. EP1 has a two-layer FIFO, and even the packet ready bits are present independently for layer A and layer B. The switching between these two layers is performed automatically by the ML60851D.

Bit name Asserting condition Action when asserted

EP1 Transmit packet ready (D5)

When the local MCU has set the bits of both layer A and layer B.

Data transmission is possible from EP1 when the bit for at least one of layer A and layer B has been asserted.

Bit name Deasserting condition Action when deasserted

EP1 Transmit packet ready (D5) When an ACK is received from the

host computer for the data transmission from either layer A or layer B.

EP1 is locked when both layer A and layer B have not prepared the transmit data.

See the explanation of the operation of the two-layer FIFO given in the Section on ‘Functional Description’.

EP2 Transmit Packet Ready Bit (D6)

This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D6 bit. The conditions of asserting and negating this bit are the following.

Bit name Asserting condition Action when asserted

EP2 Transmit packet ready (D6) When the local MCU has set this bit. Data transmission is possible from

EP2.

Bit name Deasserting condition Action when deasserted

EP2 Transmit packet ready (D6)

When an ACK is received from the host computer in response to the data transmission from EP2.

EP2 is locked.

EP3 Transmit Packet Ready Bit (D7)

This bit can be read by the local MCU. Further, this bit can be set to “1” by writing “1” to the D7 bit. The conditions of asserting and deasserting this bit are the following.

Bit name Asserting condition Action when asserted

EP3 Transmit packet ready (D7) When the local MCU has set this bit. Data transmission is possible from

EP3.

Bit name Deasserting condition Action when deasserted

EP2 Transmit packet ready (D7) When an ACK is received from the

host computer in response to the data transmission from EP3.

EP3 is locked.

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PEDL60851D-01

Semiconductor

ML60851D

End Point 0 Receive Byte Count Register (EP0RXCNT)

Read address C9h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition 0 Byte count of EP0 (R)

The ML60851D automatically counts the number of bytes in the packet being received by EP0 and stored it in this register. Although the counting is performed up to the maximum packet size entered in the payload register in the case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to this value and reads the data of one packet from the EP0RXFIFO.

The EP0 receive byte count register is cleared under the following conditions:

1. When the local MCU resets the EP0 receive packet ready bit (by writing a “1” in PKTRDY(0)).

2. When a setup packet is received.

3. When the local MCU writes a “0” in the stall bit (EP0STAT(2)).

End Point 1 Receive Byte Count Register (EP1RXCNT)

Read address CAh

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition 0 Byte count of EP1 (R)

The ML60851D automatically counts the number of bytes in the packet being received by EP1 and stored it in this register. Although the counting is performed up to the maximum packet size entered in the payload register in the case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to this value and reads the data of one packet from the EP1 receive FIFO.

This register is invalid when the EP1 transfer direction is set as ‘Transmit’.

The EP1 receive byte count register is cleared under the following conditions:

1. When an OUT token is received for EP1.

2. When the EP1 receive packet ready bit is reset (by writing a “1” in PKTRDY(1)).

3. When the local MCU writes a “0” in the stall bit (EP1CON(1)).

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PEDL60851D-01

Semiconductor

ML60851D

End Point 2 Receive Byte Count Register (EP2RXCNT)

Read address CBh

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition 0 Byte Count of EP2 (R)

The ML60851D automatically counts the number of bytes in the packet being received by EP2 and stored it in this register. Although the counting is performed up to the maximum packet size entered in the payload register in the case of a full packet, the count will be less than this value in the case of a short packet. The local MCU refers to this value and reads the data of one packet from the EP2RXFIFO.

This register is invalid when the EP2 transfer direction is set as ‘Transmit’.

The EP2 receive byte count register is cleared under the following conditions:

1. When an OUT token is received for EP2.

2. When the EP2 receive packet ready bit is reset (by writing a “1” in PKTRDY(2)).

3. When the local MCU writes a “0” in the stall bit (EP2CON(1)).

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Semiconductor

Revision Register (REVISION)

Read address CDh

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset

After a bus reset

Definition

Revision No. of Chip

Transmit FIFO Clear Register (CLRFIFO)

Read address —

Write address 4Eh

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset

After a bus reset

Definition 0 0 0 0

Cannot be read (indeterminate)

PEDL60851D-01

ML60851D

EP1 Transmit FIFO Clear EP2 Transmit FIFO Clear EP3 Transmit FIFO Clear

EP1 to EP3 FIFO Clear: When each EP has been set for transmission, by writing a “1” in these bits, the

corresponding FIFOs are cleared at the Write pulse and also the corresponding EP Packet Ready bits are reset.

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PEDL60851D-01

Semiconductor

ML60851D

System Control Register (SYSCON)

Read address —

Write address 4Fh

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset

After a bus reset

Definition 0 0 0

Cannot be read (indeterminate)

Software Reset Oscillation Stop Command

Software Reset: When a “1” is written in this bit, a system reset is executed at the Write pulse. This is

functionally equivalent to a hardware reset.

Oscillation Stop command: The Oscillation circuit of the ML60851D stops and goes into the standby state when

1010b is written in D7 to D4 (that is, when A0h is written in this register). Once the IC goes into the standby state, to start communication with the USB bus thereafter, it is necessary to carry out again disconnecting, connecting, and enumeration. Even when the Oscillation has stopped, although it is possible to read on write the registers, it is impossible to read or write the FIFO.

The oscillation can be started again by asserting the

RESET

pin. The oscillation can

be restarted even by a software reset.

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Semiconductor

bmRequest Type Setup Register

Read address D0h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition Type Receiving side

PEDL60851D-01

ML60851D

0 = Device 1 = Interface 2 = End point 3 = Others 4 to 31 = Reserved

0 = Standard 1 = Class 2 = Vendor 3 = Reserved

Data Transfer Direction

0 = From the host computer to the device 1 = From the device to the host computer

The format of the device request conforms to Section 9.3 of the USB standards. The eight bytes of setup data sent by the host computer during the setup stage of control transfer are stored automatically in eight registers including this register.

bRequest Setup Register

Read address D1h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition Request Code

The request code indicating the contents of the device request is stored automatically in this register during the setup stage of control transfer.

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Semiconductor

wValue LSB Setup Register

Read address D2h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition wValue LSB

A parameter of device request is stored in this register during the setup stage of control transfer.

wValue MSB Setup Register

Read address D3h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition wValue MSB

A parameter of device request is stored in this register during the setup stage of control transfer.

PEDL60851D-01

ML60851D

wIndex LSB Setup Register

Read address D4h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition wIndex LSB

A parameter of device request is stored in this register during the setup stage of control transfer.

wIndex MSB Setup Register

Read address D5h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition wIndex MSB

A parameter of device request is stored in this register during the setup stage of control transfer.

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Semiconductor

wLength LSB Setup Register

Read address D6h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition wLength LSB

A parameter of device request is stored in this register during the setup stage of control transfer.

wLength MSB Setup Register

Read address D7h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition wLength MSB

A parameter of device request is stored in this register during the setup stage of control transfer.

PEDL60851D-01

ML60851D

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Semiconductor

Polarity Selection Register (POLSEL)

Read address DAh

Write address 5Ah

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset The previous value is retained

Definition 00000

PEDL60851D-01

ML60851D

Polarity of INTR 0 = Active Low 1 = Active High Polarity of DREQ 0 = Active Low 1 = Active High Polarity of DACK 0 =Active High 1 =Active Low

The local MCU can set the operating conditions of the ML60851D. The bits D7 to D3 are fixed at “0” and even if “1”s are written in them, they are ignored.

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Interrupt Enable Register (INTENBL)

Read address DBh

Write address 5Bh

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000001

After a bus reset The previous value is retained

Definition

Setup ready Interrupt Enable

EP1 Packet Ready

EP2 Packet Ready

PEDL60851D-01

ML60851D

Interrupt Enable

EP0 Receive Packet

Ready Interrupt Enable

EP0 Transmit Packet

Ready Interrupt Enable

USB Bus Reset Interrupt Enable

Suspend State Interrupt Enable

EP3 Packet Ready Interrupt Enable

The interrupts that can be accepted are set in this register. It is possible to change the setting of interrupt enable or disable dynamically depending on the operating conditions. There is a correspondence between this register the interrupt status register described next in terms of the bit numbers and the corresponding interrupt factors.

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Interrupt Status Register (INTSTAT)

Read address DCh

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset

Definition

See

below

See

below

See

below

See

below

PEDL60851D-01

ML60851D

Setup Ready Interrupt Status

EP1 Packet Ready Interrupt Status

EP2 Packet Ready Interrupt Status

EP0 Receive Packet Ready Interrupt Status

EP0 Transmit Packet Ready Interrupt Status

USB Bus Reset Interrupt Status

Suspend State Interrupt Status

EP3 Packet Ready Interrupt Status

Setup Ready Interrupt Status: When bit D0 of the interrupt enable register (INTENBL) is “1”, the content of bit

D0 of the EP0 status register (EP0STAT) is copied here. This bit is “0” when D0 of INTENBL is “0”. In other words, when the eight bytes of setup data are received in the setup stage of control transfer and are correctly stored in the setup

registers, this bit is set to “1” and the

INTR

pin is asserted.

EP1 Packet Ready Interrupt Status: When bit D1 of the interrupt enable register (INTENBL) is “1”, the negation of

the content of bit D1 or of bit D5 of the end point packet ready register (PKTRDY) is copied here. This bit is “0” when bit D1 of INTENBL is “0”. The value at the time of a bus reset is determined based on the value of INTENBL and the EP transfer direction at that time, and also based on the value of the packet ready bit for that EP. (If the EP1 transfer direction has been set as “Receive”, the negation of D1 is stored here, and the negation of D5 is stored if the transfer direction has been set as “Transmit”.) During data reception, the packet ready interrupt is generated when one packet of receive data is correctly stored in one of the two FIFO layers of EP1. During transmission, the packet ready interrupt is generated when data transmission has been completed from (and writing becomes possible again) one of the two FIFO layers of EP1.

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PEDL60851D-01

Semiconductor

ML60851D

EP2 Packet Ready Interrupt Status: When bit D2 of the interrupt enable register (INTENBL) is “1”, the negation

of bit D2 or bit D6 of the end point packet ready register (PKTRDY) is copied here. This bit is “0” when bit D2 of INTENBL is “0”. The value at the time of a bus reset is determined based on the value of INTENBL and the EP transfer direction at that time, and also based on the value of the packet ready bit for that EP.

(If the EP2 transfer direction has been set as “Receive”, the negation of D2 is stored here, and the negation of D6 is stored if the transfer direction is has been set as “Transmit”.) During data reception, the packet ready interrupt is generated when one packet of receive data is correctly stored in the FIFO of EP2. During transmission, the packet ready interrupt is generated when data transmission has been completed from (and writing becomes possible again) the FIFO of EP2.

EP0 Receive Packet Ready Interrupt Status: When bit D3 of the interrupt enable register (INTENBL) is “1”, the

content of bit D0 of the end point packet ready register (PKTRDY) is copied here. This bit is “0” when bit D3 of INTENBL is “0”. In other words, when one data packet is received in the data stage of control transfer and is

correctly stored in the EP0RXFIFO, this bit is set to “1” and the

INTR

pin is asserted.

EP0 Transmit Packet Ready Interrupt Status: When bit D4 of the interrupt enable register (INTENBL) is “1”, the

negation of the content of bit D4 of the end point packet ready register (PKTRDY) is copied here. This bit is “0” when bit D4 of INTENBL is “0”. The value at the time of a bus reset is determined based on the value of INTENBL and the EP transfer direction at that time, and also based on the value of the packet ready bit of that EP. In other words, when the transmission from the EP0RXFIFO is completed (and writing is possible again in the FIFO) in the data stage of control transfer, this bit is set to “1” and the

INTR

pin is asserted.

USB Bus Reset Interrupt Status: When bit D5 of the interrupt enable register (INTENBL) is “1”, this bit becomes

“1” during a bus reset. This bit is “0” when bit D5 of INTENBL is “0”. The value at the time of a bus reset is determined based on the value of INTENBL and the EP transfer direction at that time, and also based on the value of the packet ready bit of that EP. Write a “1” in bit D5 of the device status register to return this bit to “0”.

Suspend State Interrupt Status: When bit D6 of the interrupt enable register (INTENBL) is “1”, the content of bit

D3 of the device state register (DVCSTAT) is copied here. This bit is “0” when bit D6 of INTENBL is “0”.

EP3 Packet Ready Interrupt Status: When bit D7 of the interrupt enable register (INTENBL) is “1”, the negation

of bit D7 of the end point packet ready register (PKTRDY) is copied here. This bit is “0” when bit D7 of INTENBL is “0”. The value at the time of a bus reset will be determined based on the value of INTENBL and the EP transfer direction at that time, and also based on the value of the packet ready bit of that EP.

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Semiconductor

DMA Control Register (DMACON)

Read address DDh

Write address 5Dh

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset The previous value is retained

Definition 0 0

PEDL60851D-01

ML60851D

DMA Enable 0 = DMA Inhibited 1 = DMA Transfer of EP1 is

enabled DMA Address Mode 0 = Single address mode 1 = Dual address mode

Byte Count 0 = The byte count is not inserted. 1 = The byte count data is inserted in the

leading byte or the leading word of the

transfer data. (Note 1) DMA Transfer Data Width 0 = Byte wide (8 bits) 1 = Word wide (16 bits) (Note 2) DMA Transfer Mode 0 = Single transfer mode 1 = Demand transfer mode Halting DMA Transfer 0 = Normal operation 1 = The DREQ pin is deasserted.

Note 1: In the 16-bit mode, the upper byte of the leading word is 00h. Note 2: The allocation is made in the little-endian sequence of the upper byte followed by the LSB. In

other words, the lower byte corresponds to AD0 to AD7 and the MSB corresponds to D8 to D15. In the 16-bit mode, when the packet size is an odd number of bytes, the upper byte of the last word is 00h.

Note 3: Make sure that all bits other than D7, that is, bits D4 to D0, are set completely during initialization

(at the latest, before the token packet for EP1 arrives) and are not modified thereafter. When wanting to temporarily halt the DMA transfer in the middle, write a “1” in D7. When the transfer is restarted by writing a “0” in D7, it is possible to restart the transfer from the byte (or word) next to the one a the time the transfer was halted.

Note 4: The bits D6 and D5 are fixed at “0”. Even if a “1” is written in them, it will be invalid.

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PEDL60851D-01

Semiconductor

ML60851D

DMA Interval Register (DMAINTVL)

Read address DEh

Write address 5Eh

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset The previous value is retained

Definition Interval time

This register is used for specifying the interval of the single DMA transfer mode, that is, the interval from the completion of the previous byte (or word) DMA transfer until DREQ is asserted again. The time per bit is 84ns (12MHz, one period). Interval time = (DREQ enable time) + 84 x n (ns) See DMA timings (1), (2), (5), and (6) for details of the DREQ enable time.

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PEDL60851D-01

Semiconductor

ML60851D

End Point 0 Receive Control Register (EP0RXCON)

Read address E0h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000001

Definition 0000000

Configuration Bit (R)

Transfer Type 00 = Control transfer End Point Address

Configuration Bit: The configuration bit of EP0 becomes “1” at the time of an USB bus reset. The packets sent

by the host computer to EP0 are received when this bit is “1”. This IC does not respond to any transactions with this EP when this bit is “0”.

The transfer mode of EP0 is a control transfer and the end point address is fixed at 0h. Therefore, the values of D6 to D2 are fixed and other values written in them are invalid.

End Point 0 Receive Data Toggle Register (EP0RXTGL)

Read address E1h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset0000000x

After a bus reset 0000000 x

Definition 0000000

Data Sequence Toggle Bit (R)

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PEDL60851D-01

Semiconductor

ML60851D

End Point 0 Receive Payload Register (EP0RXPLD)

Read address E2h

Write address 62h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00001000

After a bus reset 00001000

Definition 00001000

Maximum packet size

Maximum packet size: Since the FIFO capacity for EP0 in the ML60851D is 8 bytes, write 08h in the

bMaxPacketSize0 byte of the device descriptor. The maximum packet size is fixed at 8 bytes in this register EP0RXPLD. When a packet longer than 8 bytes is received, the stall bit of the EP0 status register is asserted and the stall status is returned to the host computer.

The content of this register is fixed at 08h. This value will not change even if any other value is written in this register.

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Semiconductor

End Point 1 control Register (EP1CON)

Read address E4h

Write address 64h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset 0 0 0 1 1 0 x 0

After a bus reset 000110x0

Definition 00110

PEDL60851D-01

ML60851D

Configuration Bit (R/W)

Stall Bit (R/W)

Transfer Type 10 = Bulk Transfer End point Address (R)

Transfer Direction (R/W) 0 = Receive, 1 = Transmit

Configuration Bit: The local MCU should write “1” in this bit during the status stage of control transfer when a

“Set Configuration” request is received from the host computer to make EP1 active. When this bit is “1”, the exchange of data between the host computer and EP1 is enabled. When this bit is “0”, this IC does not respond to any transactions with this EP.

Stall Bit: When a data packet is received with a number of bytes more than the maximum packet size set

in the EP1 payload register, the ML60851D automatically sets this bit to “1”. It is also possible for the local MCU to write a “1” in this bit. When this bit is “1”, the stall handshake is automatically returned to the host computer in response to the packet transmitted by the host computer to the end point. In addition, the packet ready status is not asserted and even the

INTR

pin is not asserted.

The EP1 transfer mode is set as a bulk transfer and the end point address is 1h. Therefore, the bits D6 to D2 have fixed values, and other values written in them are ignored.

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PEDL60851D-01

Semiconductor

ML60851D

End Point 1 Data Toggle Register (EP1TGL)

Read address E5h

Write address 65h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition 0000000

Data Sequence Toggle Bit (R/Reset

)

Data Sequence Toggle Bit: When initializing an EP, write a “1” in this bit to reset the toggle bit of the data

packet and specify PID of DATA0 (this bit also becomes “0”). Thereafter, the synchronous operation is made automatically based on the data sequence toggling mechanism.

The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it will be invalid.

End Point 1 Payload Register (EP1PLD)

Read address E6h

Write address 66h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset0xxxxxxx

After a bus reset 0xxxxxxx

Definition 0 Maximum packet size (R/W)

Maxi mum Pa cket Size: The value of wMaxPacketSize of the end point descriptor selected by the Set_Configuration

request from the host computer should be written in this register by the local MCU. The packet size of packets other than short packets is specified in units of a byte. The value can be one of 40h (64 bytes), 20h (32 bytes), 10h (16 bytes), and 08h (8 bytes). During data reception by EP1, if a packet with more number of bytes than that specified here is received, the receive packet ready bit is not asserted, and the stall bit is set during EOP and the stall handshake is returned to the host computer. On the other hand, when EP1 is being used for transmission, the transmit packet ready bit is set automatically when the writing of data of the number of bytes set in this register (maximum packet size) by the DMA controller is completed.

Bit D7 is fixed at “0”, and even if a “1” is written, it will be ignored.

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Semiconductor

End Point 0 Transmit Control Register (EP0TXCON)

Read address F0h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset01000000

After a bus reset 01000001

Definition 0100000

PEDL60851D-01

ML60851D

Configuration Bit (R)

Transfer Type 00 = Control transfer FIFO Number

Configuration Bit: The configuration bit of EP0 becomes “1” during an USB bus reset (both D+ and D- being “0”

for more than 2.5µs). Packets can be sent from this end point to the host computer when this bit is “1”. This IC does not respond to any transactions with this EP when this bit is “0”.

The transfer mode of EP0 is a control transfer and the end point address is fixed at 0h. Therefore, the values of D6 to D2 are fixed and other values written in them are invalid.

End Point 0 Transmit Data Toggle Register (EP0TXTGL)

Read address F1h

Write address —

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset0000000x

After a bus reset 0000000 x

Definition 0000000

Data Sequence Toggle Bit (R)

The synchronization based on the data sequence toggling mechanism is carried out automatically by the ML60851D.

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PEDL60851D-01

Semiconductor

ML60851D

End Point 0 Transmit Payload Register (EP0TXPLD)

Read address F2h

Write address 72h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset0xxxxxxx

After a bus reset 0xxxxxxx

Definition 0 Maximum Packet Size (R/W)

Maximum packet size: This is a register that has no relationship with the operation of the ML60851D, and can

be used as a general purpose register. Bit D7 is fixed at “0”.

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Semiconductor

End Point 0 Status Register (EP0STAT)

Read address F3h

Write address 73h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset 0 0 0 0 0 x 0 0

After a bus reset 00000x00

Definition 0 0 0 0

PEDL60851D-01

ML60851D

Setup Ready (R/Reset)

Stall Bit (R/W)

EP0 Stage (R) 00 = Setup stage 01 = Data stage 10 = Status stage

Setup Ready: This bit is set automatically when a proper setup packet arrives in the 8-byte setup register, and

the EP0RXFIFO is locked. If D0 of INTENBL has been asserted, the

INTR

pin is also asserted automatically when this bit is set. The local MCU should write a “1” in this bit after the reading out the 8-byte setup data. When this is performed, the setup ready bit is reset and

INTR

the

pin also is deasserted. During a control write, even the packet ready bit of EP0 is reset simultaneously, the lock condition is released, and it becomes possible to receive packets by EP0 during the data stage.

The register value will not change even if a “0” is written in this bit.

Stall bit: During EP0 reception (in the data stage of a control write transfer), the ML60851D

automatically sets this bit to “1” when a packet with a number bytes more than the maximum packet size written in EP0RXPLD is received (or when EOP is missing).

Bits D7 to D5 and D1 are fixed at “0”, and other values written in them are invalid.

EP0 Stage: Indicates the stage transition during a control transfer. The transition conditions between the

different stages are shown in the following stage transition diagram.

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Semiconductor

PEDL60851D-01

ML60851D

Hardware Reset

USB Bus Reset

Setup Stage

Condition 1

Data Stage

Condition 2

Status Stage

Condition 2

Condition 3

Condition 1

Condition 1: Reception of a setup packet of control READ transfer or control

WRITE transfer. Condition 2: Reception of a setup packet of control transfer without data. Condition 3: Reception of a token (IN/OUT) of a direction opposite to the data

flow in the data stage.

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Semiconductor

End Point 2 Control Register (EP2CON)

Read address F4h

Write address 74

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset 0 0 1 0 1 0 X 0

After a bus reset 001010X0

Definition 01010

PEDL60851D-01

ML60851D

Configuration Bit (R/W)

Stall Bit (R/W)

Transfer Type 10 = Bulk transfer End Point Address (R)

Transfer Direction (R/W) 0 = Receive, 1 = Transmit

Configuration Bit: The local MCU should write a “1” in this bit during the status stage of control transfer when a

“Set Configuration” request is received from the host computer to make EP2 active. When this bit is “1”, the exchange of data between the host computer and EP2 is enabled. When this bit is “0”, this IC does not respond to any transactions with this EP.

Stall Bit: During EP2 reception, when a data packet is received with a number of bytes more than the

maximum packet size set in the pay load register EP2PLD, the ML60851D automatically sets this bit to “1”. It is also possible for the local MCU to write a “1” in this bit. When this bit is “1”, the stall handshake is automatically returned to the host computer in response to the packet transmitted by the host computer to the end point. In addition, the packet ready status is not

asserted and the

INTR

pin is not asserted.

The EP2 transfer mode is set as a bulk transfer and the end point address is 2h. Therefore, the bits D6 to D2 have fixed values, and other values written in them are ignored.

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Page 41

PEDL60851D-01

(

)

Semiconductor

ML60851D

End Point 2 Data Toggle Register (EP2TGL)

Read address F5h

Write address 75h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition 0000000

Sequence Toggle Bit

Data

R/Rese

Data Sequence Toggle Bit: When initializing an EP after receiving a setup packet, write a “1” in this bit to reset

the toggle bit of the data packet and specify PID of DATA0 (this bit also becomes “0”). Thereafter, the synchronous operation is made automatically based on the data sequence toggling mechanism. The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it will be invalid.

End Point 2 Payload Register (EP2PLD)

Read address F6h

Write address 76h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset0xxxxxxx

After a bus reset 0xxxxxxx

Definition 0 Maximum packet size (R/W)

Maximum Packet Size: The value of wMaxPacketSize of the end point descriptor selected by the

Set_Configuration request from the host computer should be written in this register by the local MCU. The packet size of packets other than short packets is specified in units of a byte. The value can be one of 40h (64 bytes), 20h (32 bytes), 10h (16 bytes), and 08h (8 bytes). This register is used for EP2 reception. During data reception by EP2, if a packet with more number of bytes than that specified here is received, the receive packet ready bit is not asserted, and the stall bit is set during EOP and the stall handshake is returned to the host computer.

Bit D7 is fixed at “0”, and even if a “1” is written, it will be invalid.

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Page 42

Semiconductor

End Point 3 Control Register (EP3CON)

Read address F8h

Write address 78h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset 0 0 1 1 1 1 x 0

After a bus reset 001111x0

Definition 01111

PEDL60851D-01

ML60851D

Configuration Bit (R/W)

Stall Bit (R/W)

Transfer Type (R) 11b = Interrupt Transfer End Point Address

Toggling Condition (R/W) 0 = Normal 1 = Rate feedback mode

Configuration Bit: The local MCU should write a “1” in this bit during the status stage of control transfer

when a “Set Configuration” request is received from the host computer to make EP3 active. When this bit is “1”, the exchange of data between the host computer and EP3 is enabled. When this bit is “0”, this IC does not respond to any transactions with this EP.

Stall Bit: When this bit is “1”, the stall handshake is automatically returned to the host computer

in response to the packet transmitted to the host computer from this end point.

The EP3 transfer mode is set as an interrupt transfer and the end point address is fixed at 3h. Therefore, the bits D6 to D2 have fixed values, and other values written in them are invalid.

Toggling Condition Bit: When this bit is “0”, toggling is performed between DATA0 and DATA1 every time

an ACK is sent from the host computer to EP3. If this bit is set to “1”, the rate feedback mode will be set. In this case, the toggling is performed every time the packet ready bit is asserted.

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Page 43

PEDL60851D-01

Semiconductor

ML60851D

End Point 3 Data Toggle Register (EP3TGL)

Read address F9h

Write address 79h

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset00000000

After a bus reset 00000000

Definition 0000000

Data Sequence Toggle Bit (R/Reset

)

Data Sequence Toggle Bit: When initializing an EP, write a “1” in this bit to reset the toggle bit of the data packet and specify PID of DATA0 (this bit also becomes “0”).

The values of bits D7 to D1 are fixed at “0” and even if a “1” is written in these bits, it will be invalid.

End Point 3 Payload Register (EP3PLD)

Read address FAh

Write address 7Ah

D7 D6 D5 D4 D3 D2 D1 D0

After a hardware reset0xxxxxxx

After a bus reset 0xxxxxxx

Definition 0 7-Bit general purpose register

This register can be used for any purpose. It is possible to retain or refer to the value written in this register without affecting the other operations of the ML60851D. The initial values of bits other than D7 are indeterminate. Bit D7 is fixed at “0” and even if a “1” is written in this bit, it will be invalid.

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Page 44

PEDL60851D-01

ML60851D¡ Semiconductor

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Condition Rating Unit

Power Supply 3 V Power Supply 5 V Input Voltage V Storage Temperature T

CC3 CC5

STG

— –0.3 to +4.6 V — –0.5 to +6.5 V — –0.3 to V

+ 0.3 V

CC5

— –55 to +150 °C

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Condition Range Unit

Power Supply 3 V Power Supply 5 V

CC3 CC5

Operating Temperature Ta — 0 to 70 °C Oscillation Frequency F

OSC

— 3.0 to 3.6 V — 3.0 to 5.5 V

— 48 MHz

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Page 45

ELECTRICAL CHARACTERISTICS

DC Characteristics (1)

Parameter Condition

High-level Input Voltage Low-level Input Voltage High-level Input Voltage Low-level Input Voltage

Schmitt Trigger Input Voltage

High-level Output Voltage Low-level Output Voltage High-level Input Current Low-level Input Current 3-state Output Leakage Current Power Supply Current (Operating) Power Supply Current (Standby)

Symbol

t–

OZH

OZL

CCS

—

—V+0.8—–0.3V

—VV

—V2.01.6—V

(Vt+) – (Vt–)V—0.40.1DV

–100 mAV——V

–4 mA V——2.4

= 100 mAV0.2——

= 4 mA V0.4——

= V

CC5

= 0 V mA—–0.01–1I

= V

CC5

= 0 V mA—–0.01–1I

Note 3 mA—I

Note 4 mAI

Min.

CC3

CC5

2.0

¥ 0.8V

—

– 0.2

Typ.

—

CC5

PEDL60851D-01

= V

= 3.0 to 3.6 V, Tj = 0 to 85°C)

CC3

Unit

mA10.01—I

CC5

CC3

Max.

+ 0.3

+ 0.3—V

¥ 0.2—–0.3V

100

ML60851D¡ Semiconductor

Applicable pin

Note 1

XIN

RESET—V—1.20.8V

D15:D8

AD7:AD0

INTR, DREQ

Note 2

D15:D8

AD7:AD0

, V

CC3

CC5

, V

CC3

CC5

Notes: 1. Applied to D15:D8, AD7:AD0, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL.

2. Applied to XIN, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL.

3. Total currents when V

4. Total currents when V

CC3 CC3

and V and V

are connected.

CC5

are connected.

CC5

The XIN pin is fixed at a high level or a low level in the suspend state. All the output pins are open.

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Page 46

DC Characteristics (2)

Parameter Condition

High-level Input Voltage Low-level Input Voltage

Schmitt Trigger Input Voltage

High-level Output Voltage Low-level Output Voltage High-level Input Current Low-level Input Current 3-state Output Leakage Current Power Supply Current (Operating) Power Supply Current (Standby)

Symbol

t–

OZH

OZL

CC3

CC5

CCS3

CCS5

(Vt+) – (Vt–)V—0.30.2DV

—

—V+0.8—–0.5V

—V2.21.7—V

–100 mAV——V

–8 mA V——3.7

= 100 mAV0.2——

= 8 mA V0.4——

= V

CC5

= 0 V mA—–0.01–10I

= V

CC5

= 0 V mA—–0.01–10I

—mA——I —mA——I

Note 3 mAI Note 3 mAI

Min.

CC5

2.2

– 0.2

CC5

= 4.5 to 5.5 V, V

Typ.

—

—— —— —— ——

PEDL60851D-01

ML60851D¡ Semiconductor

= 3.0 to 3.6 V, Tj = 0 to 85°C)

CC3

Applicable pin

Max.

CC5

50 50

+ 0.5

Unit

INTR, DREQ

mA100.01—I

Note 1

RESET—V—1.40.8V

D15:D8

AD7:AD0

Note 2

D15:D8

AD7:AD0

CC3

CC5

CC3

CC5

Notes: 1. Applied to D15:D8, AD7:AD0, A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. The DC

characteristics (1) applies to XIN.

2. Applied to A7:A0, CS, RD, WR, DACK, ALE, and ADSEL. The DC characteristics (1)

applies to XIN.

3. The XIN pin is fixed at a high level or a low level in the suspend state. All the output pins are open.

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Page 47

DC Characteristics (3) USB Port

Parameter Condition

Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold High-level Output Voltage Low-level Output Voltage Output Leakage Current

Symbol

(D+) – (D–)

Includes V

RL of 15 kW to GND V3.62.8V

RL of 1.5 kW to 3.6 V V0.3V

0 V < VIN < 3.3 V mA+10–10I

PEDL60851D-01

ML60851D¡ Semiconductor

= 3.0 to 3.6 V, Ta = 0 to 70°C)

CC3

Applicable pin

Max.Typ.Min.

0.2

range V2.50.8V

—

Unit

V2.00.8V

D+, D–

AC Characteristics USB Port

Parameter

Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Driver Output Resistance

Data Rate

Symbol

RFM

CRS

DRV

DRATE

Condition

(Notes 1. and 2.)

CL = 50 pF CL = 50 pF ns204t

)

R/tF

Steady State Driver

(Note 3)

Ave. Bit Rate

(12 Mbps ±0.25%)

Notes: 1. 1.5 kW pull-up to 3.3 V on the D+ data line.

2. tR and tF are measured from 10% to 90% of the data signal.

3. Including an external resistance of 22 W ± 5% on the D+ and D– data lines.

= 3.0 to 3.6 V, V

CC3

= 0 V, Ta = 0 to 70°C)

Applicable pin

Max.Typ.Min.

Unit

%111.1190t

V21.3V

D+, D–

W44Z

Mbps12.0311.97t

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Page 48

TIMING DIAGRAM

READ Timing (1) (Address Separate, ADSEL = 0)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

Address Setup Time (RD)t Address Setup Time (CS)t Address (CS) Hold Time t Read Data Delay Time t Read Data Hold Time t Recovery Time t FIFO Access Time t

(RD)

Load 20 pF Load 20 pF

FIFO READ FIFO READ

21 —

63 42

Max.Min.

— 25— 250 — —

Notes: 1. t3 is defined depending upon CS or RD which becomes active last.

2. t2 is defined depending upon CS or RD which becomes active first.

3. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.

4. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.

5. t1 is required for reading FIFO. t1 is defined when either t1(CS) or t1(RD) is satisfied.

A7:A0

Unit

ns ns10 — 5(CS) ns ns ns ns ns

2 1

3 4

AD7:AD0

DATA OUT

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Page 49

READ Timing (2) (Address/Data Multiplex, ADSEL = 1)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

Address (CS) Setup Time t Address (CS) Hold Time t Read Data Delay Time t Read Data Hold Time t Recovery Time t FIFO Access Time t

Max.Min.

Load 20 pF Load 20 pF

FIFO READ FIFO READ

10 —

— 25—

250 63 42

—

Unit

ns ns ns ns ns ns

1 2

Notes: 1. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.

2. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.

AD7:AD0

DATA OUTADDRESS

ALE

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Page 50

WRITE Timing (1) (Address Separate, ADSEL = 0)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

Address Setup Time t Address Setup Time t Address (CS) Hold Time t CS Setup Time t Write Data Setup Time t Write Data Hold Time t Recovery Time t FIFO Access Time t

FIFO WRITE FIFO WRITE

Notes: 1. Either t1(a–w) or t1(a–c) should be satisfied.

2. t1 is defined depending upon CS or WR which becomes active first.

3. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.

4. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.

5. Applied to all registers including CLRFIFO (address: 4Eh).

A7:A0

t1(a–w)

Max.Min.

21 —

—

—30

—2 63 42

—

Unit

ns ns10 — 1(a–c) ns ns10 — ns ns ns ns

1(a–w)

2 3

AD7:AD0

t1(a–c)

DATA IN

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Page 51

WRITE Timing (2) (Address/Data Multiplex, ADSEL = 1)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

Address (CS) Setup Time t Address (CS) Hold Time t Write Data Setup Time t Write Data Hold Time t Recovery Time t FIFO Access Time t

Max.Min.

FIFO WRITE FIFO WRITE

10 —

— —30

—2 63 42

—

Unit

ns ns ns ns ns ns

1 2

Notes: 1. 3-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.

2. 2-clock time of oscillation clock (clock period: 21 ns). It is required for increment of FIFO.

3. Applied to all registers including CLRFIFO (address: 4Eh).

AD7:AD0 ADDRESS DATA IN

ALE

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Page 52

DMA Transfer Timing (1)

ML60851D to Memory (Single Transfer, Single Address Mode)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

DREQ Disable Time t DREQ Enable Time t

DACK Hold Time t Read Data Delay Time t Data Hold Time t

Recovery Time t

Load 20 pF

Load 20 pF Load 20 pF

8-bit DMA

16-bit DMA

—20 —

105

Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.

t1 and t4 are defined depending on DACK or RD which becomes active last.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

4. It is possible to increase t2 by setting the DMA interval register (DMAINTVL).

DREQ

DACK

Max.Min.

Unit

ns 63 —0 25— 25

2ns—63

—3

DOUT

DATA OUT

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Page 53

DMA Transfer Timing (2)

ML60851D to Memory (Single Transfer, Dual Address Mode)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

DREQ Disable Time t DREQ Enable Time t

Read Data Delay Time t Data Hold Time

Recovery Time t

Load 20 pF

Load 20 pF Load 20 pF

8-bit DMA

16-bit DMA

Notes: 1. When in Dual Address mode, the DACK is ignored.

t1 and t3 are defined depending on CS or RD which becomes active last. A7:A0 specifies the FIFO address. Refer to READ Timing (1) for Address Setup Time and Address Hold Time.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

4. It is possible to increase t2 by setting the DMA interval register (DMAINTVL).

A7:A0

DREQ

Max.Min.

—20 —

63 25—

25 —63

105

—3

Unit

ns ns ns ns

4 1

2ns

DOUT

DATA OUT

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Page 54

DMA Transfer Timing (3)

ML60851D to Memory (Demand Transfer, Single Address Mode)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

DREQ Disable Time t DACK Hold Time t Read Data Delay Time t Data Hold Time

Recovery Time t

Load 20 pF

Load 20 pF Load 20 pF

8-bit DMA

16-bit DMA

—

0—

105 3

Max.Min.

25— 25 —63 —

Unit

ns ns ns ns

2ns

Notes: 1. When in Single Address mode, t3 is defined depending on DACK or RD which becomes

active last. A7:A0 and CS are ignored.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

DREQ

DACK

DOUT

Last Packet Read

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Page 55

DMA Transfer Timing (4)

ML60851D to Memory (Demand Transfer, Dual Address Mode)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

DREQ Disable Time t CS Hold Time t

Read Data Delay Time t Data Hold Time

Recovery Time t

Load 20 pF

Load 20 pF Load 20 pF

8-bit DMA

16-bit DMA

Notes: 1. When in Dual Address mode, the DACK is ignored.

t3 is defined depending on CS or RD which becomes active last. A7:A0 specifies the FIFO address. Refer to READ Timing (1) for Address Setup Time and Address Hold Time.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

A7:A0

DREQ

—

105

Max.Min.

20 — 25 25 — —3

Unit

ns ns ns

2ns

DOUT

Last Packet Read

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Page 56

DMA Transfer Timing (5)

Memory to ML60851D (Single Transfer, Single Address Mode)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

DREQ Disable Time t DREQ Enable Time t

FIFO Access Time t DACK Hold Time Write Data Setup Time Write Data Hold Time

Recovery Time

Load 20 pF

FIFO WRITE

8-bit DMA

16-bit DMA

—20

— 42

105

Notes: 1. When in Single Address mode, CS and A7:A0 are ignored.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

4. It is possible to increase t2 by setting the DMA interval register (DMAINTVL).

DREQ

DACK

Max.Min.

Unit

ns 63 —1 —0 — — — —

4 ns ns ns ns ns ns

DIN

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Page 57

DMA Transfer Timing (6)

Memory to ML60851D (Single Transfer, Dual Address Mode)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

DREQ Disable Time t DREQ Enable Time t

FIFO Access Time t Write Data Setup Time Write Data Hold Time

Recovery Time

Load 20 pF

FIFO WRITE

8-bit DMA

16-bit DMA

Notes: 1. When in Dual Address mode, the DACK is ignored.

t1 and t3 are defined depending on CS or WR which becomes active last. Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

4. It is possible to increase t2 by setting the DMA interval register (DMAINTVL).

A7:A0

DREQ

Max.Min.

—20 — 42 30

105

63 — — — — —

Unit

ns ns ns ns ns ns ns

4 1

2 3

DIN

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Page 58

DMA Transfer Timing (7)

Memory to ML60851D (Demand Transfer, Single Address Mode)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

DREQ Disable Time t FIFO Access Time DACK Hold Time Write Data Setup Time t Write Data Hold Time t

Recovery Time t

Load 20 pF

FIFO WRITE

8-bit DMA

16-bit DMA

—20

105

Notes: 1. When in Single Address mode, A7:A0 and CS are ignored.

t2 is defined depending on DACK or WR which becomes active last.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

DREQ

DACK

Max.Min.

Unit

ns —42 — — — — —

2 3

(Note)

DIN

Last Packet Write

(Note) The last Write to reach the byte size (maximum packet size) specified by the EP1 Payload

Register. To terminate DMA transfer before reaching the maximum packet size, set EP1 Packet Ready by writing "1" to the EP1 Endpoint Packet Ready bit.

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Page 59

DMA Transfer Timing (8)

(

Memory to ML60851D (Demand Transfer, Dual Address Mode)

PEDL60851D-01

ML60851D¡ Semiconductor

Parameter Symbol Condition Note

DREQ Disable Time t FIFO Access Time CS Hold Time Write Data Setup Time t Write Data Hold Time t

Recovery Time t

Load 20 pF

FIFO WRITE

8-bit DMA

16-bit DMA

Notes: 1. When in Dual Address mode, the DACK is ignored.

A7:A0 specifies the FIFO address. Refer to WRITE Timing (1) for Address Setup Time and Address Hold Time. t2 is defined depending on CS or WR which becomes active last.

2. 3-clock time of oscillation clock (clock period: 21 ns).

3. 5-clock time of oscillation clock (clock period: 21 ns).

A7:A0

DREQ

Max.Min.

—20 42

105

— — — — — —

Unit

ns ns ns ns ns ns ns

2 3

DIN

Note) Refer to the previous page.

Last Packet Write

(Note)

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Page 60

FUNCTIONAL DESCRIPTIONS

Pin Functional Description

USB Interface

PEDL60851D-01

ML60851D¡ Semiconductor

Signal

D+

Type

I/O

—

—I/OD–

USB data (Plus). This signal and the D– signal are the transmitted or received data from/to USB Bus. The table below shows values and results for these signals.

D+ D– Result

0 0 Single end 0 0 1 Differential "0" 1 0 Differential "1" 1 1 Undefined

USB Data (Minus). This signal and the D+ signal are the transmitted or received data from/to USB Bus. The table above shows values and results for these signals.

DescriptionAssertion

Crystal Oscillator Interface

Signal

XIN For internal oscillation, connect a crystal to XIN and XOUT.

Type

— —OXOUT

For external oscillation, supply an external 48 MHz clock signal to XIN. Set XOUT to be open.

DescriptionAssertion

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Page 61

Application Interface

PEDL60851D-01

ML60851D¡ Semiconductor

Signal

D15:D8

Type

I/O

OINTR

ODREQ

IDACK

IALE

IADSEL

IRESET

—

—I/OAD7:AD0

—IA7:A0

LOWICS

LOWIRD

LOWIWR

LOW

(Note 1)

LOW

(Note 1)

HIGH

(Note 1)

—

LOW

DescriptionAssertion

Upper byte (MSB) of data bus. This data bus is used by applications to access register files and FIFO data.

Lower byte (LSB) of data bus when ADSEL is LOW. Address and lower byte of data bus are multiplexed when ADSEL is HIGH. Address when ADSEL is LOW. This address signal is used by application to access register files and FIFO data. This signal is ignored (all lows or all highs) when ADSEL is HIGH. Chip Select. When this signal is asserted LOW, the ML60851D is selected and ready to read or write data. Read Strobe. When this signal is asserted LOW, the Read instruction is executed. Write Strobe. When this signal is asserted LOW, the Write instruction is executed. Interrupt Request. When this signal is asserted, the ML60851D makes an interrupt request to the application.

DMA Request. This signal requests the Endpoint FIFO to make a DMA transfer.

DMA Acknowledge Signal. This signal, when asserted, enables accessing FIFOs, without address bus setting. When ADSEL is HIGH, the address and CS on AD7:AD0 is latched at the trailing edge of this signal. This signal is ignored when ADSEL is LOW. When ADSEL is LOW, the address is input on A7:A0 and data is input on D15:D8 and AD7:AD0. When ADSEL is HIGH, the lower bytes (LSB) of address and data are multiplexed on AD7:AD0. System Reset. When this signal is asserted LOW, the ML60851D is reset. When the ML60851D is powered on, this signal must be asserted for 1 ms or more.

Note: 1. Initial value immediately after resetting. Its assertion can be changed by programming.

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Page 62

PEDL60851D-01

ML60851D¡ Semiconductor

Functional Description

The ML60851D USB device controller contains the Protocol Engine, DPLL, Timer, Status/Control, FIFO Control, Application Interface, and Remote Wakeup blocks.

• Protocol Engine The Protocol Engine handles the USB communication protocol. It performs control of packet transmission/reception, generation/detection of synchronous patterns, CRC generation/checking, NRZI data modulation, bit stuffing, and packet ID (PID) generation/checking.

• DPLL (Digital Phase Locked Loop) The DPLL extracts clock and data from the USB differential received data (D+ and D–).

• Timer The Timer block monitors idle time on the USB bus.

• Status/Control The Status Control block moniors the transaction status and transmits control events to the application through an interrupt request.

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Page 63

PEDL60851D-01

ML60851D¡ Semiconductor

• FIFO Control The FIFO Control block controls all FIFO operations for transmitting and receiving USB packets. The FIFO configuration is described below.

Endpoint FIFO/8-Byte Setup Register Configuration

Endpoint Address 0

Endpoint Address 1

Endpoint Address 2

8-Byte Setup Register

8-Byte

FIFO Rx

8-Byte

FIFO Tx

64-Byte

FIFO

64-Byte

FIFO

64-Byte

FIFO

For Control Transfer

Setup Ready

Packet Ready

For Bulk Transfer

Packet Ready DMA Request

Packet Ready

EP0 Receive FIFO

EP0 Transmit FIFO

EP1 FIFO (128 bytes) (Selectable for transmitter or receiver)

EP2 FIFO (64 bytes) (Selectable for transmitter or receiver)

Endpoint Address 3

Endpoint address Program sizeFIFO type

Reception Transmission Reception/Transmission

8-Byte

FIFO

Packet Ready

EP3 FIFO (8 bytes)

Function

0 0 1

8 Bytes 8 Bytes 64 Bytes (2 levels)

Transfer control Transfer control

Bulk-In and bulk-Out Reception/Transmission 2 64 Bytes Bulk-Out and bulk-In Transmission

8 Bytes

Interrupt

Every FIFO has a flag that indicates a full or empty FIFO and the capability of re-transmitting and re-receiving data. Endpoint addresses 1 and 2 can be used for either of reception and transmission by writing the register. The FIFO at endpoint address 1 can be used for DMA transfer.

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Page 64

PEDL60851D-01

ML60851D¡ Semiconductor

• Remote Wakeup This functional block supports the remote wakeup function.

• USB Transfers The ML60851D supports the two transfer types (Control Transfer and Bulk Transfer) of four transfer types (Control, Isochronous, Interrupt, and Bulk) defined by the USB Specifications.

- The Control Transfer is required for transfer of configuration, commands, and status information

between the host and devices.

- The Bulk Transfer enables transfer of a large amount of data when the bus bandwidth is enough.

• USB Transceiver The ML60851D contains an Oki's USB transceiver which converts internal unidirectional signals into USB-compatible signals. This enables the designer's application module to interface to the physical layer of the USB.

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Page 65

FEDL60851D-01

Semiconductor

ML60851D

•••• Interrupts

The ML60851D requests interrupts to the local MCU, etc., by asserting the -INTR pin. The interrupt causes are the following:

(a) Setup ready for the 8-byte setup data (b) EP0 receive packet ready (c) EP0 transmit packet ready (d) EP1 transmit/receive packet ready (e) EP2 transmit/receive packet ready (f) EP3 transmit packet ready (g) USB Bus reset (h) Suspend

Although there is only one

INTR

pin, the local MCU can identify the contents of the interrupt by reading out the interrupt status register. These interrupts can also be masked dynamically by making individual settings in the interrupt enable register. The causes of the interrupts, their setting and resetting conditions, and the responses to them are described below. The functions of the setup ready bit and the packet ready bit can, in some situations, be different from those described here because of some special automatic operations done by the ML60851D. Please see the descriptions of the registers EP0STAT and PKTRDY for more details of such functions.

(1) Setup ready interrupt

Operation Source of operation Description (conditions, responses, etc.)

Setup ready

interrupt generation

End of setup ready interrupt Local MCU (firmware)

ML60851D

The setup ready bit (D0 of EP0STAT) is asserted when the 8-byte setup control data is received normally and has been stored in the set of setup registers.

An interrupt is generated at this time if D0 of INTENBL has been asserted.

The firmware can now read the set of setup registers.

→

After making the firmware read the 8-byte setup data, write a “1” in bit D0 of EP0 status register (EP0STAT). This causes the interrupt to be de-asserted.

The interrupt will not be de-asserted If a new 8-byte setup data is received during this period. In this case, discard the setup data that was being read at that time and read the new 8-byte setup data.

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(2) EP0 Receive packet ready interrupt

This is used mainly during the reception of a data packet in a control write transfer.

Operation Source of operation Description (conditions, responses, etc.)

EP0 Receive packet ready

interrupt generation

End of EP0 receive

packet ready interrupt

ML60851D The EP0 receive packet ready bit (D0 of PKTRDY) is

asserted during a control write transfer when the processing has changed from the setup stage to the data stage, and the ML60851D has detected EOP of the data packet and has stored the data without error in the EP0 receive FIFO. The end of a packet is recognized when an EOP has arrived in the cases of both full packets and short packets.

An interrupt is generated at this time, if the EP0 receive packet ready interrupt enable bit (D3 of INTENBL) has been asserted.

(EOP: End of packet)

Local MCU (firmware) In the case of EP0 reception, after the number of bytes of

the EP0 receive FIFO data indicated by the EP0 receive byte count register (EP0RXCNT) has been read, write a '1' in the EP0 receive packet ready bit (bit D0 of PKYRDY). (This status is reset when a '1' is written in this bit.)

FEDL60851D-01

ML60851D

Note: A short packet is a packet with a number of bytes less than the maximum packet size.

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(3) EP0 Transmit packet ready interrupt

This is used mainly during the transmission of a data packet in a control read transfer.

Operation Source of operation Description (conditions, responses, etc.)

EP0 Transmit packet ready

interrupt generation

End of EP0 transmit

packet ready interrupt

ML60851D The EP0 transmit packet ready bit (D4 of PKTRDY) is de-

asserted during a control read transfer when the processing has changed from the setup stage to the data stage, and it is possible to write the transmit data to the FIFO.

At this time, an interrupt is generated if the EP0 transmit packet ready interrupt enable bit (bit D4 of INTENBL) has been asserted.

For the second and subsequent packets, in addition to this condition, before the interrupt is generated, it is necessary for an ACK response to come from the host for the packet that has just been sent.

Local MCU (firmware) In the case of EP0 transmission, after the one packet of the

EP0 transmit data has been written in EP0TXFIFO, write a “1” into the EP0 transmit packet ready bit (bit D4 of PKTRDY). This puts the ML60851D in a state in which it can transmit the data (that is, it can transmit the data packet when an IN token arrives), and the at the same time.

Even when the number of bytes in the write data is less than the maximum packet size, it is possible to transmit the data by writing a “1” into the transmit packet ready status bit. This makes it possible to transmit a short packet.

FEDL60851D-01

pin is de-asserted

INTR

ML60851D

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ML60851D

(4) Receive packet ready interrupts (EP1, EP2)

These interrupts are generated when the respective EP has received an appropriate data packet from the USB bus and the local MCU can read that data.

Operation Source of operation Description (conditions, responses, etc.)

Receive packet ready

interrupt generation

End of receive packet ready interrupt

ML60851D The receive packet ready bit of the corresponding EP

status register (EPnSTAT) is asserted during data reception when the EOP of the data packet has been received and the data has been stored without error in the corresponding FIFO. The end of a packet is recognized when an EOP has arrived in the cases of both full packets and short packets.

An interrupt is generated at this time, if the corresponding receive packet ready interrupt enable bit has been asserted.

(EOP: End of packet)

Local MCU (firmware) After the number of bytes in the receive FIFO data

(EPnFIFO) indicated by the corresponding receive byte count register (EPnRXCNT) has been read, write a “1” into the receive packet ready bit of the corresponding EP status register (EPnSTAT). (This status is reset when a '1' is written in this bit.)

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FEDL60851D-01

Semiconductor

ML60851D

(5) Transmit packet ready interrupts (EP1, EP2, EP3)

These interrupts are generated when it is possible for the local MCU to write the data packet to be sent to the USB bus from the corresponding EP.

Operation Source of operation Description (conditions, responses, etc.)

Transmit packet ready

interrupt generation

End of transmit packet ready interrupt

ML60851D (1) In the case of bulk transfer and interrupt transfer

When the respective EP has been set for transmission, the transmit packet ready bit of the corresponding EP is de-asserted when it is possible to write the transmit data into the FIFO.

At this time, an interrupt is generated if the corresponding EP transmit packet ready interrupt enable bit (INTENBL1) has been asserted.

Local MCU (firmware) (1) In the case of bulk transfer and interrupt transfer

After the one packet of the corresponding EP transmit data has been written in EPnTXFIFO, write a “1” into the corresponding transmit packet ready bit. This puts the ML60851D in a state in which it can transmit the data and the

Even when the number of bytes in the write data is less than the maximum packet size, it is possible to end the pocket transmission by writing a “1” into the transmit packet ready status bit.

pin is de-asserted at the same time.

INTR

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(6) USB Bus reset interrupt

Operation Source of operation Description (conditions, responses, etc.)

USB Bus reset interrupt

generation

End of USB bus reset

interrupt

(7) Suspend state interrupt

Operation Source of operation Description (conditions, responses, etc.)

Suspend state

interrupt generation

End of suspend state

interrupt

FEDL60851D-01

ML60851D

Local MCU (firmware) Write a “1” into the device status register (bit D5 of

ML60851D

Local MCU (firmware) When receive EP0.

The ML60851D automatically detects the condition when the SE0 state continues for 2.5µs or longer at the D+ and D- pins.

Carry this out by firmware processing for bus reset.

→

DVCSTAT).

When the idle condition persists for 3ms or more at the D+ and D- pins.

Perform farmware processing to the bus reset.

→

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FEDL60851D-01

Semiconductor

ML60851D

•••• DMA (Direct Memory Access)

It is possible to carry out 8-bit wide or 16-bit wide DMA transfer for the bulk transfer of EP1. The data bus used is the following:

During 8-bit transfer: AD7 to AD0

During 16-bit transfer: D15 toD8, AD7 to AD0 Demand transfer and single transfer are supported. The settings of the DMA transfer mode and parameters are done using the DMA control register and the DMA interval register described later in this manual.

In the demand transfer mode, the possible. The

DREQ

pin is de-asserted when the transfer of all the data of the receive packets is completed by the

DREQ

pin is asserted when the reading or writing of a data packet becomes

external DMA controller. Therefore, other devices cannot access the local bus during DMA transfer. On the other hand, in the single transfer mode, the

DREQ

pin is de-asserted at the end of transfer of the number of

bytes (or words) of one transfer, and the other devices can access the local bus during this period.

•••• Power-down

By setting the system control register (SYSCON) to value A0h, the oscillator circuit of the ML60851D can be stopped and the ML60851D enters the power-down state. The ML60851D cannot communicate with the USB bus after the internal oscillations are stopped. In order to communicate with the USB bus after the termination of the power-down state, the internal oscillations should be restarted and the initial settings should be done. Therefore, the ML60851D should not be powered down during normal operation.

Note 1: Assertion of the

RESET

signal causes the internal oscillations to be restarted.

Note 2: In the power-down state, reads and writes to the registers are possible but reads or writes to

FIFO are not possible.

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ML60851D

•••• Control transfer

(a) Setup stage

The setup token and 8 bytes of setup data are transmitted from the host. The ML60851D decodes the setup token, and automatically stores the 8 bytes of setup data in the setup register. When this is completed normally, the ML60851D returns ACK to the host. The 8-byte setup data is the standard request code defined in Section 9.3 of the USB Standards, or a code of the requests unique to each device class, etc. The request is decoded on the local MCU side.

(b) Data stage

If the request specified by the 8-byte setup data is also accompanied by transfer of parameter data from the host to the device, the transfer is a control write transfer, and the OUT token and the data packet are transmitted from the host. When these are received normally, the ML60851D stores the parameter data in the EP0 receive FIFO and returns ACK to the host. If the request is accompanied by transfer of parameter data from the device to the host, the transfer is a control read transfer, and when the host sends the IN token, the ML60851D sends the parameter data that was already stored beforehand in the EP0 transmit FIFO by the local MCU. When the host receives this normally, it returns an ACK to the ML60851D. On the other hand, in the case of requests that do not contain any parameter data that need to be transmitted or received, this data stage will not be present and the processing proceeds directly to the status stage from the setup stage.

The status stage is a stage intended for reporting the status of the result of executing a request from the device to the host. During a control write transfer or a control transfer without data, the IN token is sent by the host, and the ML60851D returns a response to it. During a control read transfer, the OUT token and data of zero length are sent by the host, and the ML60851D returns a response to it.

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FEDL60851D-01

Semiconductor

ML60851D

•••• Data packet transmission and reception procedure during bulk transfer and interrupt transfer modes

The ML60851D is normally used on the peripheral device side. In this method of use, the ML60851D is connected on one side to the host via the USB bus and is connected on the other side via a parallel interface to the local microcontroller (local MCU) inside the peripheral device. The transfer of data is the major function in all types of transfermodes other than the control transfermode. When carrying out transfer of data packets between the ML60851D and the host, the following packet communication is carried out via the USB bus for the data transfer of each packet.

(a) Token packet transfer (IN token or OUT token) from the host to the ML60851D. (b) Data packet transfer in the desired direction (from the host to the device or from the device to the host). (c) Transfer of handshake packet in a direction opposite to that of the data packet.

When packet transfer is completed normally, an ACK packet is returned in step (c) and the operation proceeds to the next packet transfer.

The ML60851D requests the local MCU to transmit or receive a packet of data by asserting the

INTR

pin. The interrupt cause will be “packet ready”. The transmit packet ready interrupt is one that requests that the packet of data to be transmitted be written in the transmit FIFO, and the receive packet ready interrupt is one that requests the local MCU to read out the data that has been received and stored in the receive FIFO. The above procedures of transferring one packet of data are explained below for transmission and reception separately.

1) During transmission The local MCU writes one packet of data that has to be transmitted in the transmit FIFO of the corresponding EP in the ML60851D, and sets the transmit packet ready bit of the corresponding EP status register of the ML60851D. When the host transmits the IN token packet to the ML60851D specifying the communication method, etc., the ML60851D transmits to the host the data packet stored in the above transmit FIFO. When the host receives one data packet normally, it returns the ACK packet to the ML60851D. Consequently, the ML60851D resets the transmit packet ready status, thereby completing the transfer of one data packet over the USB bus. When the transmit packet ready status is reset, the ML60851D gives a request to the local MCU in terms of a transmit packet ready interrupt thereby prompting the local MCU to write the next packet of data to be transmitted.

2) During reception The host sends to the ML60851D an OUT token followed by a data packet. The ML60851D stores the received data packet in the receive FIFO of the corresponding EP. When it is confirmed that all the data packets have been accumulated and that there is no error, the ML60851D returns an ACK packet to the host. At the same time, the receive packet ready bit of the corresponding EP status register will also be set and a request is sent to the local MCU in terms of an interrupt. Upon receiving this interrupt, the local MCU reads out the received data from the ML60851D and resets the receive packet ready bit.

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FEDL60851D-01

)

Semiconductor

ML60851D

•••• Packets and packet sizes

The ML60851D packs the transmit data into packets and unpacks (restores to the original form) the received data. The packed data that is recognized by the software client is a set of data consisting of one or more packets, and this is called an I/O request (IRP). Among the several packets in an IRP, all the packets other than the last packet are transferred with the maximum packet size. Only the last packet can be transferred as a "short packet", that is, a packet whose size is less than the maximum packet size.

I/O Request Packet (IRP

Packet

n-1

Packet

1 Packet

M Bytes

Maximum packet size

The ML60851D has payload registers corresponding to each end point, and it is possible to set the maximum packet size for each end point in these registers. The maximum packet size should be within the capacity of the corresponding FIFO, and can be set as follows:

(1) EP0 Receive packet size can be 8 bytes or less; (2) EP0 Transmit packet size can be 8 bytes or less; (3) EP1 Transmit/receive packet size can be 64 bytes or less; (4) EP2 Transmit/receive packet size can be 64 bytes or less; (5) EP3 Transmit packet size can be 8 bytes or less;

On the USB bus, the separation between successive packets is distinguished by appending a special signal condition called EOP (End of Packet) at the end of each packet. The appending of EOP during transmission and the detection and removal of EOP during reception are carried out by the ML60851D automatically.

(1) At the time of transmission, the packet is deemed to have ended when the local MCU has completed writing

the required number of bytes of data in the transmit FIFO and has then asserted the transmit ready status bit. (The actual addition of EOP is executed at the time of transmitting the data over the USB bus after waiting for the IN token from the host.) The packet will be a short packet if the transmit packet ready status bit is asserted after writing data with less number of bytes than the maximum packet size. In particular, by asserting the transmit packet ready status bit without writing any data, it is possible to form a null packet whose data length is zero.

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Semiconductor

ML60851D

(2) At the time of reception, when an EOP is detected in the received data string, the ML60851D recognizes it as

the end of the received packet and asserts the receive packet ready status bit. The number of bytes in the received packet is counted automatically in the receive byte count register (Note 1) corresponding to that end point.

Note 1: Receive byte count registers

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ML60851D

•••• Operation of 2-layer structure FIFO during bulk transfer

The FIFOs of EP1 have a 64 bytes x 2-layer structure. As a consequence, these FIFOs can temporarily store a maximum of 128 bytes of bulk transfer data.

(1) 2-Layer reception operation (O indicates the assert condition and X indicates de-assert condition)

In the case of 1→2→3→4→5a→6

In the case of 1→2→3→4→5b→6

1 Start storing data in layer A of reception x x x x

2 Data of one packet has been stored. x

Start reception and storing of data in

layer B.

4 Local MCU starts reading layer A. x

When the storing of packet in layer B is completed following the completion of

reading layer A.

When the reading of packet in layer A is completed following the completion of

storing data in layer B.

From 5a: Layer A has become empty.

From 5b: Layer B has become full.

7 Starting reading layer B also. x

•

When one packet of receive data is stored in layer A of the FIFO and EOP is received, the ML60851D asserts the packet ready bit of EP1 and also asserts the

Layer A

64 bytes

INTR

Layer B

64 bytes

pin. This makes it possible for the local MCU to read the

Layer A

PKT

RDY

Layer B

PKT

RDY

xxxx

EP1

receive

PKT

RDY

receive data.

•

Subsequently, data can be received from the host, and the ML60851D switches the FIFO for storing to layer B.

•

When one packet of data described above has been read from layer A of the FIFO, make the local MCU reset the receive packet ready status of EP1 (by writing a “1” into bit D1 of PKTRDY).

•

At the time the EP1 receive packet ready status is reset, if the reception of layer B has not been completed, the ML60851D resets the EP1 receive packet ready status and de-asserts the

•

However, if the reception of layer B has been completed a the time the EP1 receive packet ready status is reset,

INTR

pin.

the ML60851D rejects the request from the local MCU to reset the EP1 receive packet ready status, and continues to maintain the EP1 receive packet ready status and the asserted condition of the

INTR

pin.

INTR

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FEDL60851D-01

Semiconductor

ML60851D

(2) 2-Layer transmission operation (O indicates the assert condition and X indicates de-assert condition)

In the case of 1→2→3→4→5a→6

In the case of 1→2→3→4→5b→6

1 Layer A and layer B are both empty. x x x

2 The local MCU starts writing into layer A. x x x

3 Writing of one packet is completed. x x

The data of layer A is transmitted and

the next packet is written in layer B.

When layer A has become empty after

the writing in layer B is completed.

When the writing in layer B has been completed after layer A has become

empty.

From 5a: Layer A has become empty.

From 5b: Layer B has become full.

7 Transmission of layer B is also started. x x

•

If the EP1 transmit packet ready interrupt enable bit has been asserted, the transmit FIFO is empty, and EP1

Layer A

64 bytes

Layer B

64 bytes

Layer A

PKT

RDY

Layer B

PKT

RDY

xx x

EP1

transmit

PKT

RDY

transmit packet ready bit is de-asserted, the EP1 transmit packet ready interrupt is asserted. This makes it possible to write the transmit data into the EP1 transmit FIFO.

•

When the data of one packet is written in layer A FIFO, make the local MCU set the transmit packet ready status. By setting the transmit packet ready status, it becomes possible to transmit data to the host. At this time, since

layer B is still empty, the

INTR

pin maintains the asserted condition, thereby indicating that the next packet data can be written. In this case, although bit D5 of PKTRDY remains in the “0” condition, the ML60851D recognizes that transmission is possible from layer A and starts transmission when an IN token is received from the host.

•

It is possible for the local MCU to write the next packet of transmit data in the layer B FIFO while the data in layer A is being transmitted over the USB bus.

•

When the writing of the data to be transmitted in layer B has been completed, the local MCU sets the transmit packet ready bit, and the

INTR

pin becomes de-asserted at this time if the transmission of layer A data has not been completed (that is, the ACK message is received from the host and the transmit packet ready bit is reset). The local MCU cannot yet write the subsequent packet.)

•

If the layer A becomes empty before layer B goes into the transmit enable condition and transmission is carried out normally, the ACK response is received from the host. The

INTR

pin remains asserted, and the local MCU

can write data into layer A FIFO after writing into layer B FIFO.

•

The transmission of data in layer A is continued from the state 4a, and when layer A becomes empty and the transmission is completed normally, the ACK response is received from the host, whereupon the ML60851D

asserts the

INTR

pin thereby prompting the local MCU to write data into layer A.

INTR

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ML60851D

•••• Error processing and retry operation

1) Error processing during transmission When an error such as a CRC error is detected in the data transmitted by the ML60851D, the host will not send the ACK packet, and hence the ML60851D does not reset the transmit packet ready status, but waits while retaining the current packet of data. The current packet of data is transmitted again when the next IN token is received from the host.

2) Error processing during reception When an error is detected in the data received over the USB bus, the ML60851D does not assert the interrupt signal to the local MCU and will also not send any message to the host (leading to a timeout condition). When the timeout condition is generated, the host recognizes that an error has occurred, and can take measures such as re-transmitting the data, etc. In addition, since no interrupt request is generated, the local MCU will not read the erroneous data.

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EXAMPLE OF OSCILLATOR CIRCUIT

• Oscillation Circuit Example 1

ML60851D

PEDL60851D-01

ML60851D¡ Semiconductor

XIN

XOUT

Crystal: HC-49U (KINSEKI, LTD) C2 = 5 pF C3 = 1000 pF Rf = 1 MW L1 = 2.2 mH

Note: The example shown above is not guaranteed for circuit operation.

• Oscillation Circuit Example 2

ML60851D

CSTCW4800MX41xxx

XIN

XOUT

Ceramic oscillator: CSTCM4800MXxxx (MURATA MFG.)

(C-built-in type)

Note: The example shown above is not guaranteed for circuit operation.

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PACKAGE DIMENSIONS

QFP44-P-910-0.80-2K

Mirror finish

PEDL60851D-01

ML60851D¡ Semiconductor

(Unit : mm)

Package material Lead frame material Pin treatment Solder plate thickness

Package weight (g)

Epoxy resin 42 alloy Solder plating 5 mm or more

0.41 TYP.

Notes for Mounting the Surface Mount Type Package

The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).

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TQFP44-P-1010-0.80-K

Mirror finish

PEDL60851D-01

ML60851D¡ Semiconductor

(Unit : mm)

Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)

Epoxy resin 42 alloy Solder plating 5 mm or more

0.28 TYP.

Notes for Mounting the Surface Mount Type Package

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ML60851D

NOTICE

1. The information contained herein can change without notice owing to product and/or technical improvements.

Before using the product, please make sure that the information being referred to is up-to-date.

2. The outline of action and examples for application circuits described herein have been chosen as an

explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs.

3. When designing your product, please use our product below the specified maximum ratings and within the

specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature.

4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation

resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range.

5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is

granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof.

6. The products listed in this document are intended for use in general electronics equipment for commercial

applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems.

7. Certain products in this document may need government approval before they can be exported to particular

countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these.

8. No part of the contents contained herein may be reprinted or reproduced without our prior permission.

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