Datasheet ML4950CS, ML4950ES Datasheet (Micro Linear Corporation)

July 2000

FEATURING

Extended Commercial Temperature Range

-20˚C to 70˚C

for Portable Handheld Equipment

ML4950*

Adjustable Output, Low Current

Single Cell Boost Regulator with Detect

GENERAL DESCRIPTION

The ML4950 is a low power boost regulator designed for

FEATURES

■ Guaranteed full load start-up and operation at 1V input

low voltage DC to DC conversion in single cell battery
powered systems. The maximum switching frequency can
exceed 100kHz, allowing the use of small, low cost

■ Pulse Frequency Modulation (PFM) and internal

synchronous rectification for high efficiency

inductors.

■ Minimum external components

The combination of integrated synchronous rectification,
variable frequency operation, and low supply current

■ Low ON resistance internal switching FETs

make the ML4950 ideal for single cell applications. The
ML4950 is capable of start-up with input voltages as low

■ Micropower operation

as 1V, and the output voltage can be set anywhere
between 2V and 3V.

An integrated synchronous rectifier eliminates the need for

■ Adjustable output voltage (2V to 3V)

■ Low battery detect

an external Schottky diode and provides a lower forward
voltage drop, resulting in higher conversion efficiency. In
addition, low quiescent battery current and variable
frequency operation result in high efficiency even at light
loads. The ML4950 requires a minimum number of
external components and is capable of achieving
conversion efficiencies in excess of 90%.

The circuit also contains a RESET output which goes low
when the IC can no longer function due to low input
voltage, or when the DETECT input drops below 200mV. *Some Packages Are Obsolete

BLOCK DIAGRAM

DETECT

4

V

IN

1

7

RESET

+

COMP

REF

–

SRQ

START-UP

Q

REFERENCE

GND

2

5µs

ONE SHOT

V

REF

V

6

V

L

V

OUT

+
–

–
+

V

REF

5

PWR

GND

8

SENSE

3

1

ML4950

PIN CONFIGURATION

PIN DESCRIPTION

8-Pin SOIC (S08)

V

IN

GND

SENSE

DETECT

ML4950

1

2

3

4

TOP VIEW

8

7

6

5

PWR GND

RESET

V

L

V

OUT

PIN NAME FUNCTION

1V

IN

Battery input voltage

2 GND Analog signal ground

3 SENSE Programming pin for setting the output

voltage

4 DETECT Pulling this pin below 200mV causes

the RESET pin to go low

PIN NAME FUNCTION

5V

6V

OUT

L

Boost regulator output

Boost inductor connection

7 RESET Output goes low when regulation

cannot be achieved, or when DETECT
goes below 200mV

8 PWR GND Return for the NMOS output transistor

2

ML4950

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

V

............................................................................................... 7V

OUT

Voltage on Any Other Pin ..... GND - 0.3V to V

Peak Switch Current (I
Average Switch Current (I

)..........................................1A

PEAK

) .............................. 250mA

AVG

OUT

+ 0.3V

OPERATING CONDITIONS

Temperature Range

ML4950CS-X.............................................. 0ºC to 70ºC

ML4950ES-X ........................................... -20ºC to 70ºC

VIN Operating Range

ML4950CS-X................................. 1.0V to V

ML4950ES-X ................................. 1.1V to V

V

Operating Range .......................................2V to 3V

OUT

OUT
OUT

- 0.2V

- 0.2V

Junction Temperature .............................................. 150ºC

Storage Temperature Range...................... –65ºC to 150ºC

Lead Temperature (Soldering, 10 sec) ...................... 150ºC

Thermal Resistance (qJA) .................................... 160ºC/W

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, VIN = Operating Voltage Range, TA = Operating Temperature Range (Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

SUPPLY

I

I

OUT(Q)VOUT

I

L(Q)

PFM REGULATOR

t

ON

V

SENSE

RESET

Note 1:

VIN Current VIN = V

IN

VL Quiescent Current 1µA

Pulse Width 4.5 5 5.5 µs

SENSE Compator Threshold Voltage 196 201 208 mV

Load Regulation See Figure 1 2.425 2.5 2.575 V

Undervoltage Lockout Threshold 0.85 0.95 V

COMPARATOR

DETECT Threshold Voltage 194 200 206 mV

DETECT Bias Current -100 100 nA

RESET Output High Voltage IOH = -100µA V

RESET Output Low Voltage IOL = 100µA 0.2 V

Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

- 0.2V 50 60 µA

OUT

Quiescent Current 8 10 µA

VIN = 1.2V, I

OUT

£ 25mA

-0.2 V

OUT

3

ML4950

27µH

(Sumida CD75)

ML4950

V

IN

100µF

SRQ

START-UP

V

PWR GND

IN

GND

SENSE

DETECT

RESET

V

V

OUT

L

464kΩ

0.1%

40.2kΩ

0.1%

Figure 1. Application Test Circuit.

L1

V

IN

6

V

L

Q2

Q1

5µs

ONE SHOT

A2

I

OUT

V

OUT

100µF

V

OUT

+
–

5

C1

+

V

–

OUT

Q

SENSE

A1

–
+

V

REF

3

R1

R2

Figure 2. PFM Regulator Block Diagram.

INDUCTOR

CURRENT

Q(ONE SHOT)

Q1 ON Q1 ON

Q1 & Q2 OFF

Q2
ON

Q2

ON

Figure 3. PFM Inductor Current Waveforms and Timing.

4

ML4950

FUNCTIONAL DESCRIPTION

The ML4950 combines Pulse Frequency Modulation (PFM)
and synchronous rectification to create a boost converter
that is both highly efficient and simple to use. A PFM
regulator charges a single inductor for a fixed period of
time and then completely discharges before another cycle
begins, simplifying the design by eliminating the need for
conventional current limiting circuitry. Synchronous
rectification is accomplished by replacing an external
Schottky diode with an on-chip PMOS device, reducing
switching losses and external component count.

REGULATOR OPERATION

A block diagram of the boost converter is shown in Figure

2. The circuit remains idle when V
desired output voltage, drawing 50µA from VIN, and 8µA
from V
When V

through the feedback resistors R1 and R2.

OUT

drops below the desired output level, the

OUT

output of amplifier A1 goes high, signaling the regulator to
deliver charge to the output. Since the output of amplifier
A2 is normally high, the flip-flop captures the A1 set signal
and creates a pulse at the gate of the NMOS transistor Q1.
The NMOS transistor will charge the inductor L1 for 5µs,
resulting in a peak current given by:

I

LPEAK

()

tV



ON IN IN

=

L

1

sV

5

m

=



L

1

For reliable operation, L1 should be chosen so that I
does not exceed 1A.

When the one-shot times out, the NMOS transistor
releases the VL pin, allowing the inductor to fly-back and
momentarily charge the output through the body diode of
PMOS transistor Q2. But as the voltage across the PMOS
transistor changes polarity, its gate will be driven low by
the current sense amplifier A2, causing Q2 to short out its
body diode. The inductor then discharges into the load
through Q2. The output of A2 also serves to reset the flip­flop and one-shot in preparation for the next charging
cycle. A2 releases the gate of Q2 when its current falls to
zero. If V

is still low, the flip-flop will immediately

OUT

initiate another pulse. The output capacitor (C1) filters the
inductor current, limiting output voltage ripple. Inductor
current and one-shot waveforms are shown in Figure 3.

RESET

COMPARATOR

An additional comparator is provided to detect low VIN or
any other error condition that is important to the user. The
inverting input of the comparator is internally connected
to V

, while the non-inverting input is provided

REF

externally at the DETECT pin. The output of the
comparator is the RESET pin, which swings from V
GND when an error is detected.

is at or above the

OUT

L(PEAK)

OUT

(1)

to

DESIGN CONSIDERATIONS

INDUCTOR

Selecting the proper inductor for a specific application
usually involves a trade-off between efficiency and
maximum output current. Choosing too high a value will
keep the regulator from delivering the required output
current under worst case conditions. Choosing too low a
value causes efficiency to suffer. It is necessary to know
the maximum required output current and the input
voltage range to select the proper inductor value. The
maximum inductor value can be estimated using the
following formula:

L

Vt

=

MAX

where h is the efficiency, typically between 0.8 and 0.9.
Note that this is the value of inductance that just barely
delivers the required output current under worst case
conditions. A lower value may be required to cover
inductor tolerance, the effect of lower peak inductor
currents caused by resistive losses, and minimum dead
time between pulses.

Another method of determining the appropriate inductor
value is to make an estimate based on the typical
performance curves given in Figures 4 and 5. Figure 4
shows maximum output current as a function of input
voltage for several inductor values. These are typical
performance curves and leave no margin for inductance
and ON-time variations. To accommodate worst case
conditions, it is necessary to derate these curves by at least
10% in addition to inductor tolerance.

For example, a single cell to 2.5 V application requires
20mA of output current while using an inductor with 15%
tolerance. The output current should be derated by 25% to
25mA to cover the combined inductor and ON-time
tolerances. Assuming that 1V is the end of life voltage of a
single cell input, Figure 4 shows that with the ML4950
delivers 25mA at 2.5V with a 27µH inductor.

Figure 5 shows efficiency under the conditions used to
create Figure 4. It can be seen that efficiency is mostly
independent of input voltage and is closely related to
inductor value. This illustrates the need to keep the
inductor value as high as possible to attain peak system
efficiency. As the inductor value goes down to 18µH, the
efficiency drops to between 75% and 80%. With 68µH,
the efficiency exceeds 90% and there is little room for
improvement. At values greater than 100µH, the operation
of the synchronous rectifier becomes unreliable because
the inductor current is so small that it is difficult for the
control circuitry to detect. The data used to generate
Figures 4 and 5 is provided in Table 1.

2

IN MIN ON MIN

2



() ()

VI



OUT OUT MAX

h

()

(2)

5

ML4950

DESIGN CONSIDERATIONS

After the appropriate inductor value is chosen, it is
necessary to find the minimum inductor current rating
required. Peak inductor current is determined from the
following formula:

tV

I

LPEAK

()

In the single cell application previously described, a
maximum input voltage of 1.6V would give a peak current
of 383mA. When comparing various inductors, it is
important to keep in mind that suppliers use different
criteria to determine their ratings. Many use a conservative
current level, where inductance has dropped to 90% of its
normal level. In any case, it is a good idea to try inductors
of various current ratings with the ML4950 to determine
which inductor is the best choice. Check efficiency and
maximum output current, and if a current probe is
available, look at the inductor current to see if it looks like
the waveform shown in Figure 3. For additional
information, see Application Note 29.

Suitable inductors can be purchased from the following
suppliers:

ON MAX IN MAX

=



() ()

L

MIN

(Continued)

(3)

Capacitor Equivalent Series Resistance (ESR) and
Equivalent Series Inductance (ESL), also contribute to the
output ripple due to the inductor discharge current
waveform. Just after the NMOS transistor turns off, the
output current ramps quickly to match the peak inductor
current. This fast change in current through the output
capacitor’s ESL causes a high frequency (5ns) spike that
can be over 1V in magnitude. After the ESL spike settles,
the output voltage still has a ripple component equal to
the inductor discharge current times the ESR. This
component will have a sawtooth shape and a peak value
equal to the peak inductor current times the ESR. ESR also
has a negative effect on efficiency by contributing I2R
losses during the discharge cycle.

An output capacitor with a capacitance of 100µF, an ESR
of less than 0.1W, and an ESL of less than 5nH is a good
general purpose choice. Tantalum capacitors which meet
these requirements can be obtained from the following
suppliers:

AVX [phone]

Sprague [phone]

Coilcraft [phone]

Coiltronics [phone]

Dale [phone]

Sumida [phone]

XFMRS, Inc. [phone]

OUTPUT CAPACITOR

The choice of output capacitor is also important, as it
controls the output ripple and optimizes the efficiency of
the circuit. Output ripple is influenced by three
parameters: capacitance, ESR, and ESL. The contribution
due to capacitance can be determined by looking at the
change in capacitor voltage required to store the energy
delivered by the inductor in a single charge-discharge
cycle, as determined by the following formula:

22

tV



D

V

=

OUT

For a 1.2V input, a 2.5V output, a 27µH inductor, and a
47µF capacitor, the expected output ripple due to
capacitor value is 11mV.

ON IN

LC V V

  -

2

16

OUT IN

(4)

If ESL spikes are causing output noise problems, an EMI
filter can be added in series with the output.

INPUT CAPACITOR

Unless the input source is a very low impedance battery, it
will be necessary to decouple the input with a capacitor
with a value of between 47µF and 100µF. This prevents
input ripple from affecting the ML4950 control circuitry,
and it also improves efficiency by reducing I2R losses
during the charge and discharge cycles of the inductor.
Again, a low ESR capacitor (such as tantalum) is
recommended.

SETTING THE OUTPUT VOLTAGE

The adjustable output can be set to any voltage between
2V and 3V by connecting a resistor divider to the SENSE
pin as shown in the block diagram. The resistor values R
and R2 can be calculated using the following equation:

RR

+

16

V

=

02

OUT

The value of R2 should be 40kW or less to minimize bias
current errors. R1 is then found by rearranging the
equation:

.

12

R

2

1

(5)

RR

12



OUT




02

.



1= -




(6)

V

6

ML4950

140

V

= 2V

120

100

(mA)

OUT

I

140

120

100

(mA)

OUT

I

OUT

80

60

40

20

0

1.0 1.2 1.4 1.8

VIN (V)

V

= 2.5V

OUT

80

60

40

20

1.6

L = 18µH

L = 33µH

L = 47µH

L = 68µH

L = 18µH

L = 33µH

L = 47µH

L = 68µH

95

V

= 2V

OUT

90

85

EFFICIENCY (%)

80

75

1.0 1.2 1.4 1.8

VIN (V)

95

V

= 2.5V

OUT

90

85

EFFICIENCY (%)

80

1.6

L = 68µH

L = 47µH
L = 33µH

L = 18µH

L = 68µH

L = 47µH

L = 33µH

L = 18µH

0

1.0 1.2 1.4 1.8

VIN (V)

90

V

= 3V

OUT

80

70

60

50

(mA)

40

OUT

I

30

20

10

0

1.0 1.2 1.4 1.8

VIN (V)

1.6

1.6

Figure 4. Output Current vs Input Voltage

L = 18µH

L = 33µH

L = 47µH

L = 68µH

75

1.0 1.2 1.4 1.8

VIN (V)

95

V

= 3V

OUT

90

85

EFFICIENCY (%)

80

75

1.0 1.2 1.4 1.8

VIN (V)

1.6

L = 68µH

L = 47µH
L = 33µH

L = 18µH

1.6

Figure 5. Typical Efficiency as a Function of V

IN

7

ML4950

V

IN

R

A

R

B

1

DETECT

4

RESET

V

REF

FROM

START-UP

CIRCUITRY

+
–

COMP

7

DESIGN CONSIDERATIONS

(Continued)

It is important to note that the accuracy of these resistors
directly affects the accuracy of the output voltage. The
SENSE pin threshold variation is ±3%, and the tolerance of
R1 and R2 will add to this to determine the total output
variation.

Under some circumstances, input ripple cannot be
reduced effectively. This occurs primarily in applications
where inductor currents are high, causing excess output
ripple due to “pulse grouping”, where the charge­discharge pulses are not evenly spaced in time. In such
cases it may be necessary to add a small 20pF to 100pF
ceramic feedforward capacitor (CFF) from the VIN pin to
the SENSE pin. This is particularly true if the ripple voltage
at VIN is greater than 100mV.

SETTING THE

RESET

THRESHOLD

To use the RESET comparator as an input voltage monitor,
it is necessary to use an external resistor divider tied to the
DETECT pin as shown in Figure 7. The resistor values R

A

and RB can be calculated using the following equation:

RR

+

16

V

IN MIN

()

02

.=

AB

R

B

(7)

LAYOUT

Good PC board layout practices will ensure the proper
operation of the ML4950. Important layout considerations
include:

■ Use adequate ground and power traces or planes

■ Keep components as close as possible to the ML4950

■ Use short trace lengths from the inductor to the V

and from the output capacitor to the V

■ Use a single point ground for the ML4950 PWR GND

OUT

pin

pin

L

pin and the input and output capacitors, and connect
GND to PWR GND with a separate trace

A typical PC board layout is shown in Figure 8.

The value of RB should be 100kW or less to minimize bias
current errors. RA is then found by rearranging the
equation:

V



IN MIN

RR

= -

AB

80

60

40

(µA)

IN

I

20

Figure 6. No Load Input Current vs. V

()




.02

0

1.0 1.5 2.0 3.0

For 2V, R1 = 365kW, R2 = 40.2k
For 3V, R1 = 562kW, R2 = 40.2k



1




2V OUTPUT 3V OUTPUT

2.5

W

VIN (V)

W

(8)

IN

L = Sumida CD43, 22µH

Figure 7. Battery Monitoring Circuit

Figure 8. Typical PC Board Layout

8

V

OUT

= 2V

V

OUT

ML4950

= 2.5V

V

IN

I

(mA) EFFICIENCY (%)

OUT

L = 18µH

1.0 45.8 77.5

1.2 65.8 78.0

1.4 89.4 78.3

1.6 111.7 78.9

1.8 132.9 79.8

L = 33µH

1.0 27.9 83.6

1.2 41.9 84.5

1.4 57.8 85.0

1.6 73.7 85.6

1.8 89.8 86.4

L = 47µH

1.0 20.1 85.1

1.2 31.6 86.6

1.4 43.7 87.4

1.6 57.5 87.5

1.8 70.1 88.9

L = 68µH

1.0 14.9 86.5

1.2 23.3 88.5

1.4 32.6 89.1

1.6 43.5 89.6

1.8 54.6 90.9

V

IN

I

(mA) EFFICIENCY (%)

OUT

L = 18µH

1.0 38.3 80.0

1.2 54.5 80.2

1.4 74.6 80.5

1.6 98.5 80.8

1.8 124 81.0

L = 33µH

1.0 22.7 84.2

1.2 33.0 85.2

1.4 47.0 86.0

1.6 61.8 86.6

1.8 79.3 87.0

L = 47µH

1.0 16.4 86.2

1.2 24.1 87.1

1.4 33.4 88.1

1.6 46.1 89.0

1.8 58.6 89.5

L = 68µH

1.0 12.6 86.4

1.2 17.4 87.9

1.4 25.2 89.2

1.6 33.9 90.1

1.8 43.8 90.9

V

= 3V

OUT

L = 18µH

L = 33µH

L = 47µH

L = 68µH

V

IN

1.0 30.9 81.6

1.2 43.8 81.9

1.4 55.4 82.1

1.6 65.6 82.2

1.8 84.4 82.3

1.0 18.7 85.1

1.2 27.9 85.6

1.4 38.1 86.4

1.6 50.6 86.9

1.8 65.4 87.5

1.0 13.3 84.7

1.2 19.9 86.5

1.4 27.9 87.7

1.6 36.7 88.5

1.8 47.4 89.1

1.0 9.2 84.7

1.2 14.0 86.3

1.4 20.5 88.2

1.6 27.6 89.1

1.8 35.7 90.2

I

(mA) EFFICIENCY (%)

OUT

Table 1. Typical I

and Efficiency vs. V

OUT

IN

9

ML4950

PHYSICAL DIMENSIONS

0.017 - 0.027
(0.43 - 0.69)

(4 PLACES)

0.055 - 0.061

(1.40 - 1.55)

inches (millimeters)

Package: S08

0.189 - 0.199
(4.80 - 5.06)

8

PIN 1 ID

1

0.050 BSC
(1.27 BSC)

0.012 - 0.020
(0.30 - 0.51)

SEATING PLANE

0.148 - 0.158
(3.76 - 4.01)

0.059 - 0.069
(1.49 - 1.75)

0.004 - 0.010

8-Pin SOIC

0.228 - 0.244
(5.79 - 6.20)

(0.10 - 0.26)

0º - 8º

0.015 - 0.035
(0.38 - 0.89)

0.006 - 0.010
(0.15 - 0.26)

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML4950CS 0°C to 70°C 8-Pin SOIC (S08)

ML4950ES (Obsolete) –20°C to 70°C 8-Pin SOIC (S08)

© Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.

Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483;
5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959;
5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,754,012; 5,757,174. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any
liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of
others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application
herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.

10

DS4950-01

2092 Concourse Drive

San Jose, CA 95131

Tel: [phone]

Fax: [phone]

www.microlinear.com

7/18/98 Printed in U.S.A.