Datasheet ML4841IS, ML4841CP, ML4841CS, ML4841IP Datasheet (Micro Linear Corporation)

May 1997

ML4841*

Variable Feedforward PFC/PWM Controller Combo

GENERAL DESCRIPTION

The ML4841 is a controller for power factor corrected,

FEATURES

■ Internally synchronized PFC and PWM in one IC

switched mode power supplies. Power Factor Correction
(PFC) allows the use of smaller, lower cost bulk capacitors,

■ Low total harmonic distortion

reduces power line loading and stress on the switching
FETs, and results in a power supply that fully complies
with IEC1000-2-3 specifications. The ML4841 includes
circuits for the implementation of a leading edge, average
current, “boost” type power factor correction, and a
trailing edge, pulse width modulator (PWM).

The PFC frequency of the ML4841 is automatically set at
half that of the PWM frequency generated by the internal
oscillator. This technique allows the user to design with
smaller output components while maintaining the

■ Reduced ripple current in the storage capacitor

between the PFC and PWM sections

■ Average current, continuous mode, boost type,

leading edge PFC

■ High efficiency trailing edge PWM can be configured

for current mode or voltage mode operation

■ Average line voltage compensation with brown-out

control

optimum operating frequency for the PFC. An over-voltage
comparator shuts down the PFC section in the event of a
sudden decrease in load. The PFC section also includes

■ PFC overvoltage comparator eliminates output

“runaway” due to load removal
peak current limiting and input voltage brown-out
protection.

■ Current-fed multiplier for improved noise immunity

■ Overvoltage protection, UVLO, and soft start

BLOCK DIAGRAM *Some Packages Are End Of Life Or Obsoete

13

7.5V

REFERENCE

Q

Q

15

2

4

3

8

7

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RTC

T

VEAO

VEA

­+

MODULATOR

16

GAIN

3.5kΩ

­+

3.5kΩ

IEA

IEAO

8V

1

POWER FACTOR CORRECTOR

+

-

OSCILLATOR

÷2

2.7V

-1V

OVP

+

+

PFC I

-

-

LIMIT

V

CCZ

13.5V

SRQ

SRQ

V

CC

PFC OUT

V

REF

14

12

RAMP 2

9

V

6

SS

5

DC

DUTY CYCLE

LIMIT

8V

1.25V

V

CC

50µA

8V

­+

-

V

+

FB

2.5V

PULSE WIDTH MODULATOR

­+

VIN OK

1V

+

-

DC I

LIMIT

V

CCZ

SRQ

Q

UVLO

PWM OUT

11

1

ML4841

PIN CONFIGURATION

ML4841

16-Pin PDIP (P16)

16-Pin Wide SOIC (S16W)

IEAO

I

AC

I

SENSE

V

RMS

SS

V

DC

RT/C

RAMP 1

PIN DESCRIPTION

PIN NAME FUNCTION

1 IEAO PFC transconductance current error

amplifier output

2I

AC

3I

SENSE

PFC gain control reference input

Current sense input to the PFC current
limit comparator

1

2

3

4

5

6

7

T

8

TOP VIEW

16

VEAO

15

V

FB

14

V

REF

13

V

CC

12

PFC OUT

11

PWM OUT

10

GND

9

RAMP 2

PIN NAME FUNCTION

9 RAMP 2 PWM ramp current sense input

10 GND Ground

11 PWM OUT PWM driver output

12 PFC OUT PFC driver output

4V

RMS

Input for PFC RMS line voltage
compensation

5 SS Connection point for the PWM soft start

capacitor

6V

7RTC

DC

T

PWM voltage feedback input

Connection for oscillator frequency
setting components

8 RAMP 1 PFC ramp input

13 V

CC

Positive supply (connected to an
internal shunt regulator).

14 V

REF

Buffered output for the internal 7.5V
reference

15 V

FB

PFC transconductance voltage error
amplifier input

16 VEAO PFC transconductance voltage error

amplifier output

2

ABSOLUTE MAXIMUM RATINGS

ML4841

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Junction Temperature .............................................. 150°C

Storage Temperature Range ......................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) ..................... 260°C

Thermal Resistance (θ

)

JA

Plastic DIP ....................................................... 80°C/W

VCC Shunt Regulator Current .................................. 55mA

I

Voltage .................................................... -3V to 5V

SENSE

Voltage on Any Other Pin ...... GND - 0.3V to V

I

........................................................................................... 20mA

REF

CCZ

+ 0.3V

Plastic SOIC ................................................... 105°C/W

OPERATING CONDITIONS

IAC Input Current .................................................... 10mA

Peak PFC OUT Current, Source or Sink ................ 500mA

Peak PWM OUT Current, Source or Sink.............. 500mA

PFC OUT, PWM OUT Energy Per Cycle .................. 1.5mJ

Temperature Range

ML4841CX ................................................ 0°C to 70°C

ML4841IX ............................................... -40°C to 85°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, ICC = 25mA, R
TA = Operating Temperature Range (Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

= 23kΩ, R

T

RAMP1

= 28.7kΩ, C

= 400pF, C

T

RAMP1

= 270pF,

VOLTAGE ERROR AMPLIFIER

Input Voltage Range 0 7 V

Transconductance V

Feedback Reference Voltage 2.4 2.5 2.6 V
Input Bias Current Note 2 -0.5 -1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.65 1.0 V
Source Current ∆VIN = ±0.5V, V
Sink Current ∆VIN = ±0.5V, V

Open Loop Gain 60 75 dB

PSRR V

CURRENT ERROR AMPLIFIER

Input Voltage Range -1.5 2 V

Transconductance V
Input Offset Voltage ±3 ±15 mV
Input Bias Current -0.5 -1.0 µA

Output High Voltage 6.0 6.7 V

NON INV

CCZ

NON INV

= V

- 3V < VCC < V

= V

, VEAO = 3.75V 40 70 100 µ

INV

= 6V -40 -90 µA

OUT

= 1.5V 40 90 µA

OUT

- 0.5V 60 75 dB

CCZ

, VEAO = 3.75V 130 195 310 µ

INV

Ω

Ω

Output Low Voltage 0.65 1.0 V
Source Current ∆VIN = ±0.5V, V
Sink Current ∆VIN = ±0.5V, V

Open Loop Gain 60 75 dB

PSRR V

- 3V < VCC < V

CCZ

= 6V -40 -90 µA

OUT

= 1.5V 40 90 µA

OUT

- 0.5V 60 75 dB

CCZ

3

ML4841

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

OVP COMPARATOR

Threshold Voltage 2.6 2.7 2.8 V

Hysteresis 70 95 125 mV

PFC I

COMPARATOR

LIMIT

Threshold Voltage -0.8 -1.0 -1.15 V
∆(PFC I

LIMIT VTH

Delay to Output 150 300 ns

DC I

COMPARATOR

LIMIT

Threshold Voltage 0.9 1.0 1.1 V
Input Bias Current ±0.3 ±1 µA

Delay to Output 150 300 ns

VIN OK COMPARATOR

Threshold Voltage 2.4 2.5 2.6 V

Hysteresis 0.8 1.0 1.2 V

GAIN MODULATOR

Gain (Note 3) IAC = 100µA, V

Bandwidth IAC = 100µA 10 MHz

- Gain Modulator Output) 100 190 mV

= VFB = 0V 0.35 0.50 0.65

RMS

IAC = 50µA, V

IAC = 50µA, V

IAC = 100µA, V

= 1.2V, VFB = 0V 1.15 1.65 2.15

RMS

= 1.8V, VFB = 0V 0.52 0.74 0.96

RMS

= 3.3V, VFB = 0V 0.14 0.20 0.26

RMS

OSCILLATOR

REFERENCE

Output Voltage I

= 250µA, V

AC

= 1.15V, 0.74 0.82 0.90 V

RMS

VFB = 0V

Initial Accuracy TA = 25ºC 188 200 212 kHz

Voltage Stability V

- 3V < VCC < V

CCZ

- 0.5V 1 %

CCZ

Temperature Stability 2%

Total Variation Line, Temp 182 218 kHz

Ramp Valley to Peak Voltage 2.5 V

Dead Time PFC Only 260 400 ns

CT Discharge Current V

Output Voltage TA = 25ºC, I(V

Line Regulation V

Load Regulation 1mA < I(V

= 0V, V

RAMP 2

- 3V < VCC < V

CCZ

REF

= 2.5V 4.5 7.5 9.5 mA

RAMP 1

) = 1mA 7.4 7.5 7.6 V

REF

- 0.5V 2 10 mV

CCZ

) < 20mA 2 15 mV

Temperature Stability 0.4 %

Total Variation Line, Load, Temp 7.25 7.65 V

Long Term Stability TJ = 125ºC, 1000 Hours 5 25 mV

4

ML4841

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

PFC

Minimum Duty Cycle V

Maximum Duty Cycle V

Output Low Voltage I

Output High Voltage I

> 6.7V 0 %

IEAO

< 1.2V 90 95 %

IEAO

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.7 2.0 V

OUT

I

= 10mA, VCC = 8V 0.8 1.5 V

OUT

= 20mA 10 10.5 V

OUT

I

= 100mA 9.5 10 V

OUT

Rise/Fall Time CL = 1000pF 50 ns

PWM

DC Duty Cycle Range 0-44 0-47 0-50 %

V

V

OH

Output Low Voltage I

OL

Output High Voltage I

= -20mA 0.4 0.8 V

OUT

I

= -100mA 0.7 2.0 V

OUT

I

= 10mA, VCC = 8V 0.8 1.5 V

OUT

= 20mA 10 10.5 V

OUT

I

= 100mA 9.5 10 V

OUT

Rise/Fall Time CL = 1000pF 50 ns

SUPPLY

V

CCZ

Shunt Regulator Voltage 12.8 13.5 14.2 V

V

Load Regulation 25mA < ICC < 55mA ±100 ±200 mV

CCZ

V

Total Variation Load, Temp 12.4 14.6 V

CCZ

Start-up Current VCC = 11.2V, CL = 0 0.7 1.0 mA

Operating Current VCC < V

- 0.5V, CL = 0 17 21 mA

CCZ

Undervoltage Lockout Threshold V

Undervoltage Lockout Hysteresis 2.7 3.0 3.3 V

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Includes all bias currents to other circuits connected to the V
Note 3: Gain = K x 5.3V; K = (I

GAIN MOD

– I

) x IAC x (VEAO – 1.5V)–1.

OFFSET

pin.

FB

CCZ

- 1.0 V

CCZ

- 0.7 V

- 0.4 V

CCZ

5

ML4841

TYPICAL PERFORMANCE CHARACTERISTICS

250

200

Ω

150

100

Transconductance (µ )

50

0

053

142

VFB (V)

250

200

Ω

150

100

Transconductance (µ )

50

0

-500 5000

IEA Input Voltage (mV)

Voltage Error Amplifier (VEA) Transconductance (gm) Current Error Amplifier (IEA) Transconductance (gm)

400

300

15

2

4

3

8

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

VEAO

VEA

­+

MODULATOR

16

GAIN

3.5kΩ

200

100

Variable Gain Block Constant - K

0

053142

V

(mV)

RMS

Variable Gain Control Transfer Characteristic

1

IEAO

IEA

+

3.5kΩ

-

8V

+

-

2.7V

-1V

OVP

+

+

PFC I

-

-

LIMIT

V

CCZ

13.5V

SRQ

SRQ

13

7.5V

REFERENCE

Q

Q

V

CC

PFC OUT

V

REF

14

12

FROM PWM
OSCILLATOR

÷2

V

CCZ

UVLO

Figure 1. PFC Section Block Diagram.

6

FUNCTIONAL DESCRIPTION

ML4841

The ML4841 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM section uses current mode control. The
PWM stage uses conventional trailing-edge duty cycle
modulation, while the PFC uses leading-edge modulation.
This patented leading/trailing edge modulation technique
results in a higher useable PFC error amplifier bandwidth,
and can significantly reduce the size of the PFC DC buss
capacitor.

The synchronization of the PWM with the PFC simplifies
the PWM compensation due to the controlled ripple on
the PFC output capacitor (the PWM input capacitor). The
PWM section of the ML4841 runs at twice the frequency
of the PFC, which allows the use of smaller PWM output
magnetics and filter capacitors while holding down the
losses in the PFC stage power components.

In addition to power factor correction, a number of
protection features have been built into the ML4841. These
include soft-start, PFC over-voltage protection, peak
current limiting, brown-out protection, duty cycle limit,
and under-voltage lockout.

POWER FACTOR CORRECTION

Power factor correction makes a non-linear load look like
a resistive load to the AC line. For a resistor, the current
drawn from the line is in phase with and proportional to
the line voltage, so the power factor is unity (one). A
common class of non-linear load is the input of a most
power supplies, which use a bridge rectifier and capacitive
input filter fed from the line. The peak-charging effect
which occurs on the input filter capacitor in such a supply
causes brief high-amplitude pulses of current to flow from
the power line, rather than a sinusoidal current in phase
with the line voltage. Such a supply presents a power
factor to the line of less than one (another way to state this
is that it causes significant current harmonics to appear at
its input). If the input current drawn by such a supply (or
any other non-linear load) can be made to follow the input
voltage in instantaneous amplitude, it will appear resistive
to the AC line and a unity power factor will be achieved.

To hold the input current draw of a device drawing power
from the AC line in phase with and proportional to the
input voltage, a way must be found to prevent that device
from loading the line except in proportion to the
instantaneous line voltage. The PFC section of the
ML4841 uses a boost-mode DC-DC converter to
accomplish this. The input to the converter is the full wave
rectified AC line voltage. No filtering is applied following
the bridge rectifier, so the input voltage to the boost
converter ranges, at twice line frequency, from zero volts
to the peak value of the AC input and back to zero. By
forcing the boost converter to meet two simultaneous
conditions, it is possible to ensure that the current which
the converter draws from the power line agrees with the

instantaneous line voltage. One of these conditions is that
the output voltage of the boost converter must be set
higher than the peak value of the line voltage. A
commonly used value is 385VDC, to allow for a high line
of 270VAC. The other condition is that the current which
the converter is allowed to draw from the line at any given
instant must be proportional to the line voltage. The first
of these requirements is satisfied by establishing a suitable
voltage control loop for the converter, which in turn drives
a current error amplifier and switching output driver. The
second requirement is met by using the rectified AC line
voltage to modulate the output of the voltage control loop.
Such modulation causes the current error amplifier to
command a power stage current which varies directly
with the input voltage. In order to prevent ripple which
will necessarily appear at the output of the boost circuit
(typically about 10VAC on a 385V DC level) from
introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is deliberately
kept low. A final refinement is to adjust the overall gain of
the PFC such to be proportional to 1/V

2

, which linearizes

IN

the transfer function of the system as the AC input voltage
varies.

Since the boost converter topology in the ML4841 PFC is
of the current-averaging type, no slope compensation is
required.

PFC SECTION

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4841. The gain modulator is the heart of the PFC, as it
is this circuit block which controls the response of the
current loop to line voltage waveform and frequency, rms
line voltage, and PFC output voltage. There are three
inputs to the gain modulator. These are:

1) A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified AC
input sine wave is converted to a proportional current
via a resistor and is then fed into the gain modulator at
IAC. Sampling current in this way minimizes ground
noise, as is required in high power switching power
conversion environments. The gain modulator responds
linearly to this current.

2) A voltage proportional to the long-term rms AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the
gain modulator at V
is inversely proportional to V
low values of V

RMS

. The gain modulator’s output

RMS

2

(except at unusually

RMS

where special gain contouring takes
over to limit power dissipation of the circuit
components under heavy brown-out conditions). The
relationship between V

and gain is designated as K,

RMS

and is illustrated in the Typical Performance
Characteristics.

7

ML4841

FUNCTIONAL DESCRIPTION (Continued)

3) The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current
error loop, and ultimately controls the instantaneous
current draw of the PFC from the power line. The general
form for the output of the gain modulator is:

I VEAO

×

I

GAINMOD

AC

≅

V

RMS

×

1

V

2

More exactly, the output current of the gain modulator is
given by:

I K VEAO V I

GAINMOD AC

≅× − ×(.)15

(1)

where K is in units of V-1.

Note that the output current of the gain modulator is
limited to ≅ 200µA.

Current Error Amplifier

V

REF

PFC

OUTPUT

V

FB

15

2.5V

I

AC

2

V

4

I

SENSE

3

-

+

RMS

VEAO

VEA

MODULATOR

16

GAIN

1

IEAO

IEA

­+

+

-

Figure 2. Compensation Network Connections for the

Voltage and Current Error Amplifiers

The current error amplifier’s output controls the PFC duty
cycle to keep the current through the boost inductor a
linear function of the line voltage. At the inverting input to
the current error amplifier, the output current of the gain
modulator is summed with a current which results from a
negative voltage being impressed upon the I
(current into I
on I

represents the sum of all currents flowing in the

SENSE

SENSE

≅ V

/3.5kΩ). The negative voltage

SENSE

SENSE

pin

PFC circuit, and is typically derived from a current sense
resistor in series with the negative terminal of the input
bridge rectifier. In higher power applications, two current
transformers are sometimes used, one to monitor the ID of
the boost MOSFET(s) and one to monitor the IF of the
boost diode. As stated above, the inverting input of the
current error amplifier is a virtual ground. Given this fact,
and the arrangement of the duty cycle modulator polarities
internal to the PFC, an increase in positive current from
the gain modulator will cause the output stage to increase
its duty cycle until the voltage on I

is adequately

SENSE

negative to cancel this increased current. Similarly, if the
gain modulator’s output decreases, the output duty cycle
will decrease, to achieve a less negative voltage on the
I

pin.

SENSE

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop
perturbations. However, the boost inductor will usually be
the dominant factor in overall current loop response.
Therefore, this contouring is significantly less marked than
that of the voltage error amplifier. This is illustrated in the
Typical Performance Characteristics.

Cycle-By-Cycle Current Limiter

The I

pin, as well as being a part of the current

SENSE

feedback loop, is a direct input to the cycle-by-cycle
current limiter for the PFC section. Should the input
voltage at this pin ever be more negative than -1V, the
output of the PFC will be disabled until the protection
flip-flop is reset by the clock pulse at the start of the next
PFC power cycle.

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load
should suddenly change. A resistor divider from the high
voltage DC output of the PFC is fed to VFB. When the
voltage on VFB exceeds 2.7V, the PFC output driver is shut
down. The PWM section will continue to operate. The
OVP comparator has 125mV of hysteresis, and the PFC
will not restart until the voltage at VFB drops below 2.58V.
The VFB should be set at a level where the active and
passive external power components and the ML4841 are
within their safe operating voltages, but not so low as to
interfere with the boost voltage regulation loop.

Error Amplifier Compensation

The PWM loading of the PFC can be modeled as a
negative resistor; an increase in input voltage to the PWM
causes a decrease in the input current. This response
dictates the proper compensation of the two
transconductance error amplifiers. Figure 2 shows the
types of compensation networks most commonly used for

8

FUNCTIONAL DESCRIPTION (Continued)

f

t

OSC

RAMP

=

1

ML4841

the voltage and current error amplifiers, along with their
respective return points. The current loop compensation
is returned to V

to produce a soft-start characteristic on

REF

the PFC: as the reference voltage comes up from zero
volts, it creates a differentiated voltage on IEAO which
prevents the PFC from immediately demanding a full duty
cycle on its boost converter.

There are two major concerns when compensating the
voltage loop error amplifier; stability and transient
response. Optimizing interaction between transient
response and stability requires that the error amplifier’s
open-loop crossover frequency should be 1/2 that of the
line frequency, or 23Hz for a 47Hz line (lowest
anticipated international power frequency). The gain vs.
input voltage of the ML4841’s voltage error amplifier has a
specially shaped nonlinearity such that under steady-state
operating conditions the transconductance of the error
amplifier is at a local minimum. Rapid perturbations in
line or load conditions will cause the input to the voltage
error amplifier (VFB) to deviate from its 2.5V (nominal)
value. If this happens, the transconductance of the voltage
error amplifier will increase significantly, as shown in the
Typical Performance Characteristics. This increases the
gain-bandwidth product of the voltage loop, resulting in a
much more rapid voltage loop response to such
perturbations than would occur with a conventional linear
gain characteristic.

The current amplifier compensation is similar to that of the
voltage error amplifier with the exception of the choice of
crossover frequency. The crossover frequency of the
current amplifier should be at least 10 times that of the
voltage amplifier, to prevent interaction with the voltage
loop. It should also be limited to less than 1/6th that of the
switching frequency, e.g. 16.7kHz for a 100kHz switching
frequency.

For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information for
the design of this class of PFC.

Oscillator (RT/CT)

The oscillator frequency is determined by the values of R
and CT, which determine the ramp and off-time of the
oscillator output clock:

f

OSC

=

tt

RAMP DISCHARGE

1

+

(2)

The ramp-charge time of the oscillator is derived from the
following equation:



V

tCRIn

=××

RAMP T T

REF



V



REF

125

−

375..

−






(3)

The discharge time of the oscillator may be determined
using:

.

V

t

DISCHARGE T T

25

=×=×

.

51

The deadtime is so small (t

CC

RAMP

490

>> t

mA

DEADTIME

(4)

) that the

operating frequency can typically be approximated by:

(5)

EXAMPLE:
For the application circuit shown in the data sheet, with
the oscillator running at:

f kHz

==200

OSC

tRC

=××=×

051 5 10

RAMP T T

.

1

t

RAMP

−

6

Solving for RT x CT yields 1 x 10-5. Selecting standard
components values, CT = 390pF, and R

= 24.9kΩ.

T

RAMP 1

The ramp voltage on this pin serves as a reference to
which the PFC’s current error amp output is compared in
order to set the duty cycle of the PFC switch. The external
ramp voltage is derived from a RC network similar to the
oscillator’s. The PWM’s oscillator sends a synchronous
pulse every other cycle to reset this ramp.

The ramp voltage should be limited to no more than the
output high voltage (6V) of the current error amplifier. The
timing resistor value should be selected such that the
capacitor will not charge past this point before being reset.
In order to ensure the linearity of the PFC loop’s transfer
function and improve noise immunity, the charging
resistor should be connected to the 13.5V VCC rather than
the 7.5V reference. This will keep the charging voltage
across the timing cap in the “linear” region of the charging
curve.

The component value selection is similar to oscillator RC

T

component selection.

f

=

OSC

tt

CHARGE DISCHARGE

1

+

(6)

The charge time of Ramp 1 is derived from the following
equations:

t

CHARGE

2

=

f

OSC

(7)

at V

= 7.5V:

REF

tCR

=××051.

RAMP T T



V Ramp Valley

−

tCRIn

CHARGE T T

=××

CC



V Ramp Peak

−



CC






(8)

9

ML4841

Cms

A

V

nF

SS

=× =5

50

125

200

µ

.

FUNCTIONAL DESCRIPTION (Continued)

At VCC = 13.5V and assuming Ramp Peak = 5V to allow
for component tolerances:

tRC

CHARGE T T

=××0 463.

(9)

The capacitor value should remain small to keep the
discharge energy and the resulting discharge current
through the part small. A good value to use is the same
value used in the PWM timing circuit (CT).

For the application circuit shown in the data sheet, using a
200kHz PWM and 390pF timing cap yields RT:

−

5

×

Rk

=

T

110

−

12

0 463 390 10

( . )( )

×

=

56 2

. Ω

(10)

PWM SECTION

Pulse Width Modulator

The PWM section of the ML4841 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, to which it also provides its basic
timing. The PWM operates in current-mode. In
applications utilizing current mode control, the PWM
ramp (RAMP 2) is usually derived directly from a current
sensing resistor or current transformer in the primary of
the output stage, and is thereby representative of the
current flowing in the converter’s output stage. The DC
I

comparator provides cycle-by-cycle current limiting

LIMIT

and is connected to RAMP 2 internally. If the current sense
signal exceeds the 1V threshold, the PWM switch is
disabled until the protection flip-flop is rest by the clock
pulse at the start of the next PWM power cycle.

PWM Control (RAMP 2)

The PWM section utilizes current mode control. RAMP 2
is generally used as the sampling point for a voltage
representing the current in the primary of the PWM’s
output transformer, derived either by a current sensing
resistor or a current transformer.

Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.25V. Start-up delay can be programmed
by the following equation:

A

Ct

=×

SS DELAY

50

125µ.

V

(11)

where CSS is the required soft start capacitance, and
t

is the desired start-up delay.

DELAY

It is important that the time constant of the PWM soft-start
allows the PFC time to generate sufficient output power
for the PWM section. The PWM start-up delay should be
at least 5ms.

Solving for the minimum value of CSS:

V

BIAS

PWM Current Limit

The DC I
limiter for the PWM section. Should the input voltage at
this pin ever exceed 1V, the output of the PWM will be
disabled until the output flip-flop is reset by the clock
pulse at the start of the next PWM power cycle.

VIN OK Comparator

The V
PFC and inhibits the PWM if this voltage on VFB is less
than its nominal 2.5V. Once this voltage reaches 2.5V,
which corresponds to the PFC output capacitor being
charged to its rated boost voltage, the soft-start
commences.

10

comparator is a cycle-by-cycle current

LIMIT

OK comparator monitors the DC output of the

IN

V

CC

ML4841

GND

10nF

ceramic

1µF

ceramic

Figure 3. External Component Connections to V

CC

ML4841

FUNCTIONAL DESCRIPTION (Continued)

Generating V

The ML4841 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the
voltage internal to the part at 13.5V. This allows a low
power dissipation while at the same time delivering 10V
of gate drive at the PWM OUT and PFC OUT outputs. It is
important to limit the current through the part to avoid
overheating or destroying it. This can be easily done with
a single resistor in series with the Vcc pin, returned to a
bias supply of typically 18V to 20V. The resistor’s value
must be chosen to meet the operating current requirement
of the ML4841 itself (19mA max) plus the current required
by the two gate driver outputs.

EXAMPLE:
With a V
driving a total gate charge of 100nC at 100kHz (1 IRF840
MOSFET and 2 IRF830 MOSFETs), the gate driver current
required is:

I kHz nC kHz nC mA

GATEDRIVE

R

BIAS

To check the maximum dissipation in the ML4841, check
the current at the minimum VCC (12.4V):

I

CC

CC

of 20V, a VCC limit of 14.6V (max) and

BIAS

=×

()

20 14 6

VV

=

20 12 4

=

−

19 15

mA mA

+

VV

−

160

Ω

.

+×

()

160

Ω

=

47 5..

mA

=

=100 45 200 52 15

(12)

(13)

(14)

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock.
The error amplifier output voltage is then compared with
the modulating ramp. When the modulating ramp reaches
the level of the error amplifier output voltage, the switch
will be turned OFF. When the switch is ON, the inductor
current will ramp up. The effective duty cycle of the
trailing edge modulation is determined during the ON
time of the switch. Figure 4 shows a typical trailing edge
control scheme.

In the case of leading edge modulation, the switch is
turned OFF right at the leading edge of the system clock.
When the modulating ramp reaches the level of the error
amplifier output voltage, the switch will be turned ON.
The effective duty-cycle of the leading edge modulation
is determined during the OFF time of the switch. Figure 5
shows a leading edge control scheme.

One of the advantages of this control technique is that
it requires only one system clock. Switch 1 (SW1) turns
off and switch 2 (SW2) turns on at the same instant to
minimize the momentary “no-load” period, thus lowering
ripple voltage generated by the switching action. With
such synchronized switching, the ripple voltage of the
first stage is reduced. Calculation and evaluation have
shown that the 120Hz component of the PFC’s output
ripple voltage can be reduced by as much as 30% using
this method.

The maximum allowable ICC is 55mA, so this is an
acceptable design.

The ML4841 should be locally bypassed with a 10nF and
a 1µF ceramic capacitor. In most applications, an
electrolytic capacitor of between 100µF and 330µF is also
required across the part, both for filtering and as part of
the start-up bootstrap circuitry.

I2 I3

U3

SW2

SW1

+
–

I4

C1

U1

+

DC

VIN

L1

I1

REF

OSC

U4

+

EA

–

RAMP

CLK

Figure 4. Typical Trailing Edge Control Scheme

RL

DFF

R

Q

U2

D

Q

CLK

RAMP

VEAO

TIME

VSW1

TIME

11

ML4841

+

DC

VIN

SW2

SW1

I2 I3

I4

RL

C1

RAMP

L1

I1

U3

+

EA

–

REF

OSC

U4

RAMP

CLK

VEAO

+

–

CMP

U1

DFF

R

Q

D

U2

Q

CLK

Figure 5. Leading/Trailing Edge Control Scheme

VEAO

TIME

VSW1

TIME

12

TYPICAL APPLICATIONS

ML4841

Figure 6 is the application circuit for a complete 100W
power factor corrected power supply, designed using the

AC INPUT

85 TO 265VAC

C3

100nF

C2

470nF

F1

3.15A

R2A

453kΩ

R2B

453kΩ

D12

1A, 50V

D13

1A, 50V

R1A

499kΩ

R1B

499kΩ

R3

75kΩ

R4

13kΩ

R27

22kΩ

C30

330µF

56.2kΩ

3.1mH

Q1

IRF840

R12

27kΩ

L1

R21
22Ω

C7

220pF

8A, 600V

R28

160Ω

1nF

C6

D1

C4

10nF

C12

10µF

BR1

4A, 600V

C1

680nF

D3

50V

178kΩ

178kΩ

100µF

R7A

R7B

general methods and topology suggested in Application
Note 33.

Q2

IRF830

C25

1µF

R14

33Ω

220Ω

T1

R19

R17
33Ω

R30

4.7kΩ

Q3

IRF830

1.1Ω

D7

15V

R20

D6

600V

D5

600V

MBR2545CT

T2

R23

1.5kΩ

D11

R26

10kΩ

TL431

L2

33µH

C21

1800µF

C22

4.7µF

1.2kΩ

C23

100nF

R24

C5

100nF

R15

3Ω

C20

C24

1µF

R18

220Ω

12VDC

RTN

R22

8.66kΩ

R25

2.26kΩ

R5

300mΩ

1W

C19

1µF

C11

10nF

PFC OUT

PWM OUT

DC I

ML4841

R6

24.9kΩ

VEAO

V

FB

V

REF

V

CC

GND

LIMIT

R10

6.2kΩ

D8

1A, 20V

C17

220pF

C15
10nF

1A, 20V

D10

C16

1µF

C18

390pF

390pF

IEAO

I

AC

I

SENSE

V

RMS

SS

V

DC

RAMP 1

RAMP 2

Figure 6. 100W Power Factor Corrected Power Supply.

C13

100nF

C14
1µF

R8

2.37kΩ

C31

1nF

R11

750kΩ

C8

82nF

C9

8.2nF

13

PHYSICAL DIMENSIONS inches (millimeters)

0.740 - 0.760

(18.79 - 19.31)

16

ML4841

Package: P16

16-Pin PDIP

0.02 MIN
(0.50 MIN)
(4 PLACES)

0.170 MAX
(4.32 MAX)

0.125 MIN
(3.18 MIN)

16

PIN 1 ID

1

0.055 - 0.065
(1.40 - 1.65)

0.016 - 0.022
(0.40 - 0.56)

0.400 - 0.414

(10.16 - 10.52)

0.240 - 0.260
(6.09 - 6.61)

0.100 BSC
(2.54 BSC)

0.015 MIN
(0.38 MIN)

SEATING PLANE

Package: S16W

16-Pin Wide SOIC

0.295 - 0.325
(7.49 - 8.26)

0º - 15º

0.008 - 0.012
(0.20 - 0.31)

0.024 - 0.034
(0.61 - 0.86)

(4 PLACES)

0.090 - 0.094
(2.28 - 2.39)

1

PIN 1 ID

0.050 BSC
(1.27 BSC)

0.012 - 0.020
(0.30 - 0.51)

0.291 - 0.301
(7.39 - 7.65)

0.095 - 0.107
(2.41 - 2.72)

SEATING PLANE

0.398 - 0.412

(10.11 - 10.47)

0.005 - 0.013
(0.13 - 0.33)

0º - 8º

0.022 - 0.042
(0.56 - 1.07)

0.009 - 0.013
(0.22 - 0.33)

15

ML4841

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML4841CP 0°C to 70°C 16-Pin Plastic DIP (P16)

ML4841CS0°C to 70°C16-Pin Wide SOIC (S16W) (EOL)

ML4841IP-40°C to 85°C16-Pin Plastic DIP (P16) (OBS)

ML4841IS-40°C to 85°C16-Pin Wide SOIC (S16W) (EOL)

© Micro Linear 1997 is a registered trademark of Micro Linear Corporation.
Products described herein may be covered by one or more of the following patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017;
5,559,470; 5,565761; 5,592,128; 5,594,376. Other patents are pending

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no
responsibility or liability for use of any application herein. The customer is urged to consult with appropriate
legal counsel before deciding on a particular application.

15

2092 Concourse Drive

San Jose, CA 95131

Tel: [phone]

Fax: [phone]

DS4841-01