Datasheet ML4826 Datasheet (Fairchild)

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ML4826

PFC and Dual Output PWM Controller Combo

Features

• Internally synchronized PFC and PWM in one IC

• Low total harmonic distortion

• Low ripple current in the storage capacitor between the
PFC and PWM sections

• Average current, continuous boost, leading edge PFC

• High efficiency trailing edge PWM with dual totem-pole
outputs

• Average line voltage compensation with brown-out
control

• PFC overvoltage comparator eliminates output “runaway”
due to load removal

• Current-fed multiplier for improved noise immunity

• Overvoltage protection, UVLO, and soft start

Block Diagram

19

2

4

3

8

7

9

6

5

10

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RTC

T

RAMP 2

V

DC

V

CC

SS

DC I

LIMIT

VEA

-

+

8V

50µA

8V

20

VEAO

GAIN

MODULATOR

1.5V

11

AGND

3.5kΩ

IEA

-

+

3.5kΩ

-

+

IEAO

8V

OSCILLATOR

-

+

1

POWER FACTOR CORRECTOR

+

-

V

-

FB

2.5V

+

PULSE WIDTH MODULATOR

General Description

The ML4826 is a high power controller for power factor
corrected, switched mode power supplies. PFC allows the
use of smaller, lower cost bulk capacitors, reduces power line
loading and stress on the switching FETs, and results in a
power supply that fully complies with IEC1000-3-2 specifi­cations. The ML4826 includes circuits for the implementa­tion of a leading edge, average current “boost” type power
factor correction and a trailing edge, pulse width modulator
(PWM) with dual totem-pole outputs.

An over-voltage comparator shuts down the PFC section in
the event of a sudden decrease in load. The PFC section also
includes peak current limiting and input voltage brown-out
protection. The PWM section can be operated in current or
voltage mode at up to 250kHz and includes a duty cycle limit
to prevent transformer saturation.

17

V

7.5V

CC

PGND

V

CC2

PFC OUT

DUTY CYCLE

VIN OK

LIMIT

2.7V

-1V

1V

OVP

+

+

PFC I

-

+

-

-

LIMIT

DC I

LIMIT

V

CCZ

V

CCZ

13.5V

REFERENCE

SRQ

Q

SRQ

Q

STQ

Q

SRQ

Q

UVLO

V

REF

V

CC2

PWM 2

PWM 1

PGND

18

15

16

14

13

12

REV. 1.0.5 2/14/02

ML4826 PRODUCT SPECIFICATION

Pin Configuration

ML4826

20-Pin PDIP (P20)

IEAO

I

SENSE

V

RTC

RAMP 1

RAMP 2

DC I

I

AC

RMS

SS

V

DC

LIMIT

1

2

3

4

5

6

7

T

8

9

10

TOP VIEW

20

19

18

17

16

15

14

13

12

11

VEAO

V

FB

V

REF

V

CC2

V

CC1

PFC OUT

PWM 1

PWM 2

PGND

AGND

Pin Description

PIN NAME FUNCTION

1 IEAO PFC transconductance current error amplifier output

2I

3I

4V

AC

SENSE

RMS

5 SS Connection point for the PWM soft start capacitor

6V

7R

T

DC

C

8 RAMP 1 PFC ramp input

9 RAMP 2 When in current mode, this pin functions as the current sense input; when in voltage mode,

10 DC I

LIMIT

11 AGND Analog signal ground

12 PGND Return for the PWM totem-pole outputs

13 PWM 2 PWM driver 2 output

14 PWM 1 PWM drive 1 output

15 PFC OUT PFC driver output

16 V

17 V

18 V

19 V

CC2

CC1

REF

FB

20 VEAO PFC transconductance voltage error amplifier output

PFC gain control reference input

Current sense input to the PFC current limit comparator

Input for PFC RMS line voltage compensation

PWM voltage feedback input

Connection for oscillator frequency setting components

T

it is the PWM input from the PFC output (feedforward ramp)

PWM current limit comparator input

Positive supply for the PWM drive outputs

Positive supply (connected to an internal shunt regulator).

Buffered output for the internal 7.5V reference

PFC transconductance voltage error amplifier input

2

REV. 1.0.5 2/14/02

∆

∆

Ω

PRODUCT SPECIFICATION ML4826

Absolute Maximum Ratings

Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum rat­ings are stress ratings only and functional device operation is not implied.

Parameter Min Max. Units

V

Shunt Regulator Current 55 mA

CC

I

Voltage on Any Other Pin GND – 0.3 V

I

I

Peak PFC OUT Current, Source or Sink 500 mA

Peak PWM OUT Current, Source or Sink 500 mA

PFC OUT, PWM 1, PWM 2 Energy Per Cycle 1.5 mJ

Junction Temperature 150 °C

Storage Temperature Range –65 150 °C

Lead Temperature (Soldering, 10 sec) 260 °C

Thermal Resistance ( θ
Plastic DIP 67 °C/W

Voltage –3 5 V

SENSE

+ 0.3 V

CCZ

REF

Input Current 10 mA

AC

)

JA

20 mA

Operating Conditions

Parameter Min. Max. Units

Temperature Range
ML4826CP2 0 70 °C

Electrical Characteristics

Unless otherwise specified, I
T

= Operating Temperature Range (Note 1)

A

Symbol Parameter Conditions Min. Typ. Max. Units

Voltage Error Amplifier

Input Voltage Range 0 7 V

Transconductance V

Feedback Reference Voltage 2.4 2.5 2.6 V

Input Bias Current Note 2 –0.3 –1.0 µA

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.6 1.0 V

Source Current

Sink Current

Open Loop Gain 60 75 dB

Power Supply Rejection Ratio V

Current Error Amplifier

Input Voltage Range -1.5 2 V

Transconductance V

Input Offset Voltage ±3 ±15 mV

Input Bias Current –0.5 –1.0 µA

= 25mA, R

CC

RAMP 1

= R

T

NON INV

V

= ±0.5V, V

IN

V

= ±0.5V, V

IN

– 3V < V

CCZ

NON INV

= 52.3k Ω , C

= V

= V

, VEAO = 3.75V 50 85 120 µ Ω

INV

OUT

OUT

< V

CC

, VEAO = 3.75V 130 195 310 µ Ω

INV

= C

RAMP1

= 180 pF,

T

= 6V –40 –80 µA

= 1.5V 40 80 µA

– 0.5V 60 75 dB

CCZ

Ω

REV. 1.0.5 2/14/02

3

∆

∆

∆(

ML4826 PRODUCT SPECIFICATION

Electrical Characteristics

Unless otherwise specified, I

= Operating Temperature Range (Note 1)

T

A

= 25mA, R

CC

(continued)

RAMP 1

= R

= 52.3k Ω , C

T

RAMP1

= C

= 180 pF,

T

Symbol Parameter Conditions Min. Typ. Max. Units

Output High Voltage 6.0 6.7 V

Output Low Voltage 0.6 1.0 V

Source Current

Sink Current

V

= ±0.5V, V

IN

V

= ±0.5V, V

IN

= 6V –40 –90 µA

OUT

= 1.5V 40 90 µA

OUT

Open Loop Gain 60 75 dB

Power Supply Rejection Ratio V

CCZ

– 3V < V

CC

< V

– 0.5V 60 75 dB

CCZ

OVP Comparator

Threshold Voltage 2.6 2.7 2.8 V

Hysteresis 80 115 150 mV

PFC I

Comparator

LIMIT

Threshold Voltage –0.8 –1.0 –1.15 V

PFC I

- Gain Modulator

LIMIT

100 190 mV

Output)

Delay to Output 150 300 ns

DC I

comparator

LIMIT

Threshold Voltage 0.9 1.0 1.1 V

Input Bias Current ±0.3 ±1 µA

Delay to Output 150 300 ns

V

OK Comparator

IN

Threshold Voltage 2.4 2.5 2.6 V

Hysteresis 0.8 1.0 1.2 V

Gain Modulator

Gain (Note 3) I

= 100µA, V

AC

I

= 50µA, V

AC

I

= 50µA, V

AC

I

= 100µA, V

AC

RMS

RMS

RMS

RMS

= V

= 0V 0.36 0.55 0.66

FB

= 1.2V, V

= 1.8V, V

= 3.3V, V

= 0V 1.20 1.80 2.24

FB

= 0V 0.55 0.80 1.01

FB

= 0V 0.14 0.20 0.26

FB

Bandwidth IAC = 100µA 10 MHz

Output Voltage I

= 250µA, V

AC

= 1.15V, V

RMS

= 0V 0.72 0.82 0.95 V

FB

Oscillator

Initial Accuracy T

Voltage Stability V

= 25°C 180 190 200 kHz

A

CCZ

– 3V < V

CC

< V

– 0.5V 1 %

CCZ

Temperature Stability 2 %

Total Variation Line, Temp 170 210 kHz

Ramp Valley to Peak Voltage 2.5 V

Dead Time PFC Only 250 500 ns

C

Discharge Current V

T

RAMP 1

= 0V, V(R

C

) = 2.5V 4.5 7.5 9.5 mA

T

T

RAMP 1 Discharge Current 5 mA

Reference

Output Voltage T

Line Regulation V

= 25°C, I(V

A

– 3V < V

CCZ

) = 1mA 7.4 7.5 7.6 V

REF

CC

< V

– 0.5V 2 10 mV

CCZ

4

REV. 1.0.5 2/14/02

PRODUCT SPECIFICATION ML4826

Electrical Characteristics (continued)

Unless otherwise specified, I

= 25mA, R

CC

RAMP 1

TA = Operating Temperature Range (Note 1)

Symbol Parameter Conditions Min. Typ. Max. Units

Load Regulation 1mA < I(V

Total Variation Line, Load, Temp 7.25 7.65 V

Long Term Stability TJ = 125˚C, 1000 Hours 5 25 mV

PFC

Minimum Duty Cycle ML4826-2, V

Maximum Duty Cycle V

Output Low Voltage I

Output High Voltage I

Rise/Fall Time CL = 1000pF 50 ns

PWM

Duty Cycle Range 0-47 0-48 0-50 %

Output Low Voltage I

Output High Voltage I

Rise/Fall Time CL = 1000pF 50 ns

Supply

Shunt Regulator Voltage
(V

)

CCZ

V

Load Regulation 25mA < ICC < 55mA ±150 ±300 mV

CCZ

V

Total Variation Load, temp 12.4 14.6 V

CCZ

Start-up Current VCC = 11.2V, CL = 0 0.7 1.1 mA

Operating Current VCC < V

Undervoltage Lockout
Threshold

Undervoltage Lockout
Hysteresis

Notes:

1. Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.

2. Includes all bias currents to other circuits connected to the VFB pin.

3. Gain = K x 5.3V; K = (I

GAINMOD

- I

OFFSET

= RT = 52.3kΩ, C

) < 20mA 7 20 mV

REF

> 5.7V 0 %

IEAO

< 1.2V 90 95 %

IEAO

= –20mA 0.4 0.8 V

OUT

= –50mA 0.6 3.0 V

I

OUT

I

= 10mA, VCC = 8V 0.7 1.5 V

OUT

= 20mA 9.5 10.5 V

OUT

I

= 50mA 9.0 10 V

OUT

= –20mA 0.4 0.8 V

OUT

I

= –50mA 0.6 3.0 V

OUT

I

= 10mA, VCC = 8V 0.7 1.5 V

OUT

= 20mA 9.5 10.5 V

OUT

I

= 50mA 9.0 10 V

OUT

RAMP1

= CT = 180 pF,

12.8 13.5 14.2 V

– 0.5V, CL = 0 22 28 mA

CCZ

12 13 14 V

2.65 3.0 3.35 V

) x IAC x (VEAO - 1.5V)-1.

REV. 1.0.5 2/14/02 5

ML4826 PRODUCT SPECIFICATION

Typical Performance Characteristics

250

200

Ω

150

100

Transconductance (µ )

50

0

053

142

VFB (V)

250

200

Ω

150

100

Transconductance (µ )

50

0

-500 5000

IEA Input Voltage (mV)

Voltage Error Amplifier (VEA) Transconductance (gm) Current Error Amplifier (IEA) Transconductance (gm)

400

300

200

19

2

4

3

8

7

V

FB

2.5V

I

AC

V

RMS

I

SENSE

RAMP 1

RTC

T

VEAO

VEA

-

+

MODULATOR

20

GAIN

3.5kΩ

100

Variable Gain Block Constant - K

0

053142

V

(mV)

RMS

Variable Gain Control Transfer Characteristic

1

IEAO

IEA

+

3.5kΩ

-

8V

+

-

OSCILLATOR

x2

2.7V

-1V

OVP

+

+

PFC I

-

-

LIMIT

V

CCZ

V

CCZ

13.5V

SRQ

SRQ

UVLO

17

7.5V

REFERENCE

Q

Q

V

CC

PFC OUT

V

REF

18

15

Figure 1. PFC Section Block Diagram.

6 REV. 1.0.5 2/14/02

ML4826 PRODUCT SPECIFICATION

Functional Description

The ML4826 consists of an average current controlled,
continuous boost Power Factor Corrector (PFC) front end
and a synchronized Pulse Width Modulator (PWM) back
end. The PWM can be used in either current or voltage
mode. In voltage mode, feedforward from the PFC output
buss can be used to improve the PWM’s line regulation.
In either mode, the PWM stage uses conventional trailing­edge duty cycle modulation, while the PFC uses leading­edge modulation. This patented leading/trailing edge
modulation technique results in a higher useable PFC error
amplifier bandwidth, and can significantly reduce the size of
the PFC DC buss capacitor.

The synchronization of the PWM with the PFC simplifies the
PWM compensation due to the controlled ripple on the PFC
output capacitor (the PWM input capacitor). The PWM
section of the ML4826 runs at twice the frequency of the
PFC, which allows the use of small PWM output magnetics
and filter capacitors while holding down the losses in the
PFC stage power components.

In addition to power factor correction, a number of protec­tion features have been built into the ML4826. These include
soft-start, PFC over-voltage protection, peak current limit­ing, brown-out protection, duty cycle limit, and under­voltage lockout.

neous line voltage. One of these conditions is that the output
voltage of the boost converter must be set higher than the
peak value of the line voltage. A commonly used value is
385VDC, to allow for a high line of 270VAC

. The other

rms

condition is that the current which the converter is allowed to
draw from the line at any given instant must be proportional
to the line voltage. The first of these requirements is satisfied
by establishing a suitable voltage control loop for the
converter, which in turn drives a current error amplifier and
switching output driver. The second requirement is met by
using the rectified AC line voltage to modulate the output of
the voltage control loop. Such modulation causes the current
error amplifier to command a power stage current which
varies directly with the input voltage. In order to prevent
ripple which will necessarily appear at the output of the
boost circuit (typically about 10VAC on a 385V DC level)
from introducing distortion back through the voltage error
amplifier, the bandwidth of the voltage loop is deliberately
kept low. A final refinement is to adjust the overall gain of
the PFC such to be proportional to 1/V

2

, which linearizes

IN

the transfer function of the system as the AC input voltage
varies.

Since the boost converter topology in the ML4826 PFC is of
the current-averaging type, no slope compensation is
required.

PFC Section

Power Factor Correction

Power factor correction makes a non-linear load look like a
resistive load to the AC line. For a resistor, the current drawn
from the line is in phase with, and proportional to, the line
voltage, so the power factor is unity (one). A common class
of non-linear load is the input of a most power supplies,
which use a bridge rectifier and capacitive input filter fed
from the line. The peak-charging effect which occurs on the
input filter capacitor in such a supply causes brief high­amplitude pulses of current to flow from the power line,
rather than a sinusoidal current in phase with the line
voltage. Such a supply presents a power factor to the line of
less than one (another way to state this is that it causes
significant current harmonics to appear at its input). If the
input current drawn by such a supply (or any other non­linear load) can be made to follow the input voltage in
instantaneous amplitude, it will appear resistive to the AC
line and a unity power factor will be achieved.

To hold the input current draw of a device drawing power
from the AC line in phase with, and proportional to, the input
voltage, a way must be found to prevent that device from
loading the line except in proportion to the instantaneous line
voltage. The PFC section of the ML4826 uses a boost-mode
DC-DC converter to accomplish this. The input to the con­verter is the full wave rectified AC line voltage. No filtering
is applied following the bridge rectifier, so the input voltage
to the boost converter ranges, at twice line frequency, from
zero volts to the peak value of the AC input and back to zero.
By forcing the boost converter to meet two simultaneous
conditions, it is possible to ensure that the current which the
converter draws from the power line agrees with the instanta-

Gain Modulator

Figure 1 shows a block diagram of the PFC section of the
ML4826. The gain modulator is the heart of the PFC, as it is
this circuit block which controls the response of the current
loop to line voltage waveform and frequency, rms line volt­age, and PFC output voltage. There are three inputs to the
gain modulator. These are:

1. A current representing the instantaneous input voltage
(amplitude and waveshape) to the PFC. The rectified
AC input sine wave is converted to a proportional
current via a resistor and is then fed into the gain
modulator at IAC. Sampling current in this way
minimizes ground noise, as is required in high power
switching power conversion environments. The gain
modulator responds linearly to this current.

2. A voltage proportional to the long-term rms AC line
voltage, derived from the rectified line voltage after
scaling and filtering. This signal is presented to the gain
modulator at V
inversely proportional to V
low values of V

. The gain modulator’s output is

RMS

where special gain contouring

RMS

2

(except at unusually

RMS

takes over to limit power dissipation of the circuit com­ponents under heavy brown-out conditions). The rela­tionship between V

and gain is designated as K,

RMS

and is illustrated in the Typical Performance Character­istics.

3. The output of the voltage error amplifier, VEAO. The
gain modulator responds linearly to variations in this
voltage.

7 REV. 1.0.5 2/14/02

ML4826 PRODUCT SPECIFICATION

The output of the gain modulator is a current signal, in the
form of a full wave rectified sinusoid at twice the line
frequency. This current is applied to the virtual-ground
(negative) input of the current error amplifier. In this way
the gain modulator forms the reference for the current error
loop, and ultimately controls the instantaneous current draw
of the PFC from the power line. The general form for the
output of the gain modulator is:

I

GAINMOD

--------------------------------

V

RMS

1V×≅

2

IACVEAO×

More exactly, the output current of the gain modulator is
given by:

I

GAINMOD

K VEAO 1.5V–()× IAC×≅

where K is in units of V

-1

.

(1)

Note that the output current of the gain modulator is limited
to ≅ 200µA.

Current Error Amplifier

The current error amplifier’s output controls the PFC duty
cycle to keep the current through the boost inductor a linear
function of the line voltage. At the inverting input to the
current error amplifier, the output current of the gain
modulator is summed with a current which results from a
negative voltage being impressed upon the I
(current into I
age on I

SENSE

SENSE

≅ V

/3.5kΩ). The negative volt-

SENSE

represents the sum of all currents flowing in

SENSE

pin

the PFC circuit, and is typically derived from a current sense
resistor in series with the negative terminal of the input
bridge rectifier. In higher power applications, two current
transformers are sometimes used, one to monitor the ID of
the boost MOSFET(s) and one to monitor the IF of the boost
diode. As stated above, the inverting input of the current
error amplifier is a virtual ground. Given this fact, and the
arrangement of the duty cycle modulator polarities internal
to the PFC, an increase in positive current from the gain
modulator will cause the output stage to increase its duty
cycle until the voltage on I

is adequately negative to

SENSE

cancel this increased current. Similarly, if the gain modula­tor’s output decreases, the output duty cycle will decrease, to
achieve a less negative voltage on the I

SENSE

pin.

There is a modest degree of gain contouring applied to the
transfer characteristic of the current error amplifier, to
increase its speed of response to current-loop perturbations.
However, the boost inductor will usually be the dominant
factor in overall current loop response. Therefore, this
contouring is significantly less marked than that of the
voltage error amplifier. This is illustrated in the Typical
Performance Characteristics.

Cycle-By-Cycle Current Limiter

The I

pin, as well as being a part of the current feed-

SENSE

back loop, is a direct input to the cycle-by-cycle current
limiter for the PFC section. Should the input voltage at this

pin ever be more negative than -1V, the output of the PFC
will be disabled until the protection flip-flop is reset by the
clock pulse at the start of the next PFC power cycle.

Overvoltage Protection

The OVP comparator serves to protect the power circuit
from being subjected to excessive voltages if the load should
suddenly change. A resistor divider from the high voltage
DC output of the PFC is fed to VFB. When the voltage on
VFB exceeds 2.7V, the PFC output driver is shut down. The
PWM section will continue to operate. The OVP comparator
has 125mV of hysteresis, and the PFC will not restart until
the voltage at V

drops below 2.58V. The VFB should be

FB

set at a level where the active and passive external power
components and the ML4826 are within their safe operating
voltages, but not so low as to interfere with the boost voltage
regulation loop.

V

REF

PFC

OUTPUT

V

FB

19

2.5V

I

AC

2

V

RMS

4

I

SENSE

3

Figure 2. Compensation Network Connections for the

Error Amplifier Compensation

Voltage and Current Error Amplifiers

VEAO

VEA

-

+

MODULATOR

20

GAIN

AGND

IEA

IEAO

1

+

-

11

-

+

The PWM loading of the PFC can be modeled as a negative
resistor; an increase in input voltage to the PWM causes a
decrease in the input current. This response dictates the
proper compensation of the two transconductance error
amplifiers. Figure 3 shows the types of compensation net­works most commonly used for the voltage and current error
amplifiers, along with their respective return points. The
current loop compensation is returned to V

to produce a

REF

soft-start characteristic on the PFC: as the reference voltage
comes up from zero volts, it creates a differentiated voltage
on IEAO which prevents the PFC from immediately
demanding a full duty cycle on its boost converter.

There are two major concerns when compensating the
voltage loop error amplifier; stability and transient response.
Optimizing interaction between transient response and
stability requires that the error amplifier’s open-loop
crossover frequency should be 1/2 that of the line frequency,
or 23Hz for a 47Hz line (lowest anticipated international
power frequency). The gain vs. input voltage of the
ML4826’s voltage error amplifier has a specially shaped

8 REV. 1.0.5 2/14/02

PRODUCT SPECIFICATION ML4826

nonlinearity such that under steady-state operating condi­tions the transconductance of the error amplifier is at a local
minimum. Rapid perturbations in line or load conditions will
cause the input to the voltage error amplifier (V

) to devi-

FB

ate from its 2.5V (nominal) value. If this happens, the
transconductance of the voltage error amplifier will increase
significantly, as shown in the Typical Performance Charac­teristics. This increases the gain-bandwidth product of the
voltage loop, resulting in a much more rapid voltage loop
response to such perturbations than would occur with a con­ventional linear gain characteristic.

The current amplifier compensation is similar to that of the
voltage error amplifier with the exception of the choice of
crossover frequency. The crossover frequency of the current
amplifier should be at least 10 times that of the voltage
amplifier, to prevent interaction with the voltage loop. It
should also be limited to less than 1/6th that of the switching
frequency, e.g. 16.7kHz for a 100kHz switching frequency.

For more information on compensating the current and
voltage control loops, see Application Notes 33 and 34.
Application Note 16 also contains valuable information for
the design of this class of PFC.

Main Oscillator (R

TCT

)

The oscillator frequency is determined by the values of RT
and CT, which determine the ramp and off-time of the
oscillator output clock:

f

OSC

---------------------------------------------------=

t

RAMPtDEADTIME

1

+

(2)

1.1 R

× C

t

RAMPCTRT

Solving for R

x CT yields 2 x 10-4. Selecting standard com-

T

ponents values, C

× 0.51× 110

T

×=

RAMP1

RAMP1

×==

5–

= 1000pF, and RT = 8.63kΩ.

The deadtime of the oscillator adds to the Maximum PWM
Duty Cycle (it is an input to the Duty Cycle Limiter). With
zero oscillator deadtime, the Maximum PWM Duty Cycle is
typically 45%. In many applications, care should be taken

not be made so large as to extend the Maximum

that C

T

Duty Cycle beyond 50%.

PFC RAMP (RAMP1)

The intersection of RAMP1 and the boost current error
amplifier output controls the PFC pulse width. RAMP1 can
be generated in a similar fashion to the R

TCT

ramp.

The current error amplifier maximum output voltage has a
minimum of 6V. The peak value of RAMP1 should not
exceed that voltage. Assuming a maximum voltage of 5V for
RAMP1, Equation 6 describes the RAMP1 time. With a
100kHz PFC frequency, the resistor tied to V

REF

, and a

150pF capacitor, Equation 7 solves for the RAMP1 resistor.

V



REF

---------------------------

RAMP1

×=



V

5V–

REF



(6)

t

RAMP1CRAMP1RRAMP1

1.1 R

× C

× In

RAMP1

×=

The deadtime of the oscillator is derived from the following
equation:

2.5V

at V

t

DEADTIME

= 7.5V:

REF

f

OSC

------------------

5.1mA

200kHz

C

× 490 CT×==

T

1

----------------==

t

RAMP

(3)

The ramp of the oscillator may be determined using:

t

RAMPCTRT

× In

×=

The deadtime is so small (t

-------------------------------



V

3.75–

REF

>> t

RAMP

DEADTIME

(4)

) that the

1.25–

V

REF



operating frequency can typically be approximated by:

f

OSC

1

----------------=

t

RAMP

(5)

For proper reset of internal circuits during dead time, values
of 1000pF or greater are suggested for CT.

EXAMPLE:
For the application circuit shown in the data sheet, with the
oscillator running at:

V



REF

---------------------------

t

RAMP1CRAMP1RRAMP1

× In

×=



V

5V–

REF



R

RAMP1

t

RAMP1

------------------------------------

1.1 C

×

RAMP1

V

REF

60kΩ

150pF

Figure 3.

10µs

-------------------------------- 60kΩ===

1.1 150p F×

ML4826

RAMP1

(7)

PMW SECTION

Pulse Width Modulator

The PWM section of the ML4826 is straightforward, but
there are several points which should be noted. Foremost
among these is its inherent synchronization to the PFC
section of the device, from which it also derives its basic
timing (at twice the PFC frequency in the ML4826-2). The
PWM is capable of current-mode or voltage mode operation.
In current-mode applications, the PWM ramp (RAMP2) is
usually derived directly from a current sensing resistor or

REV. 1.0.5 2/14/02 9

ML4826 PRODUCT SPECIFICATION

)

)

)

current transformer in the primary of the output stage, and is
thereby representative of the current flowing in the con­verter’s output stage. DC I

, which provides cycle-by-

LIMIT

cycle current limiting, is typically connected to RAMP 2 in
such applications. For voltage-mode operation or certain
specialized applications, RAMP2 can be connected to a sep­arate RC timing network to generate a voltage ramp against
which VDC will be compared. Under these conditions, the
use of voltage feedforward from the PFC buss can assist in
line regulation accuracy and response. As in current mode
operation, the DC I

input would be used for output

LIMIT

stage overcurrent protection.

No voltage error amplifier is included in the PWM stage of
the ML4826, as this function is generally performed on the
output side of the PWM’s isolation boundary. To facilitate
the design of optocoupler feedback circuitry, an offset has
been built into the PWM’s RAMP2 input which allows V

DC

to command a zero percent duty cycle for input voltages
below 1.5V.

PWM Current Limit

The DC I

pin is a direct input to the cycle-by-cycle

LIMIT

current limiter for the PWM section. Should the input volt­age at this pin ever exceed 1V, the output of the PWM will be
disabled until the output flip-flop is reset by the clock pulse
at the start of the next PWM power cycle.

VIN OK Comparator

The V

OK comparator monitors the DC output of the PFC

IN

and inhibits the PWM if this voltage on VFB is less than its
nominal 2.5V. Once this voltage reaches 2.5V, which corre­sponds to the PFC output capacitor being charged to its
rated boost voltage, the soft-start commences.

RAMP2

The RAMP2 input is compared to the feedback voltage
(VDC) to set the PWM pulse width. In voltage mode it can
be generated using the same method used for the RTCT
input. In current mode the primary current sense and slope
compensation are fed into the RAMP2 input.

Peak current mode control with duty cycles greater than 50%
requires slope compensation for stability. Figure 4 displays
the method used for the required slope compensation. The
example shown adds the slope compensation signal to the
current sense signal. Alternatively, the slope compensation
signal can also be subtracted form the feedback signal
(VDC).

In setting up the slope compensation first determine the
down slope in the output inductor current. To determine the
actual signal required at the RAMP2 input, reflect 1/2 of the
inductor downslope through the main transformer, current
sense transformer to the ramp input.

Internal to the IC is a 1.5V offset in series with the RAMP2
input. In the example show the positive input to the PWM
comparator is developed from V

(7.5V), this limits the

REF

RAMP2 input (current sense and slope compensation) to 6
Volts peak. The composite waveform feeding the RAMP2

pin for the PWM consists of the reflected output current
signal along with the transformer magnetizing current and
the slope compensation signal.

Equation 8 describes the composite signal feeding RAMP2,
consisting of the primary current of the main transformer and
the slope compensation. Equation 9 solves for the required
slope compensation peak voltage.

OUT

L

R

SENSE

--------------------------

×

n

N

-------

× T

N

CT

S

48V

---------------

20µ H

1

----------

V

FB

n

CT

471Ω

14

---------------

------

× 5µ

sec×× 2.2V===

90

200

S

×+

S

1

---

2

N

S

--------

× TS×

N

P

1

---

2

V

--------------

×

V

RAMP2IPRI

V

SC





V



1

OUT

---

-----------------

×



2

L



Soft Start

Start-up of the PWM is controlled by the selection of the
external capacitor at SS. A current source of 50µA supplies
the charging current for the capacitor, and start-up of the
PWM begins at 1.5V. Start-up delay can be programmed by
the following equation:

50µA

--------------

C

SStDELAY

×=

1.5V

where CSS is the required soft start capacitance, and t
is the desired start-up delay.

It is important that the time constant of the PWM soft-start
allow the PFC time to generate sufficient output power for
the PWM section. The PWM start-up delay should be at least
5ms.

Solving for the minimum value of CSS:

50µA

C

SS

--------------

5ms

× 167nF==

1.5V

Caution should be exercised when using this minimum soft
start capacitance value because premature charging of the SS
capacitor and activation of the PWM section can result if

is in the hysteresis band of the VIN OK comparator at

V

FB

start-up. The magnitude of VFB at start-up is related both to
line voltage and nominal PFC output voltage. Typically, a

1.0µF soft start capacitor will allow time for VFB and PFC

out to reach their nominal values prior to activation of the
PWM section at line voltages between 90Vrms and
265Vrms.

V

CC

The ML4826 is a current-fed part. It has an internal shunt
voltage regulator, which is designed to regulate the voltage
internal to the part at 13.5V. This allows a low power dissi­pation while at the same time delivering 10V of gate drive at
the PWM OUT and PFC OUT outputs. It is important to
limit the current through the part to avoid overheating or
destroying the part.

1.5–≤× V=

(10

DELAY

(11)

(8

(9

10 REV. 1.0.5 2/14/02

PRODUCT SPECIFICATION ML4826

V

17

CC

18

V

7

9

11

10

6

REF

R

TCT

RAMP2

AGND

DC I

LIMIT

V

DC

1V

1.5V

PWM CMP

–

+

DC I

LIMIT

–

+

I

SENSE

x Former

T3
200:1

4 x IN4148

C26

220pF

Q14

PN2222

D1

R16
471Ω

U2

R21

8.63kΩ

C11
1000pF

R13

2.2kΩ

R40

47.0kΩ

R38

10.0kΩ

Figure 4. Slope Compensation and Current Sense

There are a number of different ways to supply VCC to the
ML4826. The method suggested in Figure 5, is one which
keeps the ML4826 ICC current to a minimum, and allows for
a loosely regulated bootstrap winding. By feeding external
gate drive components from the base of Q1, the constant cur­rent source does not have to account for variations in the gate
drive current. This helps to keep the maximum ICC of the
ML4826 to a minimum. Also, the current available to charge
the bootstrap capacitor from the bootstrap winding is not
limited by the constant current source. The circuit guarantees
that the maximum operating current is available at all times
and minimizes the worst case power dissipation in the IC.

Other methods such as a simple series resistor are possible,
but can very easily lead to excessive ICC current in the
ML4826. Figures 6 and 7 show other possible methods for
feeding VCC.

Leading/Trailing Modulation

Conventional Pulse Width Modulation (PWM) techniques
employ trailing edge modulation in which the switch will
turn on right after the trailing edge of the system clock. The
error amplifier output voltage is then compared with the
modulating ramp. When the modulating ramp reaches the

level of the error amplifier output voltage, the switch will be
turned OFF. When the switch is ON, the inductor current will
ramp up. The effective duty cycle of the trailing edge modu­lation is determined during the ON time of the switch. Figure
8 shows a typical trailing edge control scheme.

In the case of leading edge modulation, the switch is turned
OFF right at the leading edge of the system clock. When the
modulating ramp reaches the level of the error amplifier
output voltage, the switch will be turned ON. The effective
duty-cycle of the leading edge modulation is determined
during the OFF time of the switch. Figure 9 shows a leading
edge control scheme.

One of the advantages of this control technique is that it
requires only one system clock. Switch 1 (SW1) turns off
and switch 2 (SW2) turns on at the same instant to minimize
the momentary “no-load” period, thus lowering ripple volt­age generated by the switching action. With such synchro­nized switching, the ripple voltage of the first stage is
reduced. Calculation and evaluation have shown that the
120Hz component of the PFC’s output ripple voltage can be
reduced by as much as 30% using this method.

REV. 1.0.5 2/14/02 11

ML4826 PRODUCT SPECIFICATION

V

RECTIFIED

V

1µF

AC

39kΩ

1500µF

GATE
DRIVE

20V

22kΩ

T1

Q1

PN2222

V

Q2

MJE200

18Ω

CC

ML4826

RTN

BIAS

V

CC

ML4826

RTN

Figure 6.

V

BIAS

1µF

Figure 5. VCC Bias Circuitry

V

CC

ML4826

RTN

Figure 7.

12 REV. 1.0.5 2/14/02

PRODUCT SPECIFICATION ML4826

+

DC

VIN

OSC

REF

U4

L1

I1

U3

+

EA

–

RAMP

CLK

SW2

SW1

I3

I2

I4

RL

C1

RAMP

VEAO

+

–

U1

R

D

DFF

U2

CLK

VSW1

Q

Q

Figure 8. Typical Trailing Edge Control Scheme.

TIME

TIME

+

DC

VIN

L1

I1

REF

OSC

U4

U3

+

EA

–

RAMP

CLK

SW2

SW1

VEAO

+

–

CMP

U1

I3

I2

I4

RL

C1

DFF

R

Q

D

U2

Q

CLK

Figure 9. Typical Leading Edge Control Scheme.

RAMP

VEAO

TIME

VSW1

TIME

REV. 1.0.5 2/14/02 13

ML4826 PRODUCT SPECIFICATION

48VDC

T2

RTN

D22

D20

1N5818

D24

EGP20J

1N5818

C1

330µF

D18

1N5819

R42

10Ω

Q2

FQP9N50

Q1

FQP9N50

R41

10Ω

D19

1N5819

D23A

D17A

T2

R37

Q10

PN2907

D23B

1N4747

R43

10kΩ

D25

EGP20J

R38

10kΩ

1N4747

Q11

PN2907

R44

200Ω

1N4747

D17B

1N4747

200Ω

C21

T1 T1

47nF

C19

R45

L2

R23

20kΩ

C14

20µH

R40

C5

2.2kΩ

2W

220Ω

100µF

820µF

C20

R36

C18

T1

Q1

C108

100nF

100nF

10Ω

470pF

T1

MJE200

R106

680nF

R39

R3

C15

D13

D21B

220Ω

18Ω

225kΩ

4.7µF

20V

Q12

R35

C10

R25

R104

2.2kΩ

PN2222

43.2kΩ

10nF

R28

330Ω

10Ω

C16

C9

Q2

R20

C111

1µF

1µF

PN2222

200Ω

1µF

R27

C7

C104

R34

1kΩ

1nF

1nF

T2

C8

10Ω

Q4

D104

R32

C6

100nF

R22

3.3kΩ

1nF

Q3

2N2907

1N5818

2.37kΩ

R31

150Ω

PN2222

R21

TL431

Q5

PN2907

200Ω

D105

1N5818

R24

2W

Q6

D14

R33

D25

R26

D10

Q9

R14B

200Ω

PN2907

1N4747

10kΩ

EGP20J

10kΩ

1N4747

PN2907

R46

200Ω

2W

39kΩ

1µF

C12

1µF

C11

C13

820µF

L3

100nH

D21A

MBR20100CT-ND

C17

470pF

T1

D26

1N5818

C4

3300µF

66nF

C107

D11

1N5819

R30

10Ω

Q7

FQP9N50

D27

1N5818

D15

EGP20J

D16

1N5818

Q8

FQP9N50

R29

10Ω

D12

1N5819

Y

39kΩ

R14A

C2

AC INPUT

85 TO 265VAC

F1

470nF

1µF

CC

V

RMS

V

C116

1.0µF

R101

C101

R102

100nF

CC2

V

SS

10.2kΩ

470nF

100kΩ

C110

PWM 1

PFC OUT

T

C

T

VDCR

R114

52.3kΩ

C113

R115

8.63kΩ

C112

Q104

PWM 2

RAMP 1

150pF

1nF

PN2222

P GND

A GND

LIMIT

RAMP 2

DC I

C114

220pF

R112

471Ω

1N4148

R116

47kΩ

R113

BR2

4x1N4148

10kΩ

T3

200:1

381kΩ

R10

10kΩ

R1

10kΩ

D1

1N4747

GBU6J

6A, 600V

C109

R110

2.37kΩ

BEAD

FERRITE

5W

R15

100mΩ

D9

1N5818

R6

BEAD

FERRITE

FB

V

REF

V

VEAO

NC

IN A

IN B

RTN

S

V

TC4427

NC

OUT A

VSOUT B

R11

10Ω

10Ω

D8

R8

1N5818

10Ω

R103

C3

1µF

C103

2.2nF

100Ω

R16

C105

R18

100pF

C106

R105

500kΩ

453kΩ

3.3nF

10kΩ

R17

IEAO

500kΩ

R19

IACI

453kΩ

SENSE

C102

R12

CR4

1N4747

D5

Q8

MUR860

FQP9N50

Q7

FQP9N50

L1

420µH

8A

R7

470kΩ

X

R2

470kΩ

1nF

Figure 10. 48V 300W Power Factor Corrected Power Supply

14 REV. 1.0.5 2/14/02

PRODUCT SPECIFICATION ML4826

Mechanical Dimensions inches (millimeters)

Package: P20

20-Pin PDIP

1.010 - 1.035

(25.65 - 26.29)

20

0.060 MIN
(1.52 MIN)

(4 PLACES)

0.170 MAX
(4.32 MAX)

0.125 MIN
(3.18 MIN)

PIN 1 ID

1

0.055 - 0.065
(1.40 - 1.65)

0.016 - 0.022
(0.40 - 0.56)

0.100 BSC
(2.54 BSC)

SEATING PLANE

0.240 - 0.260
(6.09 - 6.61)

0.015 MIN
(0.38 MIN)

0.295 - 0.325
(7.49 - 8.26)

0º - 15º

0.008 - 0.012
(0.20 - 0.31)

REV. 1.0.5 2/14/02 15

ML4826 PRODUCT SPECIFICATION

Ordering Information

Part Number PWM Frequency Temperature Range Package

ML4826CP2 2 x PFC 0°C to 70°C 20-Pin PDIP

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO
ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME
ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR
CORPORATION. As used herein:

1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, and (c) whose failure to
perform when properly used in accordance with
instructions for use provided in the labeling, can be
reasonably expected to result in a significant injury of the
user.

www.fairchildsemi.com

2. A critical component in any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.

2/14/02 0.0m 003

© 2001 Fairchild Semiconductor Corporation

Stock#DS30004826