Datasheet ML4665CQ Datasheet (Micro Linear Corporation)

March 1997
ML4665
Low Cost Single Chip 10BASE-FL Transceiver
GENERAL DESCRIPTION
The ML4665 is a low power, low cost, single chip 10BASE-FL transceiver. The ML4665 contains a fiber optic data quantizer and an LED output driver for direct connection to an optical module(s). The ML4665 offers a standard IEEE 802.3 AU interface that allows it to be directly connected to industry standard manchester encoder/decoder chips or an AUI connector.
The ML4665 provides a highly integrated solution that requires a minimal number of external components. The transmitter offers a 100mA maximum current drive output that directly drives a fiber optic LED transmitter. The receiver offers a highly stable fiber optic data quantizer capable of accepting input signals as low as 2mV
P-P
with
a 55dB dynamic range.
The ML4665 is a lower cost version of the industry standard ML4663. To achieve lower cost, the ML4665 eliminates some functionality (as described below) and is packaged in a 20-lead PLCC package.
BLOCK DIAGRAM
FEATURES
Lower cost single chip solution for 10BASE-FL internal
or external Medium Attachment Units (MAUs)
Incorporates an AU interface
Highly stable data quantizer with 55dB input
dynamic range
Input sensitivity as low as 2mV
100mA maximum current driven fiber optic LED driver
for accurate launch power
Single +5 volt supply
No crystal or clock required
Link monitor LED indicator
V
CC
(+5V)
Tx
+5V
RTSET
P-P
AV
CC
20912
Tx+
Tx–
COL+
COL–
Rx+
Rx–
7
8
2
3
4
5
GND V
AUI
RECEIVER
Tx
SQUELCH
AUI
DRIVER
AUI
DRIVER
14 6 10 1 17 15
CC
(+5V)
1MHz IDLE
SIGNAL
COL
10MHz GATED
OSCILLATOR
LOOPBACK
MUX
RRSET
+5V
Tx
Rx
CMP
AGNDLBDIS C
FIBER OPTIC
LED
DRIVER
JABBER
RECEIVE SQUELCH
AMP
LINK DETECT
TIMER
13
TxOUT
LMON
11
BIAS
19
V
+
IN
VIN-
18
16
V
DC
V
REF
1
ML4665
PIN CONNECTION
20-Pin PLCC (Q20)
COL–
3 2 1 20 19
4
Rx+
5
Rx–
6
V
CC
7
Tx+
8
Tx–
9 10111213
RTSET
ML4665
COL+
LBDIS
RRSET
LMON
CC
AV
Tx
CC
V
+
IN
V
18
17
16
15
14
TxOUT
VIN–
AGND
V
DC
C
TIMER
GND
2
PIN DESCRIPTION
ML4665
PIN NAME FUNCTION
1 LBDIS Loopback disable. When this pin is
tied to VCC, the AUI transmit pair data is not looped back to the AUI receive pair. The ML4665 will now operate in the full duplex mode. When tied to GND or left floating, the AUI transmit pair data is looped back to the AUI receive pair, except during collision. The ML4665 will now operate in the half duplex mode.
2 COL+ Gated 10MHz oscillation used to 3 COL– indicate a collision or jabber.
Balanced differential line driver outputs that meet AUI specifications.
4 Rx+ Manchester encoded receive data 5 Rx– output to the local device. Balanced
differential line driver outputs that meet AUI specifications.
6VCC+5 volt power input.
7 Tx+ Balanced differential line receiver 8 Tx– inputs that meet AUI specifications.
These inputs may be transformer or capacitively coupled. The Tx input pins are internally DC biased for AC coupling.
9 RTSET Sets the current driven output of the
transmitter.
10 RRSET A 1% 61.9k resistor tied from this
pin to VCC sets the biasing currents for internal nodes.
PIN NAME FUNCTION
11 LMON Link Monitor “Low Light” LED status
output. This pin is pulled low when the voltage on the VIN+, VIN– inputs exceed the minimum threshold and there are transitions on VIN+, VIN– indicating an idle signal or active data. If either the voltage on the VIN+, VIN– inputs fall below the minimum threshold or transitions cease on VIN+, VIN–, LMON will go high. Active low LED driver, open collector.
12 VCCTx +5 volt supply for fiber optic LED
driver.
13 TxOUT Fiber optic LED driver output.
14 GND Ground Reference.
15 C
16 V
17 AGND Analog Filtered Ground.
18 VIN– This input pin should be
19 VIN+ This input pin should be
20 AV
TIMER
DC
CC
A capacitor from this pin to V determines the Link Monitor response time.
An external capacitor on this pin integrates an error signal which nulls the offset of the input amplifier. If the DC feedback loop is not being used, this pin should be connected to V
capacitively coupled to the input source or to filtered AVCC. (The input resistance is approximately
1.3k.)
capacitively coupled to the input source or to filtered AVCC. (The input resistance is approximately
1.3k.)
Analog Filtered +5 volts.
REF
CC
.
3
ML4665
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with respect to ground.
Output Current
TxOUT .............................................................. 120mA
Junction Temperature .............................................. 150°C
Storage Temperature Range ...................... –65°C to 150°C
Lead Temperature (Soldering) .................................. 260°C
Thermal Resistance (θJA)....................................... 78°C/W
Power Supply Voltage Range
V
................................................................... GND –0.3 to 6V
CC
Input Voltage Range
Digital Inputs
(SQEN, LBDIS) .................... GND –0.3 to VCC +0.3V
Tx+, Tx–, VIN+, VIN– ............... GND –0.3 to VCC +0.3V
Input Current
RRSET, RTSET, LMON .......................................... 60mA
OPERATING CONDITIONS
Supply Voltage (V
LED on Current ....................................................... 10mA
RRSET .......................................................... 61.9k ± 1%
RTSET ............................................................. 115 ± 1%
) ........................................... 5V ± 5%
CC
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, TA = Operating Temperature Range, VCC = V
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
CC
V
I
OUT
V
V
OL
SQ
DO
Power Supply Current ICC:V While Transmitting
LED Driver: V
Transmit Peak Output Current RTSET = 115 (Note 4) 44 52 57 mA
Transmit Squelch Voltage Level –300 –250 –200 mV (Tx+, Tx–)
Differential Output Voltage ±550 ±1200 mV (Rx±, COL±)
OL
= 5V, RTSET = 115 (Note 2) 140 mA
CC
IOL = 10mA (Note 3) 0.8 V
Tx = 5V ± 5% (Note 1)
CC
V
CM
V
DOO
V
LBTH
V
TXCM
V
INCM
A
V
V
ISR
V
N
R
IN
V
TH
H Hysteresis 20 %
Common Mode 4.0 V
Output Voltage (Rx±, COL±)
Differential Output
Voltage Imbalance (Rx±, COL±) ±40 mV
LBDIS Threshold Loopback disabled VCC – 0.1 V
Loopback enabled 1.0 V
Common Mode Voltage (Tx+, Tx–) 3.5 V
Common Mode Voltage 1.65 V (VIN+, VIN–)
Amplifier Gain 100 V/V
Input Signal Range 2 1600 mV
Input Referred Noise 50MHz BW 25 µV
Input Resistance VIN+ = V
Input Threshold Voltage 5 6 7 mV
0.8 1.3 2.0 k
IN
P–P
4
ML4665
AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER MIN TYP MAX UNITS
Transmit
F
TXIDF
t
TXDC
t
TXNPW
t
TXODY
t
TXLP
t
TXFPW
t
TXSOI
t
TXSDY
t
TXJ
Receive
F
RXSFT
t
RXODY
t
RXFX
t
RXSDY
t
RXJ
t
AR
t
AF
Collision
Transmit Idle Frequency 0.85 1.25 MHz
Transmit Idle duty Cycle 45 55 %
Transmit Turn-On Pulse Width 20 ns
Transmit Turn-On Delay 200 ns
Transmit loopback Start-up Delay 500 ns
Transmit Turn-Off Pulse Width 180 ns
Transmit Start of Idle 400 2100 ns
Transmit Steady State Propagation Delay 15 50 ns
Transmit Jitter into 31 Load ±1.5 ns
Receive Squelch Frequency Threshold 2.51 4.5 MHz
Receive Turn-On Delay 285 ns
Last Bit Received to Slow Decay Output 230 300 ns
Receive Steady State Propagation Delay 15 50 ns
Receive Jitter ±1.5 ns Differential Output Rise Time 20% to 80% (Rx±, COL±)4ns Differential Output Fall Time 20% to 80% (Rx±, COL±)4ns
t
CPSQE
t
SQEXR
F
CLF
P
CLPDC
Collision Present to SQE Assert 0 350 ns
Time for SQE to Deactivate After Collision 0 700 ns
Collision Frequency 8.5 11.5 MHz
Collision Pulse Duty Cycle 40 50 60 %
Jabber and LMON Timing
t
JAD
t
JRT
t
JSQE
t
LLPH
t
LLCL
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions. Note 2: This dose not include the current from the AUI pull-down resistors, or LED status outputs. Note 3: LED drivercan sink up to 20mA, but V Note 4: Does not include pre-bias current for fiber optic LED which would typically be 3mA.
Jabber Activation Delay 20 70 150 ms
Jabber Reset Unjab Time 250 450 750 ms
Delay from Outputs Disabled to Collision Oscillator On 100 ns
Low Light Present to LMON High 3 5 10 µs
Low Light Present to LMON Low 250 750 ms
will be higher.
OL
5
ML4665
CHASSIS REF
1
9
2
10
3
11
4
12
5
13
6
14
7
15
8
AULCP– AULCP+
AULTX– AULTX+
AULRX– AULRX+ AULPWR+ AULPWR–
116
CI
2
15
13
4
D0
5
12
7
10
D1
8
9
360
360
39
0.1µF
39
360
360
3
2
8
7
5
4
COL–
COL+
Tx–
Tx+
Rx–
Rx+
510
RP1
11
LMON
ML4665
61.9k
10 9
RRSET RTSET
TxOUT
TxV
LBDIS
C
TIMER
V
DC
VIN+
V
IN
115
13
12
CC
1 +5V
0.05
15
0.1
16
0.01
19
18
1k
0.01
–V
+V
+5V
0.1µF
2,6,7
+V
RF
–V
6
FIBER OPTIC CABLE
0.1µF
RF
FIBER OPTIC CABLE
3
HP HFBR1414
OR
OPTEK
OPC1414
FIBER OPTIC
TRANSMITTER
RF
RF
R17 10
2
1
HP HFBR2416
4
OR
5
OPTEK
OPC2416
8
33µ
73
GND AGND AV
V
CC
614 17
510
RP1
D1
VR1
Q1
IN OUT
+
0.1µ
LM340
GND
4.7µ
+
+
0.1µ
–V
RF
CC
20
+V
4.7µH
4.7µH
RF
4.7
–V
+V
RF
0.1
+
–V
RF
FIBER OPTIC RCVR
RF
Figure 1. ML4665 Schematic Diagram
6
SYSTEM DESCRIPTION
RTSET
=
52mA
I
OUT
 
 
115
VCCTx
TxOUT
I
OUT
ML4665
Figure 1 shows a schematic diagram of the ML4665 in an internal or external 10BASE-FL MAU. On one side of the transceiver is the AU interface and the other is the fiber optic interface. The AU interface is AC coupled when used in an external transceiver or an internal transceiver. The AU interface for an external transceiver includes isolation transformers, some biasing resistors, and a voltage regulator for power.
The fiber optic side of the transceiver requires an external fiber optic transmitter and fiber optic receiver. The transmitter uses a current driven output that directly drives the fiber optic transmitter. The receive side of the transceiver accepts the data after passing through a fiber optic receiver, which consists of a module containing a pin diode and a transimpedance amplifier.
AU INTERFACE
The AU interface consists of 3 pairs of signals: DO, CI and DI (Figure 1). The DO pair contains transmit data from the DTE which is received by the transceiver and sent out onto the fiber optic cable. The DI pair contains valid data that has been either received from the fiber optic cable or looped back from the DO, and output through the DI pair to the DTE. The CI pair indicates whether a collision has occurred. It is an output that oscillates at 10MHz if a collision or Jabber has taken place, otherwise it remains idle.
When the transceiver is external, these three pairs are AC coupled through isolation transformers, while an internal transceiver may be capacitively coupled. Tx+, Tx– is internally DC biased (shifted up in voltage) for the proper common mode input voltage.
The two 39 1% resistors (or one 78 1% resistor) tied to
the Tx+ and Tx– pins will provide the proper termination. The CI and DI pair, which are output from the transceiver
to the AUI cable, require 360 pull down resistors when terminated with a 78 load. However, on a DTE card, CI and DI do not need 78 terminating resistors. This also
means that the pull down resistors on CI and DI can be
1k or greater depending upon the particular Manchester
encoder/decoder chip used. Using higher value pull down resistors as in a DTE card will save power. Refer to Application Note 13 for a more detailed explanation of the AUI pull-down resistors.
The AUI drivers are capable of driving the full 50 meters of cable length and have a rise and fall time of typically 4ns. In the idle state, the outputs go to the same voltage to prevent DC standing current in the isolation transformers.
Before data will be transmitted onto the fiber optic cable from the AUI interface, it must exceed the squelch requirements for the DO pair. The Tx squelch circuit serves the function of preventing any noise from being transmitted onto the fiber. This circuit rejects signals with pulse widths less than typically 20ns (negative going), or with levels less than –250mV. Once Tx squelch circuit has unsquelched, it looks for the start of idle signal to turn on the squelch circuit again. The transmitter turns on the squelch again when it receives an input signal at Tx+, Tx– that is more positive than –250mV for more than approximately 180ns.
At the start of a packet transmission, no more than 2 bits are received from the DO circuit, and are not transmitted onto the fiber optic cable. The difference between start-up delays (bit loss plus steady-state propagation delay) for
any two packets that are separated by 9.6µs or less will
not exceed 200ns.
FIBER OPTIC LED DRIVER
The output stage of the transmitter is a current mode switch which develops the output light by sinking current through the LED into the TxOUT pin. Once the current requirement for the LED is determined, the RTSET resistor is selected. The following equation is used to select the correct RTSET resistor:
The ML4665 transmitter output will drive up to 100mA,
which requires RTSET to equal 60Ω. The transmitter enters
the idle state when it detects start of idle on Tx+ and Tx– input pins. After detecting the start of idle the transmitter switches to a 1MHz output idle signal.
The output current is switched through the TxOUT pin during the on cycle and the VCCTx pin during the off cycle as shown in figure 2. Since the sum of the current in these two pins is constant, VCCTx should be connected as close as possible to the VCC connection for the LED.
If not driving an optical LED directly, a differential output can be generated by tying resistors from VCCTx and TxOUT to VCC as shown in figure 3. The minimum voltage on these two pins should not be less than VCC – 2V.
TRANSMISSION
The transmit function consists of detecting the presence of data from the AUI DO input (Tx+, Tx–) and driving that data onto the fiber optic LED transmitter. A positive signal on the Tx+ lead relative to the Tx– lead of the DO circuit will result in no current, hence the fiber optic LED is in a low light condition. When Tx+ is more negative than Tx–, the ML4665 will sink current into the chip and the fiber optic LED will light up.
Figure 2. Fiber Optic LED Driver Structure.
7
ML4665
V
OS
V
OUT
+
V
OUT
V
CC
VCCTx
51
51
51
TxOUT
RTSET = 560 I
= 15.9mA
OUT
ECL
Figure 3. Converting Optical LED Driver Output to
Differential ECL.
RECEPTION
The input to the transceiver comes from a fiber optic receiver as shown in figure 1. At the start of packet reception no more than 2.7 bits are received from the fiber cable, and are not transmitted onto the DI circuit. The receive squelch will reject frequencies lower than
2.51MHz.
While in the unsquelch state, the receive squelch circuit looks for the start of idle signal at the end of the packet. Start of idle occurs when the input signal remains idle for more than 160ns. When start of idle is detected, the receive squelch circuit returns to the squelch state and the start of idle signal is output on the DI circuit (Rx+, Rx–).
COLLISION
Whenever the receiver and the transmitter are active at the same time the chip will activate the collision output. The collision output is a differential square wave matching
the AUI specifications and capable of driving a 78 load. The frequency of the square wave is 10MHz ± 15% with a
60/40 to 40/60 duty cycle. The collision oscillator also is activated Jabber.
LOOPBACK
The loopback function emulates a 10BASE-T transceiver whereby the transmit data sent by the DTE is looped back over the AUI receive pair. Some LAN controllers use this loopback information to determine whether a MAU is connected by monitoring the carrier sense while transmitting. The software can use this loopback information to determine whether a MAU is connected to the DTE by checking the status of carrier sense after each packet transmission.
When data is received by the chip while transmitting, a collision condition exits. This will cause the collision oscillator to turn on and the data on the DI pair will follow VIN+, VIN–. After a collision is detected, the collision oscillator will remain on until either DO or VIN+, VIN– go idle.
Loopback can be disabled by strapping LBDIS to VCC. In this mode the chip operates as a full duplex transmitter and receiver, and collision detection is disabled. A loopback through the transceiver can be accomplished by tying the fiber transmitter to the receiver.
JABBER FUNCTION REQUIREMENTS
The Jabber function prevents a babbling transmitter from bringing down the network. Within the transceiver is a Jabber timer that starts at the beginning of each transmission and resets at the end of each transmission. If the transmission last longer than 20ms the jabber logic disables the transmitter, and turns on the collision signal COL+, COL–. When Tx+ and Tx– finally go idle, a second timer measures 0.5 seconds of idle time before the transmitter is enabled and collision is turned off. Even though the transmitter is disabled during jabber, the 1MHz idle signal is still transmitted.
LOW LIGHT CONDITION
The LMON LED output is used to indicate a low light condition. LMON is activated low when both the receive power exceeds the Link Monitor threshold and there are transitions on VIN+, V
– less than 3µs apart. If either one
IN
of these conditions do not exist, LMON will go high.
INPUT AMPLIFIER
The VIN+, VIN– input signal is fed into a limiting amplifier
with a gain of about 100 and input resistance of 1.3k.
Maximum sensitivity is achieved through the use of a DC restoration feedback loop and AC coupling the input. When AC coupled, the input DC bias voltage is set by an on-chip network at about 1.7V. These coupling capacitors, in conjunction with the input impedance of the amplifier, establish a high pass filter with 3dB corner frequency, fL, at
=
2 300C
π1
1
(1)
f
L
Since the amplifier has a differential input, two capacitors of equal value are required. If the signal driving the input is single ended, one of the coupling capacitors can be tied to AV
as shown in figure 1.
CC
The internal amplifier has a lowpass filter built-in to band limit the input signal which in turn will improve the signal to noise ratio.
Although the input is AC coupled, the offset voltage
within
the amplifier will be present at the amplifier’s output. This is represented by VOS in figure 4. Inorder to reduce this error a DC feedback loop is incorporated. This negative feedback loop nulls the offset voltage, forcing VOS to be zero. Although the capacitor on VDC is non-critical, the pole it creates can effect the stability of the feedback loop. To avoid stability problems, the value of this capacitor should be at least 10 times larger than the input coupling capacitors.
Figure 4.
8
ML4665
The comparator is a high-speed differential zero crossing detector that slices and accurately digitizes the receive signal. The output of the comparator is fed in parallel into both the receive squelch circuit and the loopback MUX.
LINK DETECT CIRCUIT AND LOW LIGHT
The link detect circuit monitors the input signal and determines when the input falls below a preset voltage level. When the input falls below a preset voltage, the ML4665 goes into the Low Light state. In the Low Light state the transmitter is disabled, but continues sending the 1MHz idle signal, the loopback is disabled, the receiver is disabled, and the LMON LED pin goes to high shutting off the LMON LED. To return to the Link Pass state, the optical receiver power must be 20% higher than the shut­off state. This built-in hysteresis adds stability to the Link Monitor circuit. Once the receiver power threshold is exceeded, the ML4665 waits 250ms to 750ms, then checks to see that Tx+. Tx– is idle and no data is being received before re-enabling the transmitter, receiver, loopback circuit, and lighting up the LMON LED.
The V
pin is used to adjust the sensitivity of the
THADJ
receiver. The ML4665 is capable of exceeding the 10BASE-FL specifications for sensitivity. The sensitivity is dependent on the layout of the PC board. A good low noise layout will exceed the 10BASE-FL specifications, while a poor layout will fail to meet the sensitivity and BER spec.
The response time of the Link Detect circuit is set by the C
pin. Starting from the link off state the link can be
TIMER
switched on if the input exceeds the set threshold for a time given by:
TIMER
× 0.7V
A700µ
(3)
C
T
=
DIFFERENCES BETWEEN ML4665 AND ML4663/ML4668
The ML4665 is a low cost, reduced pin count alternative to the industry standard ML4663/ML4668. The following itemizes the differences between the devices.
1. The SQEN pin found in the ML4663/ML4668, has been removed. In the ML4665, jabber is always enabled and SQE pulses are not sent on the AUI collision pair following a transmission.
2. The JAB, CLSN, RCV and XMT LED pins on the ML4663/ML4668 have been removed. LEDs showing transmit, receive and collision activity can be added externally. See Figure 6.
3. The V
REF
and V
pins available on the
THADJ
ML4663/ML4668, have been removed. In the ML4665, these pins are tied together internally, and the threshold is set at 6mV
typical. This
P-P
threshold cannot be externally modified.
V
CC
V
CC
510
COL+, Rx+
Tx+
VBB
MC10125
(OR EQUIVALENT)
5k
IN914 (OR EQUIVALENT)
0.01µ
100k
74C04
(OR EQUIVALENT)
Figure 6.
To switch the link from on to off, the above time will be
doubled. A value of 0.05µF will meet to 10BASE-FL
specifications.
R1
R2
VREF
VTHADJ
REF
THRESH
GEN
Figure 5.
9
ML4665
TIMING DIAGRAMS
Tx+
Tx–
t
TXODY
TxOUT
t
TXLP
t
TXNPW
VALID DATA
t
TXSDY
VALIDIDLE IDLEDATA
t
TXFPW
t
TXSOI
F
TXIDF
1
Rx+
Rx–
VIN+
V
IN
Rx+
Rx–
VALID DATA
Figure 7. Transmit and Loopback Timing
t
ROXDY
VALID DATA
t
RXSDY
VALID DATA
t
t
AR
t
AF
RXFX
Figure 8. Receive Timing
10
TIMING DIAGRAMS
ML4665
Tx+
Tx–
V
IN
V
IN
COL+
COL–
Rx+
Rx–
V
IN
V
IN
Tx+
Tx–
VALID DATA
+
t
Tx Tx Rx RxRx
VALID DATA
CPSQE
CS0
Figure 9. Collision Timing
+
VALID DATA
VALID DATA
COL+
COL–
VIN+
V
COL+
COL–
t
CPSQE
CS0
Figure 10. Collision Timing
IN
Tx+
Tx–
Rx+
Rx–
VALID DATA
t
SQEXR
CS0
Rx Rx Rx Tx Tx Tx
Figure 11. Collision Timing
11
ML4665
TIMING DIAGRAMS
TxOUT
V
+
IN
V
IN
COL+
COL–
VALID DATA
t
SQEXR
CS0
Rx+
Rx–
COL+
COL–
Tx+
Tx –
TxOUT
COL+
COL–
RxIN RxIN RxIN RxIN RxIN
Figure 12. Collision Timing
1
F
CLF
Figure 13. Collision Timing
VALID DATA
t
JAD
VALID
DATA
t
JSQE
CS0
t
JRT
12
VIN+
V
IN
LMON
Figure 14. Jabber Timing
t
LLPH
t
LLCL
Figure 15. LMON Timing
ML4665
PHYSICAL DIMENSIONS inches (millimeters)
Package: Q20
0.385 - 0.395 (8.89 - 10.03)
0.350 - 0.356 (8.89 - 9.04)
1
20-Pin PLCC
0.042 - 0.056 (1.07 - 1.42)
0.025 - 0.045 (0.63 - 1.14)
(RADIUS)
0.042 - 0.048 (1.07 - 1.22)
PIN 1 ID
6
0.050 BSC (1.27 BSC)
0.026 - 0.032 (0.66 - 0.81)
0.013 - 0.021 (0.33 - 0.53)
11
SEATING PLANE
0.350 - 0.356
16
(8.89 - 9.04)
0.165 - 0.180 (4.19 - 4.57)
0.385 - 0.395 (8.89 - 10.03)
0.146 - 0.156 (3.71 - 3.96)
0.009 - 0.011 (0.23 - 0.28)
0.100 - 0.110 (2.54 - 2.79)
0.200 BSC (5.08 BSC)
0.290 - 0.330 (7.36 - 8.38)
ORDERING INFORMATION
PART NUMBER TEMPERATURE PACKAGE
ML4665CQ 0°C TO 70°C 20-pin PLCC (Q20)
© Micro Linear 1997 is a registered trademark of Micro Linear Corporation Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel before deciding on a particular application.
13
2092 Concourse Drive
San Jose, CA 95131
Tel: 408/433-5200
Fax: 408/432-0295
DS4665-01
Loading...