Datasheet ML4663CQ Datasheet (Micro Linear Corporation)

March 1997

ML4663

Single Chip 10BASE-FL Transceiver

GENERAL DESCRIPTION

The ML4663 single-chip 10BASE-FL transceiv er integr ates
both a ML4662 10BASE-FL transcei v er with a ML4622
fiber optic data quantizer to implement a highly integrated
solution for 10BASE-FL transceiv ers. The ML4663 offers a
standard IEEE 802.3 A U interface that allows it to be
directly connected to industry standard manchester
encoder/decoder chips or an AUI connector.

The ML4663 provides a highly integr ated solution that
requires a minimal number of external components, and is
compliant to the IEEE 802.3 10BASE-FL standard. The
transmitter offers a current drive output that directly driv es
a fiber optic LED transmitter. The receiver offers a highly
stable fiber optic data quantizer capable of accepting
input signals as low as 2mV

with a 55dB dynamic

P-P

range.
The transmitter automatically inserts 1MHz signal during

idle time and removes this signal on reception. Low Light
is continuously monitored for both activity as well as
power level. Fiv e LED status indicators monitor error
conditions as well as transmissions, receptions and
collisions.

BLOCK DIAGRAM

5 17 12 20 27

FEATURES

■ Single chip solution for 10BASE-FL internal or external

Medium Attachment Units (MA Us)

■ Incorporates an AU interface

■ Highly stable data quantizer with 55dB input

dynamic range

■ Input sensitivity as low as 2mV

■ Current driven fiber optic LED driver for accur ate

launch power

■ Single +5 volt supply

■ No crystal or clock required

■ Five network status LED outputs

V

CC

(+5V)

Tx

+5V

RTSETSQEN/JABD

GND

P-P

AV

CC

Tx+

10

Tx–

11

Please See ML4668 for New Designs

COL+

2

COL–

3

Rx+

6

Rx–

7

GND V

AUI

RECEIVER

Tx

SQUELCH

AUI

DRIVER

AUI

DRIVER

(+5V)

1MHz IDLE

SIGNAL

SQE

10MHz GATED

OSCILLATOR

Tx

LOOPBACK

MUX

LBDIS AGND C

CC

RRSET

+5V

Rx

CMP

FIBER OPTIC

LED

DRIVER

JABBER

RECEIVE SQUELCH

AMP

∫

LINK DETECT

424813919

TIMER

LED

DRIVERS

V

REF

BIAS

18

15
16

1
28
14

26
25

21

22

23

TxOUT

XMT
RCV

CLSN
JAB

LMON

V

+

IN

VIN–

V

DC

V

REF

V

THADJ

1

ML4663

PIN CONNECTION

ML4663

28-Pin PLCC (Q28)

SQEN/JABD

Rx+

Rx–

LBDIS

V

Tx+

Tx–

TIMER

COL–

C

4 3 2 1 28 27 26

5

6

7

8

9

CC

10

11

12 13 14 15 16 17 18

RTSET

RRSET

COL+

LMON

CLSN

XMT

JAB

RCV

AVCCV

Tx

CC

V

+

IN

25

24

23

22

21

20

19

TxOUT

VIN–

AGND

V

THADJ

V

REF

V

DC

GND

GND

2

PIN DESCRIPTION

ML4663

PIN NAME FUNCTION

1 CLSN Indicates that a collision is taking

place. Active low LED driver, open
collector. Event is extended with
internal timer for visibility.

2 COL+ Gated 10MHz oscillation used to
3 COL– indicate a collision, SQE test, or

jabber. Balanced differential line
driver outputs that meet AUI
specifications.

4C

TIMER

A capacitor from this pin to V

CC

determines the Link Monitor
response time.

5 SQEN/JABD SQE Test Enable, Jabber Disable.

When tied low, SQE test is disabled,
when tied high SQE test is enabled.
When tied to 2.0V both SQE test and
Jabber are disabled.

6 Rx+ Manchester encoded receive data
7 Rx– output to the local device. Balanced

differential line driver outputs that
meet AUI specifications.

8 LBDIS Loopback Disable. When this pin is

tied to VCC, the AUI transmit pair
data is not looped back to the AUI
receive pair, and collision is disabled.
When this pin is tied to GND
(normal operation) or left floating, the
AUI transmit pair data is looped back
to the AUI receiver pair, except
during collision.

9VCC+5 volt power input.

10 Tx+ Balanced differential line receiver
11 Tx– inputs that meet AUI specifications.

These inputs may be transformer or
capacitively coupled. The Tx input
pins are internally DC biased for AC
coupling.

12 RTSET Sets the current driven output of the

transmitter.

13 RRSET A 1% 61.9kΩ resistor tied from this

pin to VCC sets the biasing currents
for internal nodes.

14 LMON Link Monitor “Low Light” LED status

output. This pin is pulled low when
the voltage on the VIN+, VIN– inputs
exceed the minimum threshold set by
the V

pin, and there are

THADJ

transitions on VIN+, VIN– indicating
an idle signal or active data. If either
the voltage on the VIN+, VIN– inputs
fall below the minimum threshold or
transitions cease on VIN+, VIN–,
LMON will go high. Active low LED
driver, open collector.

PIN NAME FUNCTION

15 XMT Indicates that transmission is taking

place. Active low LED driver, open
collector. Event is extended with
internal timer for visibility.

16 RCV Indicates that the transceiver is

receiving a frame from the optical
input. Active low LED driver, open
collector. Event is extended with
internal timer for visibility.

17 VCCTx +5 volt supply for fiber optic LED

driver.

18 TxOUT Fiber optic LED driver output.

19 GND Ground Reference.

20 GND Ground Reference.

21 V

DC

An external capacitor on this pin
integrates an error signal which
nulls the offset of the input
amplifier. If the DC feedback loop is
not being used, this pin should be

22 V

REF

connected to V

A 2.5V reference with respect to

REF

.

GND.

23 V

THADJ

This input pin sets the link monitor
threshold.

24 AGND Analog Filtered Ground.

25 VIN– This input pin should be

capacitively coupled to the input
source or to filtered AVCC. (The
input resistance is approximately

1.3kΩ.)

26 VIN+ This input pin should be

capacitively coupled to the input
source or to filtered AVCC. (The
input resistance is approximately

1.3kΩ.)

27 AV

CC

Analog Filtered +5 volts.

28 JAB Jabber network status LED. When in

the Jabber state, this pin will be low
and the transmitter will be disabled.
In the Jabber “OK” state this pin will
be high. Active low LED, open
collector.

3

ML4663

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are limits beyond which the
life of the integrated circuit may be impaired. All voltages
unless otherwise specified are measured with respect to
ground.

Junction Temperature .............................................. 150°C

Storage Temperature Range ...................... –65°C to 150°C

Lead Temperature (Soldering) .................................. 260°C

Thermal Resistance (θJA)....................................... 68°C/W

Power Supply Voltage Range

V

................................................................... GND –0.3 to 6V

CC

OPERATING CONDITIONS

Input Voltage Range

Digital Inputs

SQEN, LBDIS ....................... GND –0.3 to VCC +0.3V

Tx+, Tx–, VIN+, VIN– ............... GND –0.3 to V

Input Current

CC

+0.3V

Supply Voltage (V

LED on Current ....................................................... 10mA

RRSET .......................................................... 61.9kΩ ± 1%

RTSET ............................................................. 115Ω ± 1%

) ........................................... 5V ± 5%

CC

RRSET, RTSET, JAB, CLSN, XMT, RCV, LMON ...... 60mA

Output Current

TxOUT ................................................................ 70mA

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, TA = Operations Temperature Range, VCC = V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

I

CC

V

I

OUT

V

OL

SQ

Power Supply Current ICC:V
While Transmitting (Note 2)

LED Drivers: V

Transmit Peak Output Current RTSET = 115Ω (Note 4) 44 52 57 mA

Transmit Squelch Voltage Level –300 –250 –200 mV
(Tx+, Tx–)

OL

= 5V, RTSET = 115Ω 220 mA

CC

IOL = 10mA (Note 3) 0.8 V

Tx = 5V ± 5% (Note 1)

CC

V

DO

V

CM

V

DOO

V

SQE

V

LBTH

V

TXCM

V

INCM

V

REF

I

REF

A

V

V

ISR

Differential Output Voltage ±550 ±1200 mV
(Rx±, COL±)

Common Mode Output Voltage 4.0 V

(Rx±, COL±)
Differential Output Voltage ±40 mV

Imbalance (Rx±, COL±)

SQE/JABD SQE Test Disable 0.3 V

Both Disabled 1.5 V
Both Enabled VCC – 0.5 V

LBDIS Threshold Disabled VCC – 0.1 V

Enabled 1 V

Common Mode Voltage 3.5 V
(Tx+, Tx–)

Common Mode Voltage 1.65 V
(VIN+, VIN–)

Reference Voltage 2.30 2.45 2.60 V

V

Output Source Current 5mA

REF

Amplifier Gain 100 V/V

Input Signal Range 2 1600 mV

– 2 V

CC

P–P

4

ML4663

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, TA = Operations Temperature Range, VCC = V

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Tx = 5V ± 5% (Note 1)

CC

V

THADJ

V

OFF

V

N

R

IN

I

TH

V

TH

External Voltage at V
to Set V

TH

THADJ

Input Offset VDC = V

(DC loop inactive) 3 mV

REF

0.5 2.7 V

Input Referred Noise 50MHz BW 25 µV

Input Resistance VIN+, V

Input Bias Current of V

Input Threshold Voltage V

THADJ

THADJ

– 0.8 1.3 2.0 kΩ

IN

–200 10 +200 µA

= V

(Note 5) 5 6 7 mV

REF

H Hysteresis 20 %

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER MIN TYP MAX UNITS

Transmit

F

TXIDF

P

TXDC

t

TXNPW

t

TXODY

t

TXLP

t

TXFPW

t

TXSOI

t

TXSDY

t

TXJ

Receive

F

RXSFT

t

RXODY

t

RXFX

t

RXSDY

t

RXJ

t

AR

t

AF

Transmit Idle Frequency 0.85 1.25 MHz

Transmit Idle Duty Cycle 45 55 %

Transmit Turn-On Pulse Width 20 ns

Transmit Turn-On Delay 200 ns

Transmit Loopback Start-up Delay 500 ns

Transmit Turn-Off Pulse Width 180 ns

Transmit Turn-Off Start of Idle 400 2100 ns

Transmit Steady State Propagation Delay 15 50 ns

Transmit Jitter into 31Ω Load ±1.5 ns

Receive Squelch Frequency Threshold 2.51 4.5 MHz

Receive Turn-On Delay 285 ns

Last Bit Received to Slow Decay Output 230 300 ns

Receive Steady State Propagation Delay 15 50 ns

Receive Jitter ±1.5 ns
Differential Output Rise Time 20% to 80% (Rx±, COL±)4ns
Differential Output Fall Time 20% to 80% (Rx±, COL±)4ns

P–P

5

ML4663

AC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER MIN TYP MAX UNITS

Collision

t

CPSQE

t

SQEXR

F

CLF

P

CLPDC

t

SQEDY

t

SQETD

Jabber and LED Timing

t

JAD

t

JRT

t

JSQE

t

LED

t

LLPH

t

LLCL

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: This does not include the current from the AUI pull-down resistors, or LED status outputs.
Note 3: LED drivers can sink up to 20mA, but V
Note 4: Does not include pre-bias current for fiber optic LED which would typically be 3mA.
Note 5: Threshold for switching from Link Fail to Link Pass (Low Light).

Collision Present to SQE Assert 0 350 ns

Time for SQE to Deactivate After Collision 0 700 ns

Collision Frequency 8.5 11.5 MHz

Collision Pulse Duty Cycle 40 50 60 %

SQE Test Delay (Tx Inactive to SQE) 0.6 1.6 µs
SQE Test Duration 0.5 1.0 1.5 µs

Jabber Activation Delay 20 70 150 ms

Jabber Reset Unjab Time 250 450 750 ms

Delay from Outputs Disabled to Collision Oscillator On 100 ns

RCV, CLSN, XMT On Time 8 16 32 ms
Low Light Present to LMON High 3 5 10 µs

Low Light Present to LMON Low 250 750 ms

will be higher.

OL

6

ML4663

+5V

ALL

0.1µF

115Ω

61.9k

510Ω

RP1

FIBER OPTIC CABLE

2,6,7

3

18

TxOUT

13 12

RRSET RTSET

14

OR

OPTEK

OPC1414

HP HFBR1414

1k

17

CC

TxV

FIBER OPTIC

TRANSMITTER

+5V

8

LBDIS

RF

+V

RF

+V

0.05

4

TIMER

C

ML4663

0.1µF

R17

10Ω

HP HFBR1414

RF

–V

0.1

21

DC

V

FIBER OPTIC CABLE

RF

–V

6

2

1

0.01

OR

OPTEK

OPC1414

26

+

IN

V

OR

OPTEK

OPC2416

HP HFBR2416

4

5

8

0.01

25

–

IN

V

FIBER OPTIC RCVR

73

RF

–V

22

23

REF

V

THADJ

V

RF

–V

RF

+V

RF

–V

0.1
+

4.7µH

4.7

4.7µH

RF

+V

27

RF

–V

0.1µ

+

+

4.7µ

15 16 1 28

XMT RCV CLSN JABLMON

CHASSIS REF

COL–

3

116

AULCP–

1

9

360Ω

CI

AULCP+

AULTX–

2

10

360Ω

AULTX+

3

11

COL+

2

15

2

AULRX–

4

12

Tx–

11

39Ω

13

4

AULRX+

AULPWR+

5

13

0.1µF

AULPWR–

6

14

D0

Tx+

Rx–

7

10

39Ω

7

360Ω

12

10

5

7

360Ω

D1

8

15

Figure 1. ML4663 Schematic Diagram

Rx+
6

9

8

+5V

SQE

5

0.1

RP1

9 19, 20 24

CC

V

510Ω

5KΩ

D1

VR1

Q1

IN OUT

GND

LM340

0.1µ

+

3KΩ

33µ

+5V

7

ML4663

RTSET

=

52mA

I

OUT











115Ω

VCCTx

TxOUT

I

OUT

SYSTEM DESCRIPTION

Figure 1 shows a schematic diagram of the ML4663 in an
internal or external 10BASE-FL MAU. On one side of the
transceiver is the AU interface and the other is the fiber
optic interface. The AU interface is AC coupled when
used in an external transceiver or an internal transceiver.
The AU interface for an external transceiver includes
isolation transformers, some biasing resistors, and a
voltage regulator for power.

The fiber optic side of the transceiver requires an external
fiber optic transmitter and fiber optic receiver. The
transmitter uses a current driven output that directly drives
the fiber optic transmitter. The receive side of the
transceiver accepts the data after passing through a fiber
optic receiver, which consists of a module containing a
pin diode and a transimpedance amplifier.

AU INTERFACE

The AU interface consists of 3 pairs of signals: DO, CI and
DI (Figure 1). The DO pair contains transmit data from the
DTE which is received by the transceiver and sent out
onto the fiber optic cable. The DI pair contains valid data
that has been either received from the fiber optic cable or
looped back from the DO, and output through the DI pair
to the DTE. The CI pair indicates whether a collision has
occurred. It is an output that oscillates at 10MHz if a
collision, Jabber or SQE Test has taken place, otherwise it
remains idle.

When the transceiver is external, these three pairs are AC
coupled through isolation transformers, while an internal
transceiver may be capacitively coupled. Tx+, Tx– is
internally DC biased (shifted up in voltage) for the proper
common mode input voltage.

The two 39Ω 1% resistors (or one 78Ω 1% resistor) tied to

the Tx+ and Tx– pins will provide the proper termination.
The CI and DI pair, which are output from the transceiver

to the AUI cable, require 360Ω pull down resistors when
terminated with a 78Ω load. However on a DTE card, CI
and DI do not need 78Ω terminating resistors. This also

means that the pull down resistors on CI and DI can be

1kΩ or greater depending upon the particular Manchester

encoder/decoder chip used. Using higher value pull down
resistors as in a DTE card will save power. Refer to
Application Note 13 for a more detailed explanation of
the AUI pull-down resistors.

The AUI drivers are capable of driving the full 50 meters
of cable length and have a rise and fall time of typically
4ns. In the idle state, the outputs go to the same voltage to
prevent DC standing current in the isolation transformers.

Before data will be transmitted onto the fiber optic cable
from the AUI interface, it must exceed the squelch
requirements for the DO pair. The Tx squelch circuit
serves the function of preventing any noise from being
transmitted onto the fiber. This circuit rejects signals with
pulse widths less than typically 20ns (negative going), or
with levels less than –250mV. Once Tx squelch circuit has
unsquelched, it looks for the start of idle signal to turn on
the squelch circuit again. The transmitter turns on the
squelch again when it receives an input signal at Tx+,
Tx– that is more positive than –250mV for more than
approximately 180ns.

At the start of a packet transmission, no more than 2 bits
are received from the DO circuit, and are not transmitted
onto the fiber optic cable. The difference between start-up
delays (bit loss plus steady-state propagation delay) for

any two packets that are separated by 9.6µs or less will

not exceed 200ns.

FIBER OPTIC LED DRIVER

The output stage of the transmitter is a current mode
switch which develops the output light by sinking current
through the LED into the TxOUT pin. Once the current
requirement for the LED is determined, the RTSET resistor
is selected. The following equation is used to select the
correct RTSET resistor:

The transmitter enters the idle state when it detects start of
idle on Tx+ and Tx– input pins. After detection, the
transmitter switches to a 1MHz output idle signal.

The output current is switched through the TxOUT pin
during the on cycle and the VCCTx pin during the off cycle
as shown in figure 2. Since the sum of the current in these
two pins is constant, VCCTx should be connected as close
as possible to the VCC connection for the LED.

If not driving an optical LED directly, a differential output
can be generated by tying resistors from VCCTx and
TxOUT to VCC as shown in figure 3. The minimum
voltage on these two pins should not be less than
VCC – 2V.

TRANSMISSION

The transmit function consists of detecting the presence of
data from the AUI DO input (Tx+, Tx–) and driving that
data onto the fiber optic LED transmitter. A positive signal
on the Tx+ lead relative to the Tx– lead of the DO circuit
will result in no current, hence the fiber optic LED is in a
low light condition. When Tx+ is more negative than Tx–,
the ML4663 will sink current into the chip and the fiber
optic LED will light up.

8

Figure 2. Fiber Optic LED Driver Structure.

ML4663

V

CC

VCCTx

51Ω

51Ω

51Ω

TxOUT

RTSET = 560Ω
I

= 15.9mA

OUT

ECL

Figure 3. Converting Optical LED Driver Output to

Differential ECL.

RECEPTION

The input to the transceiver comes from a fiber optic
receiver (Figure 1). At the start of packet reception no
more than 2.7 bits are received from the fiber cable, and
are not transmitted onto the DI circuit. The receive
squelch will reject frequencies lower than 2.51MHz.

While in the unsquelch state, the receive squelch circuit
looks for the start of idle signal at the end of the packet.
Start of idle occurs when the input signal remains idle for
more than 160ns. When start of idle is detected, the
receive squelch circuit returns to the squelch state and the
start of idle signal is output on the DI circuit (Rx+, Rx–).

COLLISION

Whenever the receiver and the transmitter are active at
the same time the chip will activate the collision output,
except when loopback is disabled (LBDIS = VCC). The
collision output is a differential square wave matching the

AUI specifications and capable of driving a 78Ω load. The
frequency of the square wave is 10MHz ± 15% with a 60/

40 to 40/60 duty cycle. The collision oscillator also is
activated during SQE Test and Jabber.

LOOPBACK

The loopback function emulates a 10BASE-T transceiver
whereby the transmit data sent by the DTE is looped back
over the AUI receive pair. Some LAN controllers use this
loopback information to determine whether a MAU is
connected by monitoring the carrier sense while
transmitting. The software can use this loopback
information to determine whether a MAU is connected to
the DTE by checking the status of carrier sense after each
packet transmission.

When data is received by the chip while transmitting, a
collision condition exits. This will cause the collision
oscillator to turn on and the data on the DI pair will
follow VIN+, VIN–. After a collision is detected, the
collision oscillator will remain on until either DO or
VIN+, VIN– go idle.

Loopback can be disabled by strapping LBDIS to VCC.
In this mode the chip operates as a full duplex transmitter
and receiver, and collision detection is disabled. A
loopback through the transceiver can be accomplished by
tying the fiber transmitter to the receiver.

SQE TEST FUNCTION (SIGNAL QUALITY ERROR)

The SQE test function allows the DTE to determine
whether the collision detect circuitry is functional. After
each transmission, during the inter packet gap time, the

collision oscillator will be activated for typically 1µs. The

SQE test will not be activated if the chip is in the low light
state, or the jabber on state.

For SQE to operate, the SQEN pin must be tied to VCC.
This allows the MAU to be interfaced to a DTE. The SQE
test can be disabled by tying the SQEN pin to ground, for
a repeater interface.

JABBER FUNCTION REQUIREMENTS

The Jabber function prevents a babbling transmitter from
bringing down the network. Within the transceiver is a
Jabber timer that starts at the beginning of each
transmission and resets at the end of each transmission. If
the transmission last longer than 20ms the Jabber logic
disables the transmitter and turns on the collision signal
COL+, COL–. When Tx+ and Tx– finally go idle, a second
timer measures 0.5 seconds of idle time before the
transmitter is enabled and collision is turned off. Even
though the transmitter is disabled during Jabber, the 1MHz
idle signal is still transmitted.

LED DRIVERS

The ML4663 has five LED drivers. The LED driver pins are
active low, and the LEDs are normally off (except for
LMON). The LEDs are tied to their respective pins through

a 500Ω resistor to 5V.

The XMT, RCV and CLSN pins have pulse stretchers on
them which enables the LEDs to be visible. When
transmission or reception occurs, the LED XMT, RCV or
CLSN status pins will activate low for several
milliseconds. If another transmit, receive or collision
conditions occurs before the timer expires, the LED timer
will reset and restart the timing. Therefore rapid events
will leave the LEDs continuously on. The JAB and LMON
LEDs do not have pulse stretchers on them since their
conditions occur long enough for the eye to see.

LOW LIGHT CONDITION

The LMON LED output is used to indicate a low light
condition. LMON is activated low when both the receive
power exceeds the Link Monitor threshold and there are
transitions on VIN+, V

– less than 3µs apart. If either one

IN

of these conditions do not exist, LMON will go high.

INPUT AMPLIFIER

The VIN+, VIN– input signal is fed into a limiting amplifier

with a gain of about 100 and input resistance of 1.3kΩ.

Maximum sensitivity is achieved through the use of a DC
restoration feedback loop and AC coupling the input.
When AC coupled, the input DC bias voltage is set by an
on-chip network at about 1.7V. These coupling capacitors,
in conjunction with the input impedance of the amplifier,
establish a high pass filter with 3dB corner frequency, fL,
at

1

=

f

L

2 300C

π1

(1)

9

ML4663

Since the amplifier has a differential input, two capacitors
of equal value are required. If the signal driving the input
is single ended, one of the coupling capacitors can be tied
to AVCC (Figure 1).

The internal amplifier has a lowpass filter built-in to band
limit the input signal which in turn will improve the signal
to noise ratio.

Although the input is AC coupled, the offset voltage

within

the amplifier will be present at the amplifier’s output. This
is represented by VOS in Figure 4. In order to reduce this
error a DC feedback loop is incorporated. This negative
feedback loop nulls the offset voltage, forcing VOS to be
zero. Although the capacitor on VDC is non-critical, the
pole it creates can effect the stability of the feedback loop.
To avoid stability problems, the value of this capacitor
should be at least 10 times larger than the input coupling
capacitors.

V

+

OUT

V

OS

–

V

OUT

Figure 4.

The comparator is a high-speed, differential zero crossing
detector that slices and accurately digitizes the receive
signal. The output of the comparator is fed in parallel into
both the receive squelch circuit and the loopback MUX.

LINK DETECT CIRCUIT AND LOW LIGHT

The link detect circuit monitors the input signal and
determines when the input falls below a preset voltage
level. When the input falls below a preset voltage, the
ML4663 goes into the Low Light state. In the Low Light
state the transmitter is disabled, but continues sending the
1MHz idle signal, the loopback is disabled, the receiver is
disabled, and the LMON LED pin goes to high shutting off
the LMON LED. To return to the Link Pass state, the
optical receiver power must be 20% higher than the shut­off state. This built-in hysteresis adds stability to the Link
Monitor circuit. Once the receiver power threshold is
exceeded, the ML4663 waits 250ms to 750ms, then
checks to see that Tx+. Tx– is idle and no data is being
received before re-enabling the transmitter, receiver,
loopback circuit, and lighting up the LMON LED.

The V

pin is used to adjust the sensitivity of the

THADJ

receiver. The ML4663 is capable of exceeding the
10BASE-FL specifications for sensitivity. The sensitivity is
dependent on the layout of the PC board. A good low
noise layout will exceed the 10BASE-FL specifications,
while a poor layout will fail to meet the sensitivity and
BER spec.

The threshold generator shifts the reference voltage at
V

through a circuit which has a temperature

THADJ

coefficient matching that of the limiting amplifier. The
relationship between the V

and the VTH (the peak to

THADJ

peak input threshold) is:

V

In a 10BASE-FL receiver there must be less than 1 x 10

THADJ

= 408V

TH

(2)

–10

bit errors at a receive power level of –32.5dBm average.
One procedure to determine the sensitivity of a receiver is
to start at the lowest optical power level and gradually
increase the optical power until the BER is met. In this
case the Link Detect circuit must not disable the receiver
(i.e. V
sensitivity of the receiver is determined, V

should be tied to Ground). Once the

THADJ

THADJ

can be set
just above the power level that meets the BER
specification. This way the receiver will shut-off before the
BER is exceeded.

For 10BASE-FL V

can be tied directly to V

THADJ

REF

.
However if greater sensitivity is required the circuit in
figure 5 can be used to adjust the V
V

is tied to V

REF

, it is a good idea to layout a board

THADJ

voltage. Even if

THADJ

with these two resistors available. This will allow potential
future adjustments without board revisions.

The response time of the Link Detect circuit is set by the
C

pin. Starting from the link off state the link can be

TIMER

switched on if the input exceeds the set threshold for a
time given by:

TIMER

× 0.7V

A700µ

(3)

C

=

T

To switch the link from on to off, the above time will be

doubled. A value of 0.05µF will meet to 10BASE-FL

specifications.

R2

R1

VREF

VTHADJ

REF

THRESH

GEN

10

Figure 5.

TIMING DIAGRAMS

Tx+

Tx–

TxOUT

t

TXLP

t

TXODY

t

TXNPW

VALID DATA

t

TXSDY

VALIDIDLE IDLEDATA

t

TXFPW

t

TXSOI

F

TXIDF

ML4663

1

Rx+

Rx–

VIN+

V

IN

Rx+

Rx–

VALID DATA

Figure 6. Transmit and Loopback Timing

–

t

ROXDY

VALID DATA

t

RXSDY

VALID DATA

t

t

AR

t

AF

RXFX

Figure 7. Receive Timing

Tx+

Tx–

VIN+

V

IN

COL+

COL–

Rx+

Rx–

VALID DATA

–

Tx Tx Rx RxRx

VALID DATA

t

CPSQE

CS0

Figure 8. Collision Timing

11

ML4663

TIMING DIAGRAMS

+

V

IN

–

V

IN

VALID DATA

Tx+

Tx–

COL+

COL–

VIN+

V

IN

Tx+

Tx–

COL+

COL–

Rx+

Rx–

VALID DATA

t

CPSQE

CS0

Figure 9. Collision Timing

–

VALID DATA

t

SQEXR

CS0

Rx Rx Rx Tx Tx Tx

Tx+

Tx–

V

IN

V

IN

COL+

COL–

Rx+

Rx–

Figure 10. Collision Timing

+

–

VALID DATA

t

SQEXR

CS0

RxIN RxIN RxIN RxIN RxIN

Figure 11. Collision Timing

12

TIMING DIAGRAMS

COL+

COL–

1

F

CLF

Figure 12. Collision Timing

ML4663

Tx+

Tx –

TxOUT

COL+

COL–

Tx+

Tx–

COL+

COL–

VALID DATA

Figure 13. SQE Timing

VALID DATA

t

JAD

VALID

DATA

t

SQEDY

t

JSQE

CS0

t

SQETD

CS0

t

JRT

Tx+

Tx–

XMT

Figure 14. Jabber Timing

t

LED

Figure 15. LED Timing

13

ML4663

TIMING DIAGRAMS

VIN+

–

V

IN

RCV

VIN+

V

–

IN

Figure 16. LED Timing

t

LED

LMON

t

LLPH

Figure 17. LED Timing

t

LLCL

14

ML4663

PHYSICAL DIMENSIONS inches (millimeters)

Package: Q28

28-Pin PLCC

0.485 - 0.495

(12.32 - 12.57)

0.450 - 0.456

(11.43 - 11.58)

1

0.042 - 0.056
(1.07 - 1.42)

0.025 - 0.045
(0.63 - 1.14)

(RADIUS)

0.042 - 0.048
(1.07 - 1.22)

8

0.050 BSC
(1.27 BSC)

0.026 - 0.032
(0.66 - 0.81)

0.013 - 0.021
(0.33 - 0.53)

PIN 1 ID

15

SEATING PLANE

0.450 - 0.456

22

(11.43 - 11.58)

0.165 - 0.180
(4.06 - 4.57)

0.485 - 0.495

(12.32 - 12.57)

0.148 - 0.156
(3.76 - 3.96)

0.009 - 0.011
(0.23 - 0.28)

0.099 - 0.110
(2.51 - 2.79)

0.300 BSC
(7.62 BSC)

0.390 - 0.430
(9.90 - 10.92)

ORDERING INFORMATION

PART NUMBER TEMPERATURE PACKAGE

ML4663CQ 0°C to 70°C 28-Pin PLCC (Q28)

© Micro Linear 1997 is a registered trademark of Micro Linear Corporation
Products described in this document may be covered by one or more of the following patents, U.S.: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940;
5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; Japan: 2598946. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design.
Micro Linear does not assume any liability arising out of the application or use of any product described herein,
neither does it convey any license under its patent right nor the rights of others. The circuits contained in this
data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to
whether the illustrated circuits infringe any intellectual property rights of others, and will accept no responsibility
or liability for use of any application herein. The customer is urged to consult with appropriate legal counsel
before deciding on a particular application.

15

2092 Concourse Drive

San Jose, CA 95131

Tel: [phone]

Fax: [phone]

DS4663-01