Datasheet ML4425IP, ML4425CS, ML4425CH, ML4425IS, ML4425IH Datasheet (Micro Linear Corporation)

July 2000

ML4425

Sensorless BLDC Motor Controller

GENERAL DESCRIPTION

The ML4425 PWM motor controller provides all of the
functions necessary for starting and controlling the speed
of delta or wye wound Brushless DC (BLDC) motors
without Hall Effect sensors. Back EMF voltage is sensed
from the motor windings to determine the proper
commutation phase sequence using a PLL. This patented
sensing technique will commutate a wide range of 3­Phase BLDC motors and is insensitive to PWM noise and
motor snubbing circuitry.

The ML4425 limits the motor current using a constant off­time PWM control loop. The velocity loop is controlled
with an onboard amplifier. The ML4425 has circuitry to
ensure that there is no shoot-through in directly driven
external power MOSFETs.

The timing of the start-up sequence is determined by the
selection of three timing capacitors. This allows
optimization for a wide range of motors and loads.

BLOCK DIAGRAM

FB A

22

FB B

23

FB C

24

BACK

EMF

SAMPLER

(Pin Configuration Shown for 28 Pin Version)

750nA

17

C

DD

1.5V

AT

750nA

–
+

V

19

V

DD

1.5V

C

RT

FEATURES

■ Stand-alone operation

■ Motor starts and stops with power to IC

■ On-board start sequence: Align ® Ramp ® Set Speed

■ Patented Back-EMF commutation technique provides

jitterless torque for minimum “spin-up” time

■ Onboard speed control loop

■ PLL used for commutation provides noise immunity

from PWM spikes, compared to noise sensitive zero
crossing technique

■ PWM control for maximum efficiency

■ Direct FET drive for 12V motors; drives high voltage

motors with IC buffers from IR, IXYS, Harris, Power
Integrations, Siliconix, etc.

21

C

–
+

500nA

RR

20

SPEED

FB

V

DD

15 16

C

VCO

VOLTAGE

CONTROLLED

OSCILLATOR

R

VCO

VCO/TACH

13

8

SPEED SET

5

SPEED COMP

C

T

6

I

SENSE

1

I

LIMIT

12

1.7V

+
–

3.9V

1.7V

20kHz

–

+

16kΩ

VCO
OUT

VCO
OUT

× 5

V

REF

–
+

8kΩ

R

A

D

LIMIT

B

COMMUTATION
STATE MACHINE

C

1.4V

BRAKE

25

HA

2

HB

GATING

LOGIC

–
+

V

DD

4kΩ

UVLO

REFERENCE

V

DD

14

GND27R

28

&
OUTPUT
DRIVERS

REF

UV FAULT

7

3

HC

4

LA

9

LB

10

LC

11

18

V

REF

F

E

I

1-SHOT

C

IOS

26

1

ML4425

PIN CONFIGURATION

ML4425

28-Pin Narrow PDIP (P28N)

28-Pin SOIC (S28)

I

SENSE

HA

HB

HC

SPEED COMP

C

V

REF

SPEED SET

LA

LC

I

LIMIT

VCO/TACH

V

DD

T

LB

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TOP VIEW

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GND

R

REF

C

IOS

BRAKE

FB C

FB B

FB A

C

RR

SPEED FB

C

RT

UV FAULT

C

AT

R

VCO

C

VCO

H3

NC

SPEED COMP

C

V

REF

SPEED SET

LA

LB

ML4425

32-Pin TQFP (H32-7)

IOS

NC

DD

V

GND

NC

REF

R

NC

C

BRAKE

24

23

22

21

20

19

18

17

VCORVCO

C

FB C

FB B

FB A

C

RR

SPEED FB

C

RT

UV FAULT

C

AT

SENSE

HBHAI

32 31 30 29 28 27 26 25

1

2

3

4

T

5

6

7

8

9 10111213141516

LC

LIMIT

I

VCO/TACH

TOP VIEW

2

ML4425

PIN DESCRIPTION

PIN NAME FUNCTION

1(30) I

SENSE

(Pin number in parenthesis is for TQFP package)

Motor current sense input. When
I

exceeds 0.2 ´ I

SENSE

LIMIT,

the
output drivers LA, LB, and LC are
shut off for a fixed time
determined by C

IOS

2(31) HA Active low output driver for the

phase A high-side switch

3(32) HB Active low output driver for the

phase B high-side switch

4(1) HC Active low output driver for the

phase C high-side switch

5(3) SPEED COMP Speed control loop compensation is

set by a series resistor and capacitor
from SPEED COMP to GND

6(4) C

T

A capacitor from CT to GND sets
the PWM oscillator frequency

7(5) V

REF

6.9V reference voltage output

8(6) SPEED SET Speed loop input which ranges

from 0 (stopped) to V

REF

(maximum speed)

9(7) LA Active high output driver for the

phase A low-side switch

PIN NAME FUNCTION

17(17) C

AT

A capacitor to GND sets the time
that the controller stays in the
align mode

18(18) UV FAULT This output goes low when V

DD

drops below the UVLO threshold,
and indicates that all output
drivers have been disabled

19(19) C

RT

A capacitor to GND sets the time
that the controller stays in the
ramp mode

20(20) SPEED FB Output of the back-EMF sampling

circuit and input to the VCO. An
RC network connected to SPEED
FB sets the compensation for the
PLL loop formed by the back-EMF
sampling circuit, the VCO, and
the commutation state machine

21(21) C

RR

A capacitor to between C

RR

and
SPEED FB sets the ramp rate
(acceleration) of the motor when
the controller is in ramp mode

22(22) FB A The motor feedback voltage from

phase A is monitored through a
resistor divider for back-EMF
sensing at this pin

10(8) LB Active high output driver for the

phase B low-side switch

11(9) LC Active high output driver for the

phase C low-side switch

12(10) I

LIMIT

Voltage on this pin sets the I
threshold voltage at 0.2 ´ I

LIMIT

SENSE

leaving this pin unconnected
selects an internally set threshold

13(11) VCO/TACH This TTL level output corresponds

to the signal used to clock the
commutation state machine. The
output frequency is proportional to
the motor speed when the back­EMF sensing loop is locked onto
the rotor position

14(12) V

15(15) C

DD

VCO

12V power supply input

A capacitor to GND sets the
voltage-to-frequency ratio of the
VCO

16(16) R

VCO

An resistor to GND sets up a
current proportional to the input
voltage of the VCO

23(23) FB B The motor feedback voltage from

phase B is monitored through a
resistor divider for back-EMF
sensing at this pin

24(24) FB C The motor feedback voltage from

phase C is monitored through a

,

resistor divider for back-EMF
sensing at this pin

25(25) BRAKE A logic low input activates motor

braking by shutting off the high­side output drivers and turning on
the low-side output drivers

26(26) C

IOS

A capacitor to GND sets the time
that the low-side output drivers
remain off after I

SENSE

exceeds its

threshold

27(27) R

REF

An 137kW resistor to GND sets a
current proportional to V

REF

that is
used to set all the internal bias
currents except for the VCO

28(28) GND Signal and power ground

3

ML4425

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.

Thermal Resistance (qJA)

28-Pin Narrow PDIP ......................................... 48ºC/W

28-Pin SOIC ..................................................... 75ºC/W

32-Pin TQFP ..................................................... 80ºC/W

VDD.......................................................................... 14V

Logic Inputs (, SPEED FB, BRAKE) ..........GND - 0.3 to 7V

OPERATING CONDITIONS

All Other Inputs and Outputs .. GND -0.3V to VDD + 0.3V

Output Current (LA, LB, LC, HA, HB, HC)............ ±50mA

Junction Temperature.............................................. 150ºC

Storage Temperature Range ...................... –65ºC to 150ºC

Lead Temperature (Soldering 10 sec.) ..................... 260ºC

Temperature Range

ML4425CX................................................. 0ºC to 70ºC

ML4425IX ...............................................–40ºC to 85ºC

VDD......................................................... 10.8V to 13.2V

ELECTRICAL CHARACTERISTICS

Unless otherwise specified,V
TA = Operating Temperature Range (Notes 1, 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

REFERENCE

V

PWM OSCILLATOR

Total Variation Line, Temp 6.5 6.9 7.5 V

REF

Total Variation CT = 1nF 28 kHz

= 12V ± 10%, R

DD

SENSE

= 1W, C

VCO

= 10nF, C

= 100pF, R

IOS

= 137kW,

REF

Ramp Peak 3.9 V

Ramp Valley 1.7 V

Ramp Charging Current ? µA

SPEED CONTROL LOOP

SPEED SET Input Voltage Range 0 V

SPEED FB Input Voltage Range 0 V

SPEED COMP Output Current ±5 ±20 µA

SPEED SET Error Amp Transconductance V

START-UP

CAT Charging Current C Suffix 0.68 0.98 µA

CAT Threshold Voltage 1.4 1.7 V

CRT Charging Current C Suffix 0.68 0.98 µA

CRT Threshold Voltage 1.4 1.7 V

VOLTAGE CONTROLLED OSCILLATOR

Frequency Range R

Frequency vs. SPEED FB R

CURRENT LIMIT

REF

REF

SPEED SET

VCO

VCO

= xV, V

= 5V, SPEED FB = 6V 1.5 1.85 2.2 kHz
= 5V, 0.5V £ SPEED FB £ 7V 300 Hz/V

SPEED FB

= yV 144 µ

I Suffix 0.5 1.1 µA

I Suffix 0.5 1.1 µA

V

V

W

I

Gain V(I

SENSE

One Shot OFF-Time C

) £ 2.5V 4.5 5.0 5.5 V/V

LIMIT

= 100pF C Suffix 9 18 µs

IOS

I Suffix 9 2 0 µs

4

ML4425

ELECTRICAL CHARACTERISTICS

(Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

LOGIC INPUTS (

V

IH

V

IL

I

IH

I

IL

LOGIC OUTPUTS (VCO/TACH,

BRAKE

) (Note 3)

Input High Voltage 2 V

Input Low Voltage 0.8 V

Input High Current VIH = 2.4V 2.4 mA

Input Low Current VIL = 0.4V 2.9 mA

UV FAULT

VCO/TACH Output High Voltage I

VCO/TACH Output Low Voltage I

UV FAULT Output High Voltage I

) (Note 3)

= –100µA 2.2 V

OUT

= 400µA 0.6 V

OUT

= –10µA C Suffix 3.4 4.5 5.4 V

OUT

I Suffix 3.2 5.6 V

UV FAULT Output Low Voltage I

= 400µA 0.6 V

OUT

BACK-EMF SAMPLER

SPEED FB Align Mode Voltage 125 250 mV

SPEED FB Ramp Mode Current C Suffix 500 720 nA

I Suffix 50 0 750 nA

SPEED FB Run Mode Current State A, C

OUTPUT DRIVERS

High Side Driver Output Low Current VHX = 2V 0.5 1.2 mA

High Side Driver Output High Voltage IHX = –10µA VCC – 1.3 V

Low Side Driver Output Low Voltage ILX = 1mA 0.2 0.7 V

Low Side Driver Output High Voltage V(I

Phase C Cross-conduction Lockout Threshold VDD – 3.0 V

SUPPLY

I

DD

VDD Current 32 50 mA

UVLO Threshold C Suffix 8.8 9.5 10.2 V

UVLO Hysteresis 150 mV

= 5V, C Suffix 30 90 µA

RT

V

= VDD/3 I Suffix 2 7 90 µA

PHB

State A, C

State A, C

V

PHB

SENSE

= 5V, V

RT

= 5V, C Suffix –90 –30 µA

RT

= VDD/2 –15 15 µA

PHB

= 2´VDD/3 I Suffix –90 –27 µA

) = 0V C Suffix VDD – 2.2 V

I Suffix VDD – 2.9 V

I Suffix 8.6 10.3 V

Note 1:
Note 2:
Note 3:

Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
For explanation of states, see Figure 4 and Table 1.
The BRAKE and UV FAULT pins each have an internal 4kW resistor to the internal reference.

5

ML4425

FUNCTIONAL DESCRIPTION

GENERAL

The ML4425 provides all the circuitry for sensorless speed
control of 3-phase Brushless DC (BLDC) motors. Controller
functions include start-up circuitry, back-EMF
commutation control, Pulse Width Modulation (PWM)
speed control, fixed OFF-time current limiting, braking,
and undervoltage protection.

The start-up circuitry aligns the motor to a known position,
then ramps up the motor speed to generate a back-EMF
signal. A back-EMF sampling circuit controls
commutation timing by forming a Phase Locked Loop
(PLL). The commutation control circuitry also outputs a
speed feedback (SPEED FB) signal used in the speed
control loop. The speed control loop consists of an error
amplifier and PWM comparator that produce a PWM duty
cycle for speed regulation. Motor current is limited by a
fixed OFF-time PWM shutdown comparator that is
controlled by an external sense resistor. Commutation
control, PWM speed control, and current limiting are
combined to produce the output driver signals. Six output
drivers are used to provide gating signals to an external 3
phase bridge power stage sized for the BLDC motor
voltage and current requirements. Additional functions
include a braking function and undervoltage protection
circuit to shut down the output drivers in the event of a
low voltage condition on VDD of the ML4425.

COMPONENT SELECTION

If one or more of the above values is not known, it is still
possible to pick components for the ML4425, but some
experimentation may be necessary to determine the
optimal values. All quantities are in SI units unless
otherwise specified. The following formulas should be
considered as a starting point for optimization. All
calculations for capacitors and resistors should be used as
the first approximation for selecting the closest standard
value.

POWER SUPPLY AND REFERENCE

The supply voltage (VDD) is nominally 12V ±10%. A
100nF bypass capacitor to ground should be placed as
close as possible to VDD. A 6.9V voltage reference output
(V

) is provided to set the speed command and current

REF

limit of the ML4425. A 137kW from R

to GND is

REF

required to set up a reference current for internal
functions.

OUTPUT DRIVERS

The output drivers LA, LB, LC, HA, HB, and HC provide
totem pole output drive signals for a 3 phase bridge power
stage. All control functions in the ML4425 translate to
outputs at these pins. LA, LB, and LC provide the low-side
drive signals for phases A, B, and C of the 3 phase power
stage and are 12V active high signals. HA, HB, and HC
provide the high-side signals and are 12V active low
signals.

Selecting external components for the ML4425 requires
calculations based on the motor’s electrical and
mechanical parameters. The following is a list of the
motor parameters needed for these calculations :

DC motor supply voltage – V

Maximum operating current – I

MOTOR

MAX

(V)

(A)

Number of magnetic poles – N

Back EMF constant – Ke (V-s/Rad)

Motor torque constant – Kt (Nm/A) (Kt = Ke in SI units)

Maximum speed of operation RPM

MAX

(RPM)

Moment of inertia of the motor and load – J (Kg-m2)

Viscous damping factor of the motor and load – z

DC SUPPLY
CAPACITOR

HA

LA

V

MOTOR

12V

HB

MOTOR

PHASE A

LB

R

SENSE

HC

MOTOR
PHASE B

LC

MOTOR

PHASE C

Figure 1. Using R

in a 3-Phase 12V Power Stage

SENSE

6

ML4425

(a)

0V

460mV

(b)

FUNCTIONAL DESCRIPTION

(Continued)

CURRENT LIMITING IN THE POWER STAGE

The current sense resistor (R

) shown in Figure 1

SENSE

regulates the maximum current in the power stage and
the BLDC motor. Current regulation is accomplished by
shutting off the output drivers LA, LB, and LC for a fixed
amount of time if the voltage across R

exceeds the

SENSE

current limit threshold.

I

LIMIT

The voltage on the I

pin sets the current limit

LIMIT

threshold. The ML4425 has an internal voltage divider
from V

that sets a default current limit threshold of

REF

2.3V (see Figure 2). An external voltage divider
referenced to V
I

setting. The external divider should have at least 10

LIMIT

can be used to override the default

REF

times the current flow of the internal divider.

R

SENSE

The function of R

is to provide a voltage

SENSE

proportional to the motor current to set the current limit
trip point. The default trip voltage across R
460mV, set by the internal I

divider ratio. The current

LIMIT

SENSE

is

sense resistor should be a low inductance resistor such as
a carbon composition. For resistors in the milliohms range,
wire-wound resistors tend to have low values of
inductance. R
dissipation (I

should be sized to handle the power

SENSE

2

MAX

´ R

SENSE

).

FROM

R

SENSE

I

SENSE

× 5

V

V

REF

I

LIMIT

REF

16kΩ

8kΩ

2.9V
0V

–
+

STOP
START

C

IOS

Figure 2. Current Sense Circuitry

PWM

ON/OFF

SRQ

Q

30µA

I

Filter

SENSE

The I

RC lowpass filter is placed in series with the

SENSE

current sense signal as shown in Figure 2. The purpose of
this filter is to remove the diode reverse recovery
shootthrough current. This current causes a voltage spike
on the leading edge of the current sense signal which
may falsely trigger the current limit. The current sense
voltage waveform is shown before and after filtering in
Figure 3. The recommended starting values for this circuit
are R = 1kW and C = 330pF. This gives a time constant of
330ns, and will filter out spikes of shorter duration. C can
be increased to as much as 2.2nF, but should not exceed
a time constant of more than a few microseconds.

C

IOS

When I

exceeds 0.2 ´ I

SENSE

, the current limit one-

LIMIT

shot is activated, turning off LA, LB, and LC for a fixed
amount of time (t
capacitance connected to C

OFF

). t

is set by the amount of

OFF

IOS

. C

IOS

is usually set for a
fixed off time equal to or less than the PWM period. For a
25kHz PWM frequency, the PWM period is 40µs; t
should be between 20µs and 40µs. The lower limit of t

OFF

OFF

is dictated by the minimum on time of the power stage; a
safe approximation is 5µs or less. The equation for finding
the C

capacitance value is as follows:

IOS

tA

 50

OS

OFF

=

V

24m.

C

(1)

Figure 3. Current Sense Resistor Waveforms

(a) Without Filtering, and (b) With Filtering

COMMUTATION CONTROL

A 3-phase BLDC motor requires electronic commutation
to achieve rotational motion. Electronic commutation
requires the switching on and off of the power switches of
a 3-phase half bridge. For torque production to be
achieved in one direction, the commutation is dictated by
the rotor position. Electronic commutation in the ML4425
is achieved by turning on and off, in the proper sequence,
one N output from one phase and one P output from
another phase. There are six combinations of N and P
outputs (six switching states) that constitute a full
commutation cycle. These combinations are illustrated in
Table 1 and Figure 4, and are labeled states A through F.
This sequence is programmed into the commutation state
machine. Clocking of the commutation state machine is
provided by a voltage controlled oscillator (VCO).

7

ML4425

OUTPUTS INPUT

STATE LA LB LC HA HB HC SAMPLING

R OFF ON OFF ON OFF ON N/A
A OFF OFF ON ON OFF OFF FB B
B OFF OFF ON OFF ON OFF FB A
C ON OFF OFF OFF ON OFF FB C
D ON OFF OFF OFF OFF ON FB B

E OFF ON OFF OFF OFF ON FB A
F OFF ON OFF ON OFF OFF FB C

Table 1. Commutation State Functions

ABCDEFABCDEF

HA

HIGH

SIDE

DRIVE

OUTPUTS

HB

HC

LA

LOW

SIDE

DRIVE

LB

OUTPUTS

LC

Figure 4. Output Commutation Sequence Timing Diagram

Cycle 1 - Full Commutation, Cycle 2 - Commutation with 50% PWM Duty Cycle

FUNCTIONAL DESCRIPTION

(Continued)

Voltage Controlled Oscillator (VCO)

The VCO provides a TTL compatible clock output on the
VCO/TACH pin proportional to the VCO input voltage at
the SPEED FB pin. The proportion of frequency to voltage
(VCO constant, Kv) is set by an 80.6kW resistor on R
and a capacitor on C

as shown in Figure 5. R

VCO

VCO

VCO

sets
up a current proportional the VCO input voltage at SPEED
FB. This current is used to charge and discharge C

VCO

between the threshold voltages of 2.3V and 4.3V. The
resulting triangle wave on C

corresponds to the clock

VCO

on VCO. Kv should be set so that the VCO output

frequency corresponds to the maximum commutation
frequency or maximum motor speed when the VCO input
is equal to or slightly less than V

REF

. C

is calculated

VCO

using the following equation:

Hz Farad



-

6

NSPEED



V

(2)

MAX

C

65 3101 10

=

VCO

V



..

Hz

005

.

RPM

The closest standard value that is equal to or less than the
calculated C

should be used.

VCO

8

ML4425

FUNCTIONAL DESCRIPTION

(Continued)

The maximum frequency on the VCO pin is found by:

fNRPM

=005.

MAX MAX

(3)

The voltage at the VCO/TACH pin is equal to the rotor
speed. The voltage at SPEED FB is controlled by the back
EMF sampler.

BACK EMF SAMPLER

The input to the voltage controlled oscillator is the back
EMF sampler. The back EMF sense pins FB A, FB B, and
FB C inputs to the back EMF sampler require a signal
from the motor phase leads that is below the VDD of the
ML4425. The phase sense input impedance is 8kW. This
requires a series resistor RES1 from the motor phase lead
as shown in Figure 6 based on the following equation:

RES V V V

1 670 10=-

W

/

16

MOTOR

(4)

The back EMF sampler takes the motor phase voltages
divided down to signals that are less than VDD (12V
nominal) and calculates the neutral point of the motor by
the following equation:

FROM

BACK EMF

SAMPLER

& RAMP

GENERATOR

C

VCO

VCO/TACH

RESET

(FROM CAT)

4.3V

2.3V

5V

0V

C

VCO

SPEEDFBC

VCO

VOLTAGE

CONTROLLED

OSCILLATOR

R

VCO

R

VCO

VCO/TACH

PH PH PH

Neutral

++123

=

3

(5)

This allows the ML4425 to compare the back EMF signal
to the motor's neutral point without the need for bringing
out an extra wire on a WYE wound motor. For DELTA
wound motors there is no physical neutral to bring out, so
this reference point must be calculated in any case.

The back EMF sampler measures the motor phase that is
not driven (i.e. if LA and HB are on, then phase A is
driven low, phase B is driven high, and phase C is

MOTOR ΦA

MOTOR ΦB

MOTOR ΦC

RES1

RES2

RES3

FB A

FB B

FB C

4kΩ

4kΩ

4kΩ

sampled). The sampled phase provides a back EMF signal
that is compared against the neutral of the motor. The
sampler is controlled by the commutation state machine.
The sampled back EMF is compared to the neutral through
an error amplifier. The output of the error amplifier outputs
a charging or discharging current to SPEED FB, which
provides the control voltage to the VCO.

NEUTRAL

SIMULATOR

ΦA + ΦB + ΦC

6

MULTIPLEXER

Figure 5. External VCO Component Connections

1

gm =

8kΩ

SIGN

CHANGER

+
–

TO
SPEED FB

F/R

4kΩ

4kΩ

4kΩ

F/R

COMMUTATION

STATE MACHINE

Figure 6. Back EMF Sampler Detailed Block Diagram

9

ML4425

FUNCTIONAL DESCRIPTION

BACK EMF SENSING PLL COMMUTATION CONTROL

Three blocks form a phase locked loop that locks the
commutation clock onto the back EMF signal: the
commutation state machine, the voltage controlled
oscillator, and the back EMF sampler. The complete phase
locked loop is illustrated in Figure 7. The phased locked
loop requires a lead lag filter that is set by external
components on SPEED FB. The components are selected
as follows:




K



OS

C

SPEEDFB

RM

SPEEDFB

CC M

SPEEDFB SPEEDFB21

START-UP SEQUENCE

025

=

.

1

= 

2

1



M






d



ln




100 1

05











N

d





ln









100



NK M

-

SO

1=-

(Continued)



f

VCO

0







2











5

2

2



f

VCO

1

(6a)

(6b)

(6c)

C

SPEEDFB1

20

SPEED

500nA

B

C

FB

V

DD

VOLTAGE

CONTROLLED

OSCILLATOR

PHASE

LOCKED

LOOP

FB A

22

FB B

23

FB C

24

BACK

EMF

SAMPLER

R

A

F

E

D

COMMUTATION
STATE MACHINE

R

SPEEDFB

C

SPEEDFB2

VCO/TACH

13

When power is first applied to the ML4425 and the motor
is at rest, the back EMF is equal to zero. The motor needs
to be rotating for the back EMF sampler to lock onto the
rotor position and commutate the motor. The ML4425 uses
an open loop start-up technique to bring the rotor from rest
up to a speed fast enough to allow back EMF sensing.
Start-up is comprised of three modes: align mode, ramp
mode, and run mode.

Align Mode (RESET)

Before the motor can be started, the rotor must be in a
known position. When power is first applied to the
ML4425, the controller is reset into the align mode. Align
mode turns on the output drivers LB, HA, and HC which
aligns the motor into a position 30 electrical degrees
before the center of the first commutation state. This is
shown as state R in the commutation states of Table 1.
Align mode must last long enough to allow the motor and
its load to settle into this position. The align mode time is
set by a capacitor connected to the CAT pin as shown in
Figure 8. CAT is charged by a constant 750µA current from
GND to 1.5 V until the align comparator trips to end the
align mode. A starting point for CAT is calculated as
follows:

-

tamp

 

75 10

.

AT

S

=

C

If the align time is not long enough to allow the rotor to
settle for reliable starting, then increase CAT until the
desired performance is achieved.

7

V

15

.

(7)

Figure 7. Back EMF Commutation Phase Locked Loop

Ramp Mode

At the end of align mode the controller goes into ramp
mode. Ramp mode starts commutating through the states
A through F as shown in Table 1. This ramps up the
commutation frequency, and therefore the motor speed,
for a fixed length of time. This allows the motor to reach a
sufficient speed for the back EMF sampler to lock
commutation onto the motor's back EMF. The amount of
time the ML4425 stays in ramp mode is determined by a
capacitor connected to the CRT pin as shown in Figure 8.
CRT is charged by a constant 750µA current from GND to

1.5 V until the ramp comparator trips to end the ramp
mode. This gives a fixed ramp time. CRT is calculated as
follows:

-

RT

=

p

IK N

MAX t

C

The rate at which the ML4425 ramps up the motor speed
is determined by a fixed 500µA current source on the
SPEED FB pin. The current sources charges up the PLL
filter components causing the VCO frequency to ramp up.
During ramp mode, the back EMF sampler is disabled to
allow control of the ramping to be set only by the 500µA
current source. The ramp based on the SPEED FB filter is
generally too fast for the motor to keep up, so a capacitor
from CRR to SPEED FB can be added to slow down the
ramping rate. The optimal ramp rate is based on the motor
and load parameters and is can be adjusted by varying
the value of CRR.

JampK

   

2510

7



3

V

(8)

10

FB A

FB B

FB C

C

750nA

BACK

EMF

SAMPLER

RR

C

AT

V

750nA

DD

1.5V

C

RT

C

DD

1.5V

AT

–
+

TO RESET INPUT

OF COMMUTATION

STATE MACHINE

V

C

RT

C

RR

–
+

500nA

V

DD

SPEED

FB

TO

SPEED FB

FILTER

C

VCO

Figure 8. ML4425 Start-up Circuitry for Controlling the Align and Ramp Times

VOLTAGE

CONTROLLED

OSCILLATOR

R

VCO

ML4425

VCO/TACH

Run Mode (Back EMF Sensing)

At the end of ramp mode the controller goes into run
mode. In run mode, the back EMF sensing is enabled and
commutation is now under the control of the phase locked
loop. Motor speed is now regulated by the speed control
loop.

PWM SPEED CONTROL

Speed control is accomplished by setting a speed
command at SPEED SET with an input voltage from 0 to

6.9V (V
determined by the external components R

). The accuracy of the speed command is

REF

VCO

and C

VCO

.

There are a number of methods that can be used to control
the speed command of the ML4425. One is to use a 10kW
potentiometer from V

to ground with the wiper

REF

connected to SPEED SET. If SPEED SET is controlled from
a microcontroller, one of its DACs can be used with V

REF

as its input reference.

The speed command is compared with the sensed speed
from SPEED FB through a transconductance error
amplifier. The output of the speed error amplifier is SPEED
COMP. SPEED COMP is clamped between one diode drop
above 3.9V (approximately 4.6V) and one diode drop
below 1.7V (approximately 1V) to prevent speed loop
“wind-up”. Speed loop compensation components are
connected to this pin as shown in Figure 9. The speed loop
compensation components are calculated as follows:

.

NV C

 

C

SC

R

SC

269

=

fK mf

+

SB e SB

fC



2

p

10

SB SC

=

MOTOR VCO

..

25 98696

2

t

2

(9a)

(9b)

Where fSB is the speed loop bandwidth in Hz.

FROM

SPEED FB

TO

GATING
LOGIC &
OUTPUT
DRIVERS

LIMIT

10kΩ

V

REF

SPEED SET

R

SC

C

SC

C

T

SPEED COMP

C

T

1.7V

+
–

20kHz

3.9V

–

+

1.7V

PWM ON/OFF

FROM I

ONE-SHOT

Figure 9. Speed Control Loop Component Connections

The voltage on SPEED COMP is compared with a ramp
oscillator to create a PWM duty cycle. The PWM ramp
oscillator creates a sawtooth function from 1.7V to 3.9V
as shown in Figure 9. A negative clamp at one diode drop
below 1.7V (approximately 1V) starts the oscillator on
power up. The frequency of the ramp oscillator is set by a
capacitor to ground C

and is selected using the

IOS

following equation:

1



50

m

A

(10)

.

V

C

T

Where f

f

PWM

=

24

is the PWM frequency in Hz. The PWM duty

PWM

cycle from the speed control loop is gated the current
limit one shot that controls the LA, LB, and LC output
drivers.

11

ML4425

2

4

3

9

10

HA

HB

HC

LA

LB

GATING

LOGIC

&
OUTPUT
DRIVERS

–
+

1.4V

9.5V

25

BRAKE

V

DD

4kΩ

14

V

DD

28

GND27R

REF

11

LC

REFERENCE

18

UV FAULT

7

V

REF

FROM

COMMUTATION

STATE MACHINE

FROM

SPEED CONTROL LOOP

& CURRENT LIMIT

+

–

FUNCTIONAL DESCRIPTION

(Continued)

CROSS CONDUCTION COMPARATOR

When the ML4425 goes from align mode into ramp mode,
there is a possibility of cross conduction in phase 3 of the
bridge power stage. This cross conduction can happen
when HC is on in the align mode shown as state R in
Table 1, and the controller transitions to state A in ramp
mode where HC is turned off and LC is turned on. Cross
conduction can appear due to the differences in turn on
and turn off times of the power devices. To solve this
problem, the LC output driver is gated off until the HC is
equal to V

– 3V as shown in Figure 10.

DD

BRAKING

When the BRAKE pin is pulled below 1.4V, the low side
output drivers LA, LB, and LC are turned on and the high
side output drivers HA, HB, HC are turned off. Braking
causes rapid deceleration of the motor and current
limiting is de-activated, and care should be taken when
using the BRAKE pin. BRAKE is has an internal 4kW pull­up as shown in Figure 10, and can be driven by a switch
to ground, an open collector or drain logic signal, or a TTL
logic signal.

Figure 10. Cross Conduction, Brake, and UVLO Circuits

UNDERVOLTAGE LOCKOUT

Undervoltage lockout is used to protect the 3-phase
bridge power stage from a low VDD condition.
Undervoltage is triggered at VDD of 9.5V or less and is
indicated by a TTL low output on the UV FAULT pin.
Undervoltage lockout also turns off all output drivers (LA,
LB, LC, HA, HB, and HC). The comparator that triggers
undervoltage lockout has 150mV of hystresis.

DESIGN CONSIDERATIONS

INTERFACING TO A 3-PHASE BRIDGE POWER STAGE

The ML4425 output drivers are configured to drive a 3
phase bridge power stage. For applications with buss
voltages from 12V up to 80V, level shifting circuitry can
be used to drive higher voltage P-channel MOSFETS for
the high side switches as shown in Figure 11.

The most flexible configuration is to use high side drivers
to control N-Channel MOSFETs (or IGBTs) which allows
applications from less than 12V up to 600V. Figure 12
shows the interface between the ML4425 and IR2118 high
side drivers from International Rectifier. This configuration
is capable of driving motors from busses of up to 320V.
The BRAKE pin can be pulsed prior to startup with an RC
circuit. This charges the bootstrap capacitors (C19, C20,
and C21) for the three high side drivers, allowing the reset
phase to operate normally. These capacitors must be sized
so that they stay sufficiently charged during the align
mode. Refer to AN-43 for additional applications
information on the ML4425.

12

V

BUSS

24V–80V

12V

C2

330µF

100V

2N6718

C3

1µF

C1

100nF

100V

Q1

R2

10kΩ

Q4

IRFR9120

Q2

2N6718

R3

10kΩ

Q5

IRFR9120

ML4425

R4

10kΩ

Q6

IRFR9120

Q3

2N6718

R12
2kΩ

R16

10kΩ

C9

100nF

100Ω

Q7

IRFR120

R1

470mΩ

2W

R13

2kΩ

Q8

IRFR120

R14

2kΩ

R15

1kΩ

Q9

IRFR120

MOTOR

C5

2.2nF

ML4425

C4

R20

137kΩ

R8 (RES1)

C14

C8

1µF

C16

330pF

R9 (RES1)

R17

10kΩ

C6

1µF

R19

80.5kΩ

R10 (RES1)

RUN

S1

BRAKE

C7

100nF

C15

470nF

I

SENSE

HA

HB

HC

SPEED COMP

C

C13

100nF

T

V

REF

SPEED SET

LA

LB

LC

I

LIMIT

VCO/TACH

V

DD

C17

1nF

C12

R7

R5

100Ω

R6

100Ω

R18

10kΩ

R21

787Ω

12V

C14
1µF

GND

R

REF

C

IOS

BRAKE

FB C

FB B

FB A

C

SPEED FB

C

UV FAULT

C

R

VCO

C

VCO

RR

RT

AT

Figure 11. Driving Lower Voltage Motors (12 to 80V)

13

ML4425

12V

V

BUSS

24V–80V

C5

330µF

400V

C16

100nF

25V

R6

100Ω

IR2118

V

CC

IN

HO

COM

NC

VB

VS

NC

D1

MUR150

C19

2.2µF
25V

R7

100Ω

C17

100nF

25V

IR2118

V

CC

IN

COM

NC

R8

100Ω

VB

HO

NC

VS

D2

MUR150

C20

2.2µF
25V

C18

100nF

25V

IR2118

V

CC

IN

COM

NC

VB

HO

VS

NC

D3

MUR150

C21

2.2µF
25V

D4 D5 D6

Q1

IRF720

R5

10kΩ

C3

100nF

100Ω

(3×1N5819)

R9

IRF720

R12

470mΩ

2W

R10

100Ω

Q2

R11

100Ω

C4

1nF

C15

100nF

Q3

IRF720

12V

R20

10kΩ

R19

787Ω

1µF

IR720

C6

Q4

Q5

IRF720

R1

1kΩ

I

SENSE

HA

HB

HC

SPEED COMP

C

T

V

REF

SPEED SET

LA

LB

LC

I

LIMIT

VCO/TACH

V

DD

C7

100nF

Q6

IRF720

ML4425

MOTOR

C1

2.2nF

RAMP COMP

SPEED FB

UV FAULT

GND

R

REF

C

IOS

BRAKE

FB C

FB B

FB A

C

RT

C

AT

R

VCO

C

VCO

C8

10nF

R18

137kΩ

R15 (RES1)

C13*

C10
1µF

C14

330pF

R14 (RES1)

R13 (RES1)

R17

10kΩ

C12

1µF

R16

80.6kΩ

BOOTSTRAP

PRE-CHARGE

CAPACITOR

RUN

S1

BRAKE

C11

100nF

C9

470nF

14

Figure 12. ML4425 High Voltage Motor Drive Application Circuit

ML4425

PHYSICAL DIMENSIONS

0.354 BSC
(9.00 BSC)

0.276 BSC
(7.00 BSC)

1

PIN 1 ID

9

0.032 BSC
(0.8 BSC)

inches (millimeters

Package: H32-7

32-Pin (7 x 7 x 1mm) TQFP

25

0.276 BSC
(7.00 BSC)

17

0.012 - 0.018
(0.29 - 0.45)

0.354 BSC
(9.00 BSC)

0.037 - 0.041
(0.95 - 1.05)

0.048 MAX

(1.20 MAX)

0º - 8º

0.003 - 0.008
(0.09 - 0.20)

0.018 - 0.030
(0.45 - 0.75)

SEATING PLANE

0.180 MAX

(4.57 MAX)

0.125 - 0.135
(3.18 - 3.43)

28

PIN 1 ID

1

1.355 - 1.365

(34.42 - 34.67)

0.045 - 0.055
(1.14 - 1.40)

0.015 - 0.021
(0.38 - 0.53)

Package: P28N

28-Pin Narrow PDIP

0.100 BSC
(2.54 BSC)

0.280 - 0.296
(7.11 - 7.52)

SEATING PLANE

0.020 MIN

(0.51 MIN)

0.299 - 0.325
(7.60 - 8.26)

0º - 15º

0.008 - 0.012
(0.20 - 0.31)

15

ML4425

PHYSICAL DIMENSIONS

0.699 - 0.713

(17.75 - 18.11)

0.050 BSC

(1.27 BSC)

0.024 - 0.034
(0.61 - 0.86)

(4 PLACES)

0.090 - 0.094
(2.28 - 2.39)

28

PIN 1 ID

1

inches (millimeters)

Package: S28

28-Pin SOIC

0.012 - 0.020
(0.30 - 0.51)

SEATING PLANE

0.291 - 0.301
(7.39 - 7.65)

0.095 - 0.107
(2.41 - 2.72)

0.398 - 0.412

(10.11 - 10.47)

0.005 - 0.013
(0.13 - 0.33)

0º - 8º

0.022 - 0.042
(0.56 - 1.07)

0.009 - 0.013
(0.22 - 0.33)

ORDERING INFORMATION

PART NUMBER TEMPERATURE RANGE PACKAGE

ML4425CP 0ºC to 70ºC 28-Pin PDIP (P28N)

ML4425CS 0ºC to 70ºC 28-Pin SOIC (S28)

ML4425CH (Obsolete) 0ºC to 70ºC 32-Pin TQFP (H32-7)

ML4425IP –40ºC to 85ºC 28-Pin PDIP (P28N)
ML4425IS –40ºC to 85ºC 28-Pin SOIC (S28)

ML4425IH (Obsolete) –40ºC to 85ºC 32-Pin TQFP (H32-7)

© Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.

Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;
5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897;
5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174; 5,767,653;. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending.

Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability
arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits
contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits
infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult
with appropriate legal counsel before deciding on a particular application.

16

DS4425-01

2092 Concourse Drive

San Jose, CA 95131

Tel: [phone]

Fax: [phone]

www.microlinear.com

7/6/98 Printed in U.S.A.